AD90774 Analog Devices, AD90774 Datasheet
AD90774
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... SHIFTER MULT ALU SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...
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ADSP-21161N KEY FEATURES (continued Bit On-Chip Dual-Ported SRAM (0.5 M Bit Block 0, 0.5 M Bit Block 1) for Independent Access by Core Processor and DMA 200 Million Fixed-Point MACs Sustained Performance Dual Data Address Generators (DAGs) with ...
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... Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 GENERAL DESCRIPTION The ADSP-21161N SHARC DSP is the first low cost derivative of the ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161N is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARCs in SISD (Single Instruction, Single Data) mode ...
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ADSP-21161N The ADSP-21161N continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include bit dual ported SRAM memory, host processor interface, I/O processor that ...
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ADSP-21161N Family Core Architecture The ADSP-21161N includes the following architectural features of the ADSP-2116x family core. The ADSP-21161N is code compatible at the assembly level with the ADSP-21160, ADSP- 21060, ADSP-21061, ADSP-21062, and ADSP-21065L. SIMD Computational Engine The ADSP-21161N contains ...
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ADSP-21161N PM bus, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. IOP REGISTERS LONG WORD ADDRESSING INTERNAL MEMORY NORMAL WORD ADDRESSING SPACE SHORT ...
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... SDRAM devices. Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21161N processor to monitor and control the target board processor during emulation ...
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ADSP-21161N CLOCK RESET Figure 4. Shared Memory Multiprocessing System or DMA-transferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowl- edge handshaking controls link port transfers. Transfers are programmable as either transmit or receive. ...
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... The VisualDSP++ project management environment lets pro- grammers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader, 1 VisualDSP registered trademark of Analog Devices, Inc. –9– ADSP-21161N – ), and external DDINT ) powers the ADSP-21161N’ ...
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... Designing an Emulator-Compatible DSP Board (Target) The Analog Devices DSP Tools family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. The emulator ...
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... Figure 8. JTAG Pod Connector Dimensions TDI TDO Figure 9. JTAG Pod Connector Keep-Out Area the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68”. This document is updated regularly to keep pace with improvements to emulator support. Additional Information This data sheet provides a general overview of the ADSP-21161N architecture and functionality ...
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ADSP-21161N PIN FUNCTION DESCRIPTIONS ADSP-21161N pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously ...
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Table 2. Pin Function Descriptions (continued) Pin Type Function WR Memory Write Low Strobe asserted when ADSP-21161N writes a word to external I/O/T memory or IOP registers of other ADSP-21161Ns. External devices must assert WR for writing to ...
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ADSP-21161N Table 2. Pin Function Descriptions (continued) Pin Type Function HBG Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor I/O may take control of the external bus. HBG is asserted (held low) by the ADSP-21161N ...
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Table 2. Pin Function Descriptions (continued) Pin Type Function FSx I/O Transmit or Receive Frame Sync (Serial Ports 3). The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. It ...
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ADSP-21161N Table 2. Pin Function Descriptions (continued) Pin Type Function BMS I/O/T Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins (see hardwired. For Host and PROM boot, DMA channel 10 (EPB0) ...
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... I/A after power-up or held low for proper operation of the ADSP-21161N. TRST has internal pull-up resistor. EMU O (O/D) Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has internal pull-up resistor Core Power Supply. Nominally +1 and supplies the DSP’s core processor (14 pins). ...
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ADSP-21161N SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Internal (Core) Supply Voltage DDINT AV Analog (PLL) Supply Voltage DD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL T Case Operating Temperature ...
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Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10, BRST. 10 pull-ups: RD, WR, DMAG1, DMAG2, PA. Applies to three-statable pins with Applies to three-statable ...
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ADSP-21161N TIMING SPECIFICATIONS The ADSP-21161N’s internal clock switches at higher frequen- cies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system ...
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Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect sta- ...
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ADSP-21161N Table 7. External Power Calculations (3.3 V Device) Pin Type Number of Pins Address 11 MSx 4 SDWE 1 Data 32 SDCLK0 1 Note that the conditions causing a worst-case P from those causing a worst-case P . Maximum ...
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Power-Up Sequencing – Silicon Revision 1.2 The timing requirements for DSP startup for silicon with revision 1.2 are given in Table 9. Table 9. Power-Up Sequencing for Revision 1.2 (DSP Startup) Parameter Timing Requirements RESET Low Before V t RSTVDD ...
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ADSP-21161N protection circuitry. With this technique, if the 1.8 V rail rises ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail along with the 1.8 V rail. Clock Input In systems that use multiprocessing or ...
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Reset Table 11. Reset Parameter Timing Requirements RESET Pulsewidth Low t WRST RESET Setup Before CLKIN High t SRST 1 Applies after the power-up sequence is complete. 2 Only required if multiple ADSP-21161Ns must come out of reset synchronous to ...
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ADSP-21161N Timer Table 13. Timer Parameter Switching Characteristic t CLKIN to TIMEXP DTEX CLKIN t DTEX TIMEXP Flags Table 14. Flags Parameter Timing Requirement t FLAG11–0 Setup Before CLKIN SFI IN t FLAG11–0 Hold After CLKIN HFI IN Delay After ...
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Memory Read – Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21161N is the bus master accessing external memory space in asynchro- nous access mode. Table ...
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ADSP-21161N Memory Write – Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21161N is the bus master accessing external memory space in asynchro- nous access mode. ...
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Synchronous Read/Write – Bus Master Use these specifications for interfacing to external memory systems that require CLKIN, relative to timing or for accessing a slave ADSP-21161N (in multiprocessor memory space). When accessing a slave ADSP-21161N, these switching characteristics Table 17. ...
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ADSP-21161N Synchronous Read/Write – Bus Slave Use these specifications for ADSP-21161N bus master accesses of a slave’s IOP registers in multiprocessor memory space. The bus master must meet these (bus slave) timing requirements. Table 18. Synchronous Read/Write – Bus Slave ...
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Host Bus Request Use these specifications for asynchronous host bus requests of an ADSP-21161N (HBR, HBG). Table 19. Host Bus Request Parameter Timing Requirements HBG Low to RD/WR/CS Valid t HBGRCSV HBR Setup Before CLKIN t SHBRI HBR Hold After ...
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ADSP-21161N Multiprocessor Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-21161Ns (BRx). Table 20. Multiprocessor Bus Request Parameter Timing Requirements BRx, Setup Before CLKIN High t SBRI BRx, Hold After CLKIN High t HBRI PA Setup ...
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Asynchronous Read/Write – Host to ADSP-21161N Use these specifications for asynchronous host processor accesses of an ADSP-21161N, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-21161N, the host can drive the RD and ...
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ADSP-21161N READ CYCLE ADDRESS/CS RD DATA (OUT) REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 26. Asynchronous Read/Write – Host to ADSP-21161N t SADRDL ...
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Three-State Timing – Bus Master, Bus Slave These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master tran- sition cycles (BTC) ...
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ADSP-21161N CLKIN SBTS t t MIENA, MEMORY INTERFACE t DATEN DATA t ACKEN ACK CLKIN t CDCEN CLKOUT HBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE) Figure 27. Three-State Timing – Bus Master, ...
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DMA Handshake These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is ...
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ADSP-21161N CLKIN t SDRC DMARx DMAGx TRANSFERS BETWEEN ADSP-21161N INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2116x TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-21161N) TRANSFERS BETWEEN EXTERNAL DEVICE AND 1 EXTERNAL MEMORY (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE ...
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SDRAM Interface – Bus Master Use these specifications for ADSP-21161N bus master accesses of SDRAM: Table 25. SDRAM Interface – Bus Master Parameter Timing Requirements t Data Setup Before SDCLK SDSDK t Data Hold After SDCLK HDSDK Switching Characteristics t ...
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ADSP-21161N CLKIN t DSDK1 SDCLK t SDSDK DATA(IN) t DCADSDK t SDENSDK DATA(OUT) t DCADSDK 1 CMND ADDR (OUT) t SDCEN 1 CMND (OUT) ADDR (OUT) t SDAEN CLKIN t SDSDKEN SDCLK CLKOUT SDCLK (IN) 2 CMND (IN) 1 COMMAND ...
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Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay ...
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ADSP-21161N Table 28. Link Ports – Transmit Parameter Timing Requirements t LACK Setup Before LCLK High SLACH t LACK Hold After LCLK High HLACH Switching Characteristics t Data Delay After LCLK High DLDCH t Data Hold After LCLK High HLDCH ...
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Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and ...
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ADSP-21161N Table 33. Serial Ports – Enable and Three-State Parameter Switching Characteristics t Data Enable from External Transmit SCLK DDTEN t Data Disable from External Transmit SCLK DDTTE t Data Enable from Internal Transmit SCLK DDTIN t Data Disable from ...
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DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE t SCLKIW SCLK t DFSI t t HOFSI SFSI FS t SDRI D A NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS ...
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ADSP-21161N SCLK SCLK Figure 33. Serial Ports EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE ...
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SPI Interface Specifications Table 35. SPI Interface Protocol – Parameter Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Set-up SSPIDM Time) t SPICLK Last Sampling Edge to Data Input Not Valid HSPIDM t Sequential Transfer Delay SPITDM ...
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ADSP-21161N FL AG3 UTPUT ) SPICLK ( UTPUT ) SPIC LK (CP = ...
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SPIDS (INPUT) SPICLK ( (INPUT SPICLK ( (INPUT MISO (OUTPUT ) CPH ASE = ...
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ADSP-21161N JTAG Test Access Port and Emulation Table 37. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System ...
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Output Drive Currents Figure 37 shows typical I-V characteristics for the output drivers of the ADSP-21161N. The curves represent the current drive capability of the output drivers as a function of output voltage 3.47V, –40°C DDEXT ...
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ADSP-21161N 0.0835X - 2.42 5 NOMINAL – 120 LOAD CAPACITANCE – pF Figure 41. Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature) 16.0 14 ...
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METRIC MBGA PIN CONFIGURATIONS Table 39. 225-Ball Metric MBGA Pin Assignments PBGA Pin Name Pin Number Pin Name TRST NC A01 BMSTR A02 TDI BMS A03 RPBA SPIDS A04 MOSI EBOOT A05 FS0 LBOOT A06 SCLK1 SCLK2 A07 D2B ...
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ADSP-21161N Table 39. 225-Ball Metric MBGA Pin Assignments (continued) PBGA Pin Name Pin Number Pin Name ADDR14 N01 ADDR13 ADDR15 N02 ADDR9 ADDR10 N03 ADDR8 ADDR5 N04 ADDR4 MS2 ADDR1 N05 MS0 SBTS N06 BR5 BR4 N07 BR2 BR1 N08 ...
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The ADSP-21161N comes BALL INDICATOR TOP VIEW 1.85 MAX (SEE NOTE 1) NOTES: 1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MO-192-AAF2, EXCEPT FOR HEIGHT AND THICKNESS DIMENSIONS NOTED. 2. ACTUAL POSITION OF ...
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ADSP-21161N Revision History Location 5/03—Changed from Rev Rev. A Changes to: KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Location Changes to: Table ...
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