MT92210BG Zarlink Semiconductor, MT92210BG Datasheet
MT92210BG
Related parts for MT92210BG
MT92210BG Summary of contents
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Features • 1023 full-duplex PCM or ADPCM voice channels over IP/UDP/RTP connections • RTP packaging optional in IP/UDP connection • Supports IP version 4 and version 6 • Supports IP over Ethernet, ATM (AAL5) or POS • Support Ethernet II, ...
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... The verb “to set” means to put one or multiple bits to ‘1’. • All addresses are specified in hexadecimal and point to bytes. Addresses are converted from bytes to words to double words using the little endian format, unless otherwise specified. ii Zarlink Semiconductor Inc. ...
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... Clocking (Chapter 11.0) describes the clocks used for the Network Interface and the SAR portion of the device. • Pin-out is in Chapter 12.0. • Electrical Characteristics (Chapter 13.0) describes the electrical characteristics of all the interfaces. • Register List and Memory Map are contained in the MT92210 Design Manual. Zarlink Semiconductor Inc. MT92210 iii ...
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... Packet Reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.0 RX/TX Data Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 RX Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 TX Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.0 Packet Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1 Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2 Packet Parsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 Look- 6.4 Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5 Post-search Confirmation 7.0 Packet Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.1 Service Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 Event Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3 RTP Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.1 TX RTP Header Structure 7.3.2 Header Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.3 Packet Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table of Contents Zarlink Semiconductor Inc. MT92210 v ...
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... AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.5.1 Intel/Motorola CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.5.2 UTOPIA / POS-PHY / Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.5.3 H.110 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.5.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Appendix 179 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Appendix 181 HDLC Format, Including Zero-Insertion and Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Appendix 183 Standards & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 vi Table of Contents Zarlink Semiconductor Inc. ...
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... Data Sheet Appendix .185 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table of Contents Zarlink Semiconductor Inc. MT92210 vii ...
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... Figure Silence Suppression Structure: External VAD & Spectral Energy Forwarding Figure Disassembly Event Report Queue Figure RTP Connection Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 47 - Payload Type/Marker Bit Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure Disassembly Event Report Queue - RTP Connection Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure RTP xxPCM Channel Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 List of Figures Zarlink Semiconductor Inc. MT92210 ix ...
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... Figure 88 - Multiplexed CPU Interface - Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 89 - UTOPIA / POS-PHY / Ethernet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 90 - H.110 Input Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 91 - H.110 Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 92 - External Memory Timing (both SSRAM and SDRAM 177 Figure 93 - Supported RTP HDLC Packet Format (after zero extraction 181 x List of Figures Zarlink Semiconductor Inc. ...
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... Table 41 - Fields and Description 117 Table 43 - Fields and Description 120 Table 44 - Fields and Description 121 Table 45 - Fields and Description 123 Table 46 - Fields and Description 125 Table 47 - Fields and Description 129 Table 48 - Clock Divisor X and 135 Table 49 - Clock Divisor 136 List of Tables Zarlink Semiconductor Inc. MT92210 xi ...
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... Table 50 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 Table Write Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Table Read Access Time .172 Table 53 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Table 54 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Table 55 - Fields and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 xii List of Tables Zarlink Semiconductor Inc. ...
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... Policing on HDLC channels and CPU channels protects against misbehaving connections • PCM, ADPCM, HDLC and CPU mini-packets can all be transported on the same connection with chip's RTP engine to guarantee consistency among the packets • In the disassembly module, synchronization deltas allow multiple independent connections to be Zarlink Semiconductor Inc. MT92210 13 ...
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... Translation between u-law and A-law on a per connection basis • Support of ADPCM at 40, 32 kbps • Dual time-slot mode allows dynamic, error-free switching between PCM and ADPCM formats with silence suppression • Support of HDLC encapsulated mini-packets with asynchronous timing 14 Zarlink Semiconductor Inc. ...
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... Transmission of voice to secondary port allows H.110/PCM bridging when coupled with AAL5 SAR • Pin-out allows designs that support Ethernet, ATM and Packet over SONET with only software configuration deciding on the link layer used Zarlink Semiconductor Inc. MT92210 15 ...
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... For this example Interrupt2 is employed and the CPU module will be the source of the interruption. 2.2.1.1 Interrupt Initialization Set interrupt polarity, register interrupt2_conf[15:14], address 216h. Enable Inetrrupt2 for the CPU module by setting bit 0 in inetrrupt2_enble register (21Ch). The MT92210 will generate an interrupt on interrupt2 pin according to the modules enabled in inetrrupt2_enable. Zarlink Semiconductor Inc. MT92210 17 ...
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... Interrupt1 Enable (0218h) interrupt1_active_level 18 b10 Status Bits internal interrupt AND OR Interrupt Enable Bits Global Service Register (0210h) AND OR Interrupt interrupt2_active_level Frequency Controler interrupt1 Figure 2 - Internal Interrupt Network Zarlink Semiconductor Inc. b0 AND Interrupt2 Enable (021Ch) OR interrupt2 ...
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... Table 2 - CPU Interface Mode Selection Zarlink Semiconductor Inc. MT92210 DIRECT_ b DATA PIN ACCESS cpu_d[15:0] cpu_a_das cpu_d[15:0] cpu_a_das cpu_d[7:0] cpu_a_das cpu_d[7:0] cpu_a_das cpu_d[15:0] ...
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... Table 4 - Read/Write Data Register (004h) Type Reset RW 0000h Extended address bits 32:20. extended_a[32:0] points to bytes. Used both for extended indirect and extended direct accesses. RO 000 Table 5 - Address High Register (008h) Zarlink Semiconductor Inc. Description Description Description ...
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... Some bits in this register are not used in direct accesses. When operating the CPU interface with a 16 bit data bus, only bits 19:16 are used. When operating the CPU interface with an 8-bit data bus, only bits 19:15 are used. Table 6 - Address Low Register (00Ah) Zarlink Semiconductor Inc. MT92210 Description 21 ...
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... Set active levels for interrupt pins in the Main Registers (214h, 216h). 11. Configure external memories in the Main Registers (230h, 232h, 234h, 236h, 240h). 12. Set Bit 1 (nreset_chip) in CPU Register 100h. 13. Configure all the other registers. 14. Set Bit 2 (nreset_network) in CPU Register 100h. 22 Zarlink Semiconductor Inc. ...
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... Buffer 2 TX Link A LP Packet Buffer Note: Only one type for port A is supported at once (UTOPIA, Ethernet or POS-PHY) TX Link A Raw Cell LP Buffer 3 Figure 3 - Network Interface Buffering Zarlink Semiconductor Inc. MT92210 rxb_clk Clock Net RXB UTOPIA RX B UTOPIA Input FIFO RX ATM 128 x 16 ...
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... Payload Payload Payload Payload Payload Payload Payload Payload Payload Payload Payload Payload Multicast Sum Figure 5 - Packet Block Format Zarlink Semiconductor Inc. b12 b11 b10 Payload Payload Payload Payload Payload Payload Payload Payload Payload ...
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... Used in TX. When packet is queued in multiple TX queues this is decremented each time the packet is sent and the TX queue that decrements frees the cell memory. Table 7 - Packet Block Format Table n size. Note that while handles may be copied to a new Zarlink Semiconductor Inc. MT92210 25 ...
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... Blocks in Queue [18:0] Service Block Fill [18:2] Figure 6 - Packet Handler Memory Description Table 8 - Handle Queue Descriptor Zarlink Semiconductor Inc. b12 b11 b10 Handle Queue Base Address & Size [20:11] Handle Write Pointer [14:0] ...
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... Figure 7 - Handle Queue and Handle Format b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 RTD Blocks in Packet[10:0] Figure 8 - Basic Handle Format Zarlink Semiconductor Inc. HRP HWP b12 b11 b10 SOP Handle[18:0] EOP Handle[18:0] ...
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... Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload PN Figure 9 - Raw Cell Format (used cell) Description Table 9 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 AAL5 VC Number [15:0] b3 ...
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... Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Cell Payload Figure 10 - Raw Cell Format (free cell) Description Points to the next free cell in SSRAM. Table 10 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 ...
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... Format of 8 Read Pointer Queue b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 Figure 11 - Cell Handler Memory Zarlink Semiconductor Inc. Reserved Reserved b12 b11 b10 Read FIFO Cell Base Address [20:6] Read FIFO Cell Base Address [20:6] ...
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... SONET. In addition, it has a secondary port (Port B) that is always configured to operate as an ATM port. Port B can be used to interoperate with a secondary data SAR daisy chain several MT92210 devices together onto a single network connection. By keeping the same secondary port configuration independently of the mode in which Zarlink Semiconductor Inc. MT92210 31 ...
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... VC number AAL5. The routing can be performed differently for normal and OAM cells typical application, OAM cells will be routed to one of the raw cell queues, while user cells will be sent to an AAL5 VC. The format of the look-up table entries is described below: 32 Zarlink Semiconductor Inc. ...
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... TX Link A Raw Cell Buffer 3; “xxxx1xxxx” Link B Raw Cell Buffer 0; “xxx1xxxxx” Link B Raw Cell Buffer 1; “xx1xxxxxx” CPU Raw Cell Buffer; “x1xxxxxxx” = reserved; “100000000” = AAL5 VC; Table 11 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 b9 b8 ...
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... When the primary network interface is configured as Ethernet or Packet over SONET, a single Reassembly structure is used and all packets are routed to this structure. Since Ethernet and Packet over SONET do not break down packets, interleave them, or carry several packets over different VC, the packets always arrive contiguously, thus not requiring more than 1 structure. 34 Zarlink Semiconductor Inc. ...
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... AIP ER P CRC-32 Connection Packet Count Connection Cell Count [23:0] Connection Packet Byte Count Flow Table Pointer [26:3] Figure 15 - Packet Reassembly Structure Zarlink Semiconductor Inc. Register A20h Ethernet/POS port Packet Reassembly Struct b12 b11 b10 ...
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... This counter excludes the Next Cell Handle, since this handle has been seized for a cell that has not yet arrived. Next Cell Handle Pointer to the block that has been pre-allocated for storing the next cell payload when it is received. 36 Description Table 12 - Fields and Description Zarlink Semiconductor Inc. ...
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... VC on which the packet is carried (in the case of ATM). This field can be overridden later on by protocols that allow VCs to carry packets on multiple subnets, such as LANEv2 or MPOA. The Flow Table Pointer points to a single bit in SSRAM C. Description Table 12 - Fields and Description Zarlink Semiconductor Inc. MT92210 37 ...
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... Cells that are tagged as non-AAL5 pass by the packet reassembly process but are routed immediately to their own destination, which is already known because it was indicated in the UTOPIA look-up table. These cells may be sent back onto one of the TX links, or they may be routed directly to the CPU. Zarlink Semiconductor Inc. MT92210 39 ...
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... A = Ethernet/ POS Legend: Structure in Internal Memory Structure in SSRAM A Structure in SSRAM B Structure in SSRAM C Structure in SDRAM C Figure Flow 1 Zarlink Semiconductor Inc. UTOPIA look-up table (1 per port) UTOPIA0 UTOPIA RX B From link B input FIFO (global) UTOPIA look-up UTOPIA RX A input FIFO ...
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... Profile) ID1 type) ID2 Identifi- cation Key (pre- Identification CRC) Binary Tree Key CRC + Search hashing RTP Data Figure Flow 2 Zarlink Semiconductor Inc. MT92210 Profile Next Memory Header (Option + Memory TOS) (global) (global) ID1 ID4 Packet Identification Packet ...
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... Packet Disassembly Process: Performs dejittering on xxPCM data, copies payload into circular buffer, performs policing on HDLC & CPU channels, reports errors & events in the Event Report Queue. Figure Flow 3 Zarlink Semiconductor Inc. Payload Type/Marker Bit Table (1 per connection) PTM1 RX RTP Connection ...
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... TONEMEM0 TONEMEM0 Tone Copying Tone Copying Process Process SSRAM Tone SSRAM Tone Buffers (global, Buffers (global, 32 Pairs) 32 Pairs) Figure Flow 4 Zarlink Semiconductor Inc. MT92210 RX TDM RX TDM Process Process Low Latency Low Latency SDRAM Silence SDRAM Silence Loopback Loopback Buffer Memory ...
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... Structure (1 per Stream) TXTDM1 Stream) TXTDM1 TX Channel TX Channel TX TDM TX TDM Association Association Process Process Memory (1 entry Memory (1 entry per TSST) TXTDM0 per TSST) TXTDM0 TX xxPCM TX xxPCM Buffer Structure Buffer Structure (1 per Bearer) (1 per Bearer) TXTDM1 TXTDM1 Figure Flow 1 Zarlink Semiconductor Inc. ...
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... Process Assembly Event Queue (global) Service EVENTQ0-7 Indicator Process Service Indicator Table (up to 16, (1 entry per global) SERVTIM0 Figure Flow 2 Zarlink Semiconductor Inc. MT92210 Packet Assembly TX RTP Connection Identification Structure (1 per Counter Source Connection) (1 per SRC/DST ASSEM0-1 IP Address pair) TX Silence ...
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... TX link A HP Packet Copying Buffer Handles Process (global) NET6 TX link A LP Packet Buffer Handles (global) NET6 TX link B HP Packet Buffer Handles (global) NET6 Network CPU Packet TX link B LP Packet Buffer Handles Buffer Handles (global) NET6 (global) NET6 Figure Flow 3 Zarlink Semiconductor Inc. ...
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... A cell FIFO into contiguous packets which are then written in the TX link A Packet/Cell FIFO. Also takes care of all Ethernet/POS formatting, such as removing the LANEv1 header. TX link B Cell TX Link B FIFO (global) Copy Process Figure Flow 4 Zarlink Semiconductor Inc. MT92210 TX link link A Packet/Cell FIFO (global link B 47 ...
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... Initial Search Memory Entry No Match Structure (1 per (Hash Key packet type) Mask) (1 per Profile) Identification Binary Tree Key CRC + Search hashing Figure 24 - Packet Identification Zarlink Semiconductor Inc. Next Profile Header Memory Memory (Option + TOS) (global) (global) Identifi- cation Key (pre- Packet ...
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... IPv6 with Fragmented UDP Protocol/non-UDP Protocol/Invalid Protocol 7 IPvX (Other than version ELAN-ID Lookup 9 MPOA Look-up 10 MPLS Look-up Table 13 - Packet Types and Initial Search Structures 50 Packet Type Zarlink Semiconductor Inc. Initial Search Structure ID Key Address in SDRAM Format 1000h 3 1080h - 1100h 1 1180h 1 ...
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... IPv4 header as well as the “options” found in the hop-by-hop options header and the destination options b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 Match Packet Count [31:0] Match Byte Count [31:0] Next Profile Zarlink Semiconductor Inc. b12 b11 b10 RTD RUN MT92210 ...
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... UDP ports, and potentially the RTP synchronization source. The packet type determines which of the three identification key formats be selected. 52 b14 b13 b12 b11 b10 NH=1 NH=2 NH=3 NH=4 NH=249 NH=250 NH=251 NH=252 Figure 26 - Next Header Memory Description Table 14 - Fields and Description Zarlink Semiconductor Inc NH=5 NH=6 NH=7 NH=253 NH=254 NH=255 ...
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... Flow Table Bit Pointer [23:0] Flow Table Bit Pointer [23:0] Third dword of packet - SSRC [31:0] / ELAN-ID [31:0] Third dword of packet - SSRC [31:0] / ELAN-ID [31:0] MPLS Shim [19:0] MPLS Shim [19:0] MPOA Tag [31:0] MPOA Tag [31:0] Zarlink Semiconductor Inc. b13 b13 b12 b12 b11 b11 b10 b10 b9 b9 ...
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... N*16 to N*16+15, where N is the profile entry number. In this way, all 256 values for the options are treated. These values are not in any way linked to the profile; they just reside in the same memory. Table 15 - Fields and Description Zarlink Semiconductor Inc. b13 b12 b11 b10 ...
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... Table 15 - Fields and Description b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 Figure 29 - Flow Table Zarlink Semiconductor Inc. MT92210 b12 b11 b10 I253 b1 ...
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... Table 17 - Profile Default Post-Search Structure 56 Description Table 16 - Fields and Description Profile Default Post-Search Structure Address in SDRAM 1800h 1880h 1900h 1980h 1A00h 1A80h 1B00h 1B80h 1C00h 1C80h 1D00h 1D80h 1E00 1E80 1F00 1F80 Zarlink Semiconductor Inc. ...
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... Register F18h points to the root node of binary tree. This is the format of the binary tree nodes: b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 FFFFh Match Packet Count [31:0] Match Byte Count [31:0] Next Profile (Refer to Table 19 for field descriptions) Zarlink Semiconductor Inc. b13 b12 b11 b10 FFFFh RTD RUN MT92210 b2 ...
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... Header CRC Key [55:32] Header CRC Key [31:0] First Post-Search Confirmation Structure Address [24:7] Figure 31 - Binary Tree Node Description Table 18 - Fields and Description Zarlink Semiconductor Inc. b12 b11 b10 Right Address [19: ...
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... The format of the post-search confirmation structure is indicated in the next figure. Zarlink Semiconductor Inc. MT92210 59 ...
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... Identification Key Dword 9 Flow Table Pointer [23:0] Match Packet Count [31:0] Match Byte Count [31:0] Next Profile LHR New ATM Header HP [31:0] CPI HP [7:0] New ATM Header LP [31:0] CPI LP [7:0] Figure 32 - Post-Search Conformation Structure Zarlink Semiconductor Inc. b13 b12 b11 b10 RTP Connection Structure Base Address [20:5] ...
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... This index points to an entry within the Flow table that corresponds to the Destination IP Flow Table) address of this packet. Note that the old Flow Table Pointer will be used to look-up the IP Address Index, even if the Flow Table Pointer is changed by this structure. Description Table 19 - Fields and Description Zarlink Semiconductor Inc. MT92210 61 ...
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... Then the chip will repeat the above search procedure with using the Destination IP address and the Destination UDP port, and come back to the matching post-search confirmation structure. This time, the required destination is the packet disassembly module. Thus the packet is sent to the disassembly module and the next packet can be treated. 62 Description Table 19 - Fields and Description Zarlink Semiconductor Inc. ...
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... Silence suppression can only be used with connections carrying a single channel. The service timers are configured internal memory that contains 16 entries. The format of this internal memory is the following: Zarlink Semiconductor Inc. MT92210 63 ...
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... Service Timer Descriptor 13 Service Timer Descriptor 14 Service Timer Descriptor 15 b11 b10 Indicators per Frame Service Timer Base Address [20:5] Next Indicator to be Read [15:0] Last Indicator Number [15:0] Figure 33 - Service Timer Control Memory Table 20 - Fields and Description Zarlink Semiconductor Inc ...
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... Indicator 0 +4 Indicator 1 +8 Indicator 2 Indicator N-3 Indicator N-2 Indicator N 65536} Start Boundary = 16 bytes b11 b10 b11 b10 Serv Timer # Assembly Structure Base Address [20:6] Table 21 - Service Timer Zarlink Semiconductor Inc. MT92210 ...
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... For example, the sequence number will be incremental across all packets on an IP/RTP connection, not just on voice packets generated by the chip. 66 Description +0 Assembly Event 0 +10 Assembly Event 1 +20 Assembly Event 2 +(N-3)*10h Assembly Event N-3 +(N-2)*10h Assembly Event N-2 +(N-1)*10h Assembly Event N {1024, 2048, 4096} Start/Cross Boundary = {16K, 32K, 64K} bytes Figure 34 - Assembly Event Queue Zarlink Semiconductor Inc. ...
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... Local Bus Time Stamp during which the HDLC packet completed. b12 b11 b10 Assembly Structure Base Address [20:6] CPU Packet Base Address [20:5] TDM Write Pointer [13:0] CPU Packet Length [10:0] Buf Size Time Stamp [31:16] Time Stamp [15:0] Description Table 22 - Fields and Description Zarlink Semiconductor Inc. MT92210 ...
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... Table 23 - Fields and Description b13 b12 b11 b10 Assembly Structure Base Address [20:6] CPU Packet Base Address [20:5] TDM Write Pointer [13:0] Buf Size CPU Packet Length [10:0] Time Stamp [31:16] Time Stamp [15:0] Zarlink Semiconductor Inc Description ...
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... UDP header is always 8 bytes, while the link header can end on any byte boundary. In the structure, padding bytes and will be added to the link header: it must always end on a dword Description Table 24 - Fields and Description Zarlink Semiconductor Inc. MT92210 69 ...
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... HDLC/CPU packets), or the first 12 bytes of RTP header for PCM packets, are copied into external memory. For HDLC/CPU channel carrying RTP, the first 12 bytes will represent the mandatory fields of the RTP 70 14 identification values can be contained in external memory, and each Zarlink Semiconductor Inc. ...
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... Second Word of Last RTP Packet Sent Third Word of Last RTP Packet Sent Fourth Word of Last RTP Packet Sent Fifth Word of Last RTP Packet Sent Sixth Word of Last RTP Packet Sent Figure RTP Connection Structure Zarlink Semiconductor Inc ...
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... Word of Last RTP Packet Record of first 6 words of last transmitted RTP payload. These fields can be used Sent to monitor what is being sent on this connection. Note This structure must begin on a 64-byte boundary. 72 Description Table 25 - Fields and Description Zarlink Semiconductor Inc. ...
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... Fourth Word of Last RTP Packet Sent Fifth Word of Last RTP Packet Sent Sixth Word of Last RTP Packet Sent Bearer 1 - Circular Buffer Base Address [20:9] Bearer 2 - Circular Buffer Base Address [20:9] Bearer N-2 - Circular Buffer Base Address [20:9] Bearer N-1 - Circular Buffer Base Address [20:9] Zarlink Semiconductor Inc ...
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... Bearers For each bearer in this xxPCM channel, a single circular buffer base address must be specified in one of these extension words. All xxPCM channels will have between 1 and 255 bearers, thus between 1 and 255 extension words. 74 Definition Table 26 - Fields and Description Zarlink Semiconductor Inc. ...
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... TX Link A LP; “xxx1xxxxx” Link B LP; “xxxx1xxxx” Link B HP; “xxxxx1xxx” = reserved; “xxxxxx1xx” = Network CPU Packet Buffer; “xxxxxxx1x” = reserved; “000000001” = Packet Identifier. Table 27 - Fields and Description Zarlink Semiconductor Inc Packet Type Header Length [9:2] ...
Page 76
... Header Words - Padding. Position in bytes of the first byte of the 802.3 Ethertype/Length with respect to Header word 0. Points to the dword of the IPv6 header, relative to Header Word 0, in which the packet identification field will be written. Table 27 - Fields and Description (continued) Zarlink Semiconductor Inc. Description ...
Page 77
... IP and UDP (or null) headers and transmitted as such. The assembly process, in addition to encapsulating the payload in these protocols, may perform some RTP functions. The Sequence Number Insert bit indicates whether the RTP sequence number should be generated by the structure or kept the payload. Zarlink Semiconductor Inc. MT92210 77 ...
Page 78
... Timestamp Insert bit to '0' and the Timestamp Offset well. By setting the Sequence Number Insert bit to '0' and making the timestamp transparent as described above, non-RTP packets can also be sent through HDLC or the CPU port. 78 Zarlink Semiconductor Inc. ...
Page 79
... CN packets at the beginning of silence periods, or whenever it decides to update also possible to configure it to suppress silence packets but never to send CN packets at any time. It also supports two modes in which it does not suppress packets. In the first one, it uses the marker bit in RTP to Zarlink Semiconductor Inc. MT92210 79 ...
Page 80
... The format of the TX Silence Suppression Structure varies according to whether or not the silence suppression decision is being taken internally being fed from an outside agent, and according to whether or not the generated CN packet will be a white energy value or a preprogrammed spectral value. 80 Zarlink Semiconductor Inc. ...
Page 81
... Energy Sum [31:16] Energy Sum [15:0] Energy Counter [12:0] Underrun Count [15:0] Energy Increase Threshold [7:0] amp_iir_fall_length ceiling_exp_half_life [15:0] floor_exp_half_life [15:0] ceiling_exp_start_v max_floor_level [12:0] min_threshold_while_talking [12:0] min_threshold_while_silent [12:0] flux_min_threshold [12:0] First Energy Period [12:0] Subsequent Energy Period [12:0] Zarlink Semiconductor Inc Maximum dB Value [6:0] Type 0 HPE BL holdover_counter [5:0] LS amp_iir [21:16] Energy Sum [38:32] ...
Page 82
... HP 10Hz Context [15:0] floor_exp [4:0] holdover_talk_counter [6:0] floor_latch [12:0] ceiling_latch [12:0] CTS LS amp_iir [15:0] ceiling_exp_half_life_counter [15:0] floor_exp_half_life_counter [15:0] Preprog Packet Length - 1 Preprogrammed Packet Pointer[16:2] Underrun Count amp_iir_fall_length ceiling_exp_half_life [15:0] floor_exp_half_life [15:0] ceiling_exp_start_v max_floor_level [12:0] min_threshold_while_talking [12:0] min_threshold_while_silent [12:0] flux_min_threshold [12:0] Zarlink Semiconductor Inc Type 0 HPE BL holdover_counter [5:0] amp_iir [21:16] Preprog Pnt [20:17] holdover_time [6:0] flux_ratio [4:0] ratio_while_talking [7:0] ...
Page 83
... Figure Silence Suppression Structure: External VAD & White Energy Estimation b13 b12 b11 b10 Correction [7:0] Minimum dB Value [6:0] Latched Energy Energy Sum [31:16] Energy Sum [15:0] Energy Counter [12:0] Underrun Count First Energy Period [12:0] Subsequent Energy Period [12:0] Zarlink Semiconductor Inc Maximum dB Value [6:0] Type 1 Energy Sum [38:32] Energy Increase Threshold MT92210 83 ...
Page 84
... Figure Silence Suppression Structure: External VAD & Spectral Energy Forwarding 84 b13 b12 b11 b10 Preprog Packet Length - 1 Preprogrammed Packet Pointer [16:2] Underrun Count Zarlink Semiconductor Inc Type 1 Preprog Pnt [20:17] ...
Page 85
... Should be initialized to zero by software. Should be initialized to zero by software. Last sent energy level exactly as it was sent in the comfort noise description packet. Accumulator used to estimate the idle line energy level. Must be initialized to zero by software. Table 28 - Fields and Description Zarlink Semiconductor Inc. Description MT92210 85 ...
Page 86
... Length of the preprogrammed comfort noise packet in bytes (minus 1). To send single byte comfort noise packets (the basic non-spectral mode), this field must be set to 00h. This field points to the location in SSRAM A at which the preprogrammed packet is located. Table 28 - Fields and Description (continued) Zarlink Semiconductor Inc. Description ...
Page 87
... CPU the HDLC bus). +0 Event 0 +10 Event 1 +(N-2)*10h Event N-2 +(N-1)*10h Event N-1 Figure Disassembly Event Report Queue Zarlink Semiconductor Inc. MT92210 87 ...
Page 88
... Structure Address from the RX connection structure and the RX Channel structure is read. This structure may be in the xxPCM, HDLC or CPU format. If the Type field in the RX Connection Structure associated to the RX Channel Structure is delete, then no RX Channel structure will be read and the packet will be deleted. Otherwise, the RX Channel structure is read and interpreted according to its type. 88 Zarlink Semiconductor Inc. ...
Page 89
... Network Jitter Integer [11:0] Received Packet Count [15:0] Received Octet Count [31:16] Received Octet Count [15:0] Type RX RTP Channel 0 Structure Address [20:5] Type RX RTP Channel 15 Structure Address [20:5] Figure RTP Connection Structure Description Table 29 - Fields and Description Zarlink Semiconductor Inc Net Jitter Fraction [3:0] ...
Page 90
... Report UUI/LI Combination to CPU through the RX Disassembly Event Report Queue (when set). Type Type of RX RTP Channel Structure. “000” = PCM + ADPCM; “001” = HDLC; “010” CPU; “111” = delete; others = reserved. 90 Description Table 29 - Fields and Description (continued) Zarlink Semiconductor Inc. ...
Page 91
... Table 29 - Fields and Description (continued) b13 b12 b11 b10 Entry 1 Entry 5 Entry 249 Entry 250 Entry 253 Entry 254 Figure 47 - Payload Type/Marker Bit Table Description Table 30 - Fields and Description Zarlink Semiconductor Inc Entry 3 Entry 2 Entry 7 Entry 6 Entry 251 Entry 255 MT92210 91 ...
Page 92
... RVM UCE BL1 RX RTP Connection Base Address [20:5] Payload Type [6:0] UDP Payload Length [7:0] Previous RTP Sequence Number [15:0] This RTP Sequence Number [15:0] Local Bus Time Stamp [31:16] Local Bus Time Stamp [15:0] Description Table 31 - Fields and Description Zarlink Semiconductor Inc ...
Page 93
... RTP is being used). This will more accurately allow the clock recovery process to reconstruct the relationship between mclk and the packet arrival rate. Description Table 31 - Fields and Description (continued) Zarlink Semiconductor Inc. MT92210 93 ...
Page 94
... Received Octet Count [15:0] Channel 0 - Circular Buffer Base Address [20:8] Channel 1 - Circular Buffer Base Address [20:8] Channel 2 - Circular Buffer Base Address [20:8] Channel 253 - Circular Buffer Base Address [20:8] Channel 254 - Circular Buffer Base Address [20:8] Figure RTP xxPCM Channel Structure Zarlink Semiconductor Inc ...
Page 95
... RPM bit will be cleared automatically by the hardware. When PDV monitoring is reset, the Minimum Delta and Maximum Delta are set to the delta of the first packet received in the new PDV monitoring period. Table 32 - Fields and Description Zarlink Semiconductor Inc. MT92210 95 ...
Page 96
... RX xxPCM Channel structure (to identify the channel to which the report structure belongs), the current Local Bus Timestamp and the current Remote Timestamp. 96 Table 32 - Fields and Description (continued) Zarlink Semiconductor Inc. ...
Page 97
... Reset Total Slip Offset Delta Completed. When this bit is set, the Total Slip Offset Delta has been reset in the Common PDV Absorption structure. Samples lost. When set, the Samples Lost[31:0] field is non-zero, meaning that one or many samples have been lost between packets. Table 33 - Fields and Description Zarlink Semiconductor Inc ...
Page 98
... Remote time stamp of the packet received that cause the generation of this report structure. Local Bus Time Stamp present at the time of reception of the packet that caused this report structure to be generated. Table 33 - Fields and Description (continued) Zarlink Semiconductor Inc. Description ...
Page 99
... Glitchless fallback. Because multiple chips can maintain delay consistency, channels and connections can be swapped from one chip to another without a single byte loss. The format of the RX RTP Common PDV Absorption structure is the following: n increments, between 2 ms and 256 ms. Zarlink Semiconductor Inc. MT92210 99 ...
Page 100
... Remote/Local Time Stamp Delta. Setting this bit gives controlling software full control of the de-jittering functionality. This field contains the local 32-bit bus time stamp that was present when the last received packet was processed by the PDV monitoring block. Table 34 - Fields and Description Zarlink Semiconductor Inc ...
Page 101
... This value is the current number of frames either added or dropped due to overruns and underruns. A positive number represents overruns and a negative number represents underruns. Note that underrun frames and overruns frames cancel-out in this field. Table 34 - Fields and Description (continued) Zarlink Semiconductor Inc. Description MT92210 101 ...
Page 102
... This field should be written to zero at initialization time. Write 0 for normal operation. all remote/local time stamp deltas are calculated with the following equation: delta = remote_packet_timestamp - local_bus_timestamp; Table 34 - Fields and Description (continued) Zarlink Semiconductor Inc. Description ...
Page 103
... HDLC Address [15:0] 0 Discharge Rate [5:0] Maximum Bucket Fill [15:0] Last Packet Local Time Stamp [23:8] I Current Bucket Fill [15:0] Received Packet Count [15:0] Received Octet Count [31:16] Received Octet Count [15:0] Figure RTP HDLC Channel Structure Zarlink Semiconductor Inc HDLC Control [7:0] Header Type CRC ...
Page 104
... Initialized bit. Written to zero by software channel initialization. Written to ‘1’ by hardware as soon at the first packet is received on this channel. Received Packet Count Total number of packets received on this channel so far. Every packet that gets to this structure will be included. 104 Description Table 35 - Fields and Description Zarlink Semiconductor Inc. ...
Page 105
... Channel Structure Address [20:5] RX Connection Structure Address [20:5] Packet Base Pointer [15:0] Packet Length [11:0] Local Bus Time Stamp [31:16] Local Bus Time Stamp [15:0] Description Table 36 - Fields and Description Zarlink Semiconductor Inc MT92210 105 ...
Page 106
... RX CPU Buffer Control Structure 511 b12 b11 b10 Circular Buffer Base [20:8] and Size Circular Buffer Write Pointer [15:0] Circular Buffer Read Pointer [15:0] Figure CPU Buffer Control Table Description Table 37 - Fields and Description Zarlink Semiconductor Inc Add ...
Page 107
... RX Circular Buffer Base [20:14] b12 b11 b10 Circular Buffer Base [20:15] 1 b12 b11 b10 Circ Buf Base [20:16 Figure Circular Buffer Base and Size Zarlink Semiconductor Inc ...
Page 108
... Discharge Rate [5:0] Maximum Bucket Fill [15:0] Last Packet Local Time Stamp [23:8] I Current Bucket Fill [15:0] Received Packet Count [15:0] Received Octet Count [31:16] Received Octet Count [15:0] Figure RTP CPU Channel Structure Description Table 38 - Fields and Description Zarlink Semiconductor Inc 0x00 ...
Page 109
... Received Octet Count Total number of bytes received on this channel so far. Every packet that gets to this structure will be included. This field increments by the UDP Length - 8 each time packet is received. Table 38 - Fields and Description (continued) Zarlink Semiconductor Inc. Description MT92210 109 ...
Page 110
... Zarlink Semiconductor Inc. ...
Page 111
... Entry ready for the next frame. 80000h Entry 0 80008h Entry 1 81FF0h Entry 1022 81FF8h Entry 1023 b13 b12 b11 b10 Stream/Buffer Tag TSST [11:0] Link to Next Entry Figure Channel Association Memory Description Table 39 - Fields and Description Zarlink Semiconductor Inc. MT92210 111 ...
Page 112
... The format of the TX TDM Control Memory is the following: 112 b10 PCM Buffer Number [9:0] b10 HDLC Stream Number [8:0] b10 LLL Buffer Number [6:0] Figure 58 - Buffer Tag Format Zarlink Semiconductor Inc ...
Page 113
... TX Circular Buffer Base [20:8] / SOP [14:5] Write Offset [10:0] Add [6:0] 1’s Cnt b12 b11 b10 Circular Buffer Base [20:9] / Size Indication N Figure TDM Control Memory Zarlink Semiconductor Inc Buf Size History & Valid ...
Page 114
... HT HDLC Type. ‘0’ = bit wise packet framing and escape code; ‘1’ = byte wise packet framing and escape code. 114 Description Table 40 - Fields and Description Zarlink Semiconductor Inc. ...
Page 115
... TX Circular Buffer Base [20:10] TX Circular Buffer Base [20:10] TX Circular Buffer Base [20:10] TX Circular Buffer Base [20:10] TX Circular Buffer Base [20:10] b12 b12 b11 b11 b10 b10 Circular Buffer Base [20:11] TX Circular Buffer Base [20:11] Zarlink Semiconductor Inc ...
Page 116
... HDLC Address LUT Base [20:6] for HDLC Stream 0 HDLC Address LUT Base [20:6] for HDLC Stream 1 HDLC Address LUT Base [20:6] for HDLC Stream 510 HDLC Address LUT Base [20:6] for HDLC Stream 511 Zarlink Semiconductor Inc SOP [7:5] ...
Page 117
... TX Connection Structure Base [20:5] for Address = 0 TX Connection Structure Base [20:5] for Address = 1 TX Connection Structure Base [20:5] for Address = N-2 TX Connection Structure Base [20:5] for Address = N-1 Figure 63 - HDLC Address LUT (RTP) Table 42 - Fields and Description Zarlink Semiconductor Inc ...
Page 118
... ADPCM samples with compression auto-detection and silence suppression with energy level detection. • PCM and ADPCM samples with compression auto-detection and silence suppression with energy level detection. The format of the TX xxPCM TSSTs in single and dual time-slot mode is the following: 118 Zarlink Semiconductor Inc. ...
Page 119
... Suppress packet ending with this sample. Suppress packet ending with this sample. Figure 64 - Format of TX xxPCM TSSTs Zarlink Semiconductor Inc. TSST Grouping on H.110 TSST Grouping on H.110 (Associated Stream bit cleared) (Associated Stream bit cleared ...
Page 120
... Table 43 - Fields and Description b10 PCM Buffer Number [9:0] b10 HDLC Stream Number [8:0] b10 LLL Buffer Number [6:0] Figure 66 - Stream/Buffer Tag Format Zarlink Semiconductor Inc ...
Page 121
... H.110 streams (i.e. ct_d[0] and ct_d[1], during the same time slot). The even stream contains the data that is logically first. The format of the RX TDM Control Memory is the following: Description Table 44 - Fields and Description Zarlink Semiconductor Inc. MT92210 121 ...
Page 122
... RX Circular Buffer Base [20:8] / Size Indication RX Circular Buffer Write Pointer [15:0] RX Circular Buffer Read Pointer [15:0] b12 b11 b10 Circular Buffer Base [20:8] / Size Indication Figure TDM Control Memory Zarlink Semiconductor Inc Padding Type ...
Page 123
... Address at which the next byte to be sent out on the HDLC stream will be read from in Read Pointer the RX Circular Buffer. This field is written to the RX HDLC Stream/Buffer Control Entries each time it is modified. Description Table 45 - Fields and Description Zarlink Semiconductor Inc. MT92210 123 ...
Page 124
... RX Circ Buf Base [20:16] RX Circ Buf Base [20:16 Zarlink Semiconductor Inc ...
Page 125
... Packets in the HDLC Circular Buffers have already been zero inserted/byte inserted. Entry 0 Entry 1 Entry 510 Entry 511 b12 b11 b10 Circular Buffer Base [20:8] and Size Circular Buffer Write Pointer [15:0] Circular Buffer Read Pointer [15:0] Description Table 46 - Fields and Description Zarlink Semiconductor Inc MT92210 125 ...
Page 126
... RX Circular Buffer Base [20:15 b13 b12 b11 b10 Circ Buf Base [20:16 Figure Circular Buffer Base and Size Zarlink Semiconductor Inc ...
Page 127
... Figure 71 - Format of RX xxPCM TSSTs - Zarlink Semiconductor Inc. Format of PCM Samples Format of PCM Samples Format of PCM Samples (both padding and voice) (both padding and voice) (both padding and voice) (no Decompressor Reset) (no Decompressor Reset) (no Decompressor Reset) b7 ...
Page 128
... Figure 72 - Format of RX xxPCM TSSTs - Zarlink Semiconductor Inc. Fields covered by CRC16 (PCM-R not included in CRC16) Explicit Underrun Indication (present until another CN/voice packet is received) ...
Page 129
... Ignore CN Packet. b13 b12 b11 b10 CN=0 Padding Type CN=2 Padding Type Figure Packet Conversion Lookup Table Description Table 47 - Fields and Description Zarlink Semiconductor Inc CN=1 Padding Type CN=3 Padding Type CN=253 Padding Type CN=255 Padding Type MT92210 129 ...
Page 130
... Zarlink Semiconductor Inc. ...
Page 131
... If the chip is a backup on the bus and the primary master fails, it will stop synchronizing itself on the master and track the local reference. 63.b2 63.b1 63.b0 31.b0 63.b2 63.b1 63.b0 31.b0 1/2 Period Sampling 3/4 Period Sampling 4/4 Period Sampling Figure 74 - TDM Bus Timing - ct_d Zarlink Semiconductor Inc. MT92210 131 ...
Page 132
... Figure 77 - TDM Bus Timing - Compatibility Clock Generation (other than sclk, sclkx2) 132 Figure 76 - TDM Bus Timing - sclkx2 Generation Zarlink Semiconductor Inc. : ...
Page 133
... MHz, allowing all 32 streams to be used in backwards compatibility with another non-H.110 agent. In addition, the MT92210, instead of supporting the full bandwidth of H.110, can be configured to only interface with the streams on the bus. This allows the chip to be run at a much lower frequency than 60 MHz. Zarlink Semiconductor Inc. MT92210 133 ...
Page 134
... Zarlink Semiconductor Inc. ...
Page 135
... SSRAM used with the chip. The maximum skew allowed is ± 0.5 ns. Div Div Y upclk (MHz 33.33 5 33. 53.33 6 53.33 to 66.66 Table 48 - Clock Divisor X and Y Zarlink Semiconductor Inc. MT92210 fast_clk (MHz) - 160 to 200 166.66 to 200 160 to 200 - 160 to 200 . 135 ...
Page 136
... Table 49 - Clock Divisor Z Clock Divisor CKOUT REF fc1pll FB Clock Divisor Clock Divisor CKOUT REF fc2pll FB Clock Divisor Figure 78 - Clock Synthesis Zarlink Semiconductor Inc. Clock Divisor mem_clk_sar_o fast_clk Clock Divisor mem_clk_net_o ...
Page 137
... E vent N-1 b13 b12 b11 b10 mem_clk_sar_i Counter [31:16] mem_clk_sar_i Counter [15:0] Reference Clock Counter [31:16] Reference Clock Counter [15:0] mem_clk_sar_i Cycles Since Last Reference Clock Rise [15:0] RTP Sequence Number [15:0] RTP Timestamp [31:16 est 15: 0] Zarlink Semiconductor Inc MT92210 137 ...
Page 138
... RTP Sequence Number Sequence number of the packet that caused this Adaptive Clock Recovery Event Structure to be written. RTP Timestamp Timestamp of the packet that caused this Adaptive Clock Recovery Event Structure to be written. 138 Description Table 50 - Fields and Description Zarlink Semiconductor Inc. ...
Page 139
... Programmable Fractional Divisor (Range = 2 to65535) Figure 81 - Adaptive Clock Recovery Modules Zarlink Semiconductor Inc. MT92210 E Written to clock recovery buffer in external memory bank A adapa_ref E Written to clock ...
Page 140
... Pll_clk 140 Edges and Level Monitor Figure 82 - GPIO Functionality Zarlink Semiconductor Inc. gpio[7:0], ct_netref1, ct_netref2 Internal_pll_clk ...
Page 141
... This is programmed in registers 398h and 39Ah. Finally, the memory controller allows manual accesses to the SDRAM to be performed through registers, allowing CPU accesses to perform the initialization sequence to the SDRAM. gpio_in[2] ‘0’ ct_mc_in MC Clock mc_clock Generator Figure 83 - Message Channel Circuit Zarlink Semiconductor Inc. MT92210 ct_mc 141 ...
Page 142
... Zarlink Semiconductor Inc. ...
Page 143
... I 12.5 25 I/O Z 12.5 25 I/O 12.5 25 I/O Z 12.5 25 I/O Z 12.5 25 I/O Z 12.5 25 I/O Z 12.5 25 I/O Z Zarlink Semiconductor Inc. MT92210 LVTTL (F) LVTTL LVTTL LVTTL LVTTL LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) ...
Page 144
... I/O Z Zarlink Semiconductor Inc. LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 8 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) Schmitt 12 mA (F) 200 pf load ...
Page 145
... Zarlink Semiconductor Inc. MT92210 PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load PCI (F) 200 pf load ...
Page 146
... X 18.75 37 18.75 37 18.75 37 18.75 37 18.75 37 Zarlink Semiconductor Inc. LVTTL (F) LVTTL (F) LVTTL LVTTL 4 mA (F) LVTTL LVTTL LVTTL (F) LVTTL 4 mA LVTTL 8 mA (F) LVTTL 8 mA LVTTL (F) LVTTL 4 mA LVTTL 4 mA LVTTL LVTTL LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 147
... I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z Zarlink Semiconductor Inc. MT92210 LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 148
... Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z 9.375 37.5 I/O Z Zarlink Semiconductor Inc. LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 149
... O 1 18.75 37 18.75 37 18.75 37 18.75 37 Zarlink Semiconductor Inc. MT92210 LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 150
... Z 6.25 12 6.25 12 6.25 12 6.25 12 Zarlink Semiconductor Inc. LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA LVTTL 4 mA ...
Page 151
... O Z 6.25 12 6.25 12 6.25 12 Zarlink Semiconductor Inc. MT92210 LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 8 mA (F) LVTTL 4 mA (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a UTOPIA PHY Layer LVTTL (F) 1. MT92210 is a UTOPIA ATM Layer 2. MT92210 is a ...
Page 152
... I 6.25 12 6.25 12 Zarlink Semiconductor Inc. LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) LVTTL 8 mA (F) 1. MT92210 is UTOPIA ATM Layer 2 ...
Page 153
... 6. Zarlink Semiconductor Inc. MT92210 LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) 1. MT92210 is UTOPIA ATM/PHY Layer 2. MT92210 is POS-PHY Link Layer LVTTL 8 mA (F) 1. MT92210 is a UTOPIA ATM Layer 2 ...
Page 154
... O X 6.25 12 6.25 12 Zarlink Semiconductor Inc. LVTTL 1. MT92210 is UTOPIA PHY Layer 2. MT92210 is POS-PHY Link Layer LVTTL (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL 4 mA (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) 0V Power Supply used for ...
Page 155
... Power C22 vss_ring Power C25 vss_ring Power C26 vss_ring Power D27 vss_ring Power E3 vss_ring Power E28 vss_ring Power F3 vss_ring Power F28 vss_ring Power J3 vss_ring Power J28 vss_ring Power K3 vss_ring Power K28 vss_ring Power N3 vss_ring Power Zarlink Semiconductor Inc. MT92210 155 ...
Page 156
... T16 vss_ring Power T17 vss_ring Power T18 vss_ring Power U3 vss_ring Power U13 vss_ring Power U14 vss_ring Power U15 vss_ring Power U16 vss_ring Power U17 vss_ring Power U18 vss_ring Power U28 vss_ring Power V3 vss_ring Power V13 vss_ring Power 156 Zarlink Semiconductor Inc. ...
Page 157
... F18 vdd33_ring Power F19 vdd33_ring Power F22 vdd33_ring Power F23 vdd33_ring Power G6 vdd33_ring Power H25 vdd33_ring Power J25 vdd33_ring Power K6 vdd33_ring Power L6 vdd33_ring Power M25 vdd33_ring Power N25 vdd33_ring Power Zarlink Semiconductor Inc. MT92210 3.3V Power Supply used for core and I/Os. 157 ...
Page 158
... AE23 vdd33_ring Power AB25 vdd33_ring Power AC25 vdd33_ring Power F25 vdd33_ring Power G25 vdd33_ring Power K25 vdd33_ring Power L25 vdd33_ring Power P25 vdd33_ring Power R25 vdd33_ring Power V25 vdd33_ring Power W25 vdd33_ring Power F8 vdd33_ring Power F9 vdd33_ring Power 158 Zarlink Semiconductor Inc. ...
Page 159
... AJ3 fc1pll_pllvss Power AK3 fc1pll_pllvdd Power AJ26 fc2pll_pllvdd Power AF25 fc2pll_pllvss Power Zarlink Semiconductor Inc. MT92210 Additional 0V power supply pins. Additional 0V power supply pins. 5V Power Supply used for 5V tolerance. May be connected to 3.3Vpower supply if all devices connected to the MT92210 are 3.3V only. See vdd5_0. ...
Page 160
... E25 NC 160 Zarlink Semiconductor Inc. 0V PLL power supply. See Figure PLL noise reduction circuit for reference design. 2.5V PLL power supply. See Figure PLL noise reduction circuit for reference design. 2.5V Core power supply. See vdd25_0 See vdd25_0 See vdd25_0 ...
Page 161
... AG14 NC AH4 NC AH7 NC AH12 NC AJ4 NC AJ27 NC AJ28 NC AK28 NC vdd25 vdd25 vdd25 10 ohm 1/10W 5% 0.1uF 50V 10% 10 ohm 1/10W 5% 0.1uF 50V 10% 10 ohm 1/10W 5% 0.1uF 50V 10% Figure 84 - PLL Noise Reduction Circuits Zarlink Semiconductor Inc. MT92210 fc1pll_pllvdd fc1pll_pllvss fc2pll_pllvdd fc2pll_pllvss h110pll_pllvdd h110pll_pllvss 161 ...
Page 162
... Zarlink Semiconductor Inc. ...
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... IN TSTG - 150 TSTG - 125 VDD Overstress: 2x VDD (7.2 V) Symbol VDD + 2.25 to 2. 125 Condition _ 1023 RTP Connections, all output pins loaded _ Zarlink Semiconductor Inc. MT92210 Limits Unit °C ° Limits Unit V °C °C ...
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... VDD3.3- 0.5 LVTTL Comm/Ind 2.0 Temp Range 5-Volt Compatible 2.0 – – – – – 0.8 – 0 VDD or VSS - VDD VSS - 2 Zarlink Semiconductor Inc. Min Typ Max 1.7 – VDD V +0.3 – 1.35 2.0 V – 1.7 2.0 V 0.8 1.0 – V 0.6 0.7 – 200 390 uA -28 -185 ...
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... MHz Yes 25 MHz 50 MHz No 25 MHz 50 MHz No 25 MHz 50 MHz No 25 MHz 50 MHz No 25 MHz 25 MHz No 25 MHz 25 MHz No 65.536 MHz No 8.192 MHz No Zarlink Semiconductor Inc. MT92210 Typ Max Unit 40% 60 40% 60% 400 ps 40% 60% 400 ps 40% 60% 400 ps ...
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... Figure 85 - Non-multiplexed CPU Interface - Intel Mode 166 Write Access Read Access t1 t8 t13 t7 t4 *Access Active Generation inmo_cs write_access_active inmo_rd_ds Zarlink Semiconductor Inc read_access_active ...
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... Figure 86 - Non-multiplexed CPU Interface - Motorola Mode Write Access Read Access *Access Active Generation inmo_cs read_access_active inmo_rd_ds inmo_wr_rw Zarlink Semiconductor Inc. MT92210 t3 t3 t10 t11 t3 t3 t14 t12 t10 t11 inmo_cs write_access_active inmo_rd_ds inmo_wr_rw 167 ...
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... Figure 87 - Multiplexed CPU Interface - Intel Mode 168 Write Access t15 t1 t16 t17 Read Access t15 t1 t16 t17 t8 t13 t7 t4 *Access Active Generation inmo_cs write_access_active inmo_rd_ds Zarlink Semiconductor Inc read_access_active ...
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... Write Access t15 t1 t16 t17 Read Access t15 t1 t16 t17 t9 t8 t14 t7 *Access Active Generation inmo_cs read_access_active inmo_rd_ds inmo_wr_rw Min Typical Zarlink Semiconductor Inc. MT92210 t3 t3 t10 t11 t3 t3 t12 t10 t11 write_access_active Max Unit Notes 2 * upclkp - 4 ns 169 ...
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... Read Access Time (to external memory) t8 read_access_active falling edge to inmo_d driven 170 Min Typical upclkp 0 see Table 52 see Table upclkp - 4 Zarlink Semiconductor Inc. Max Unit Notes see Table upclkp ns see Table 52 ns see Table 52 ns ...
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... Note 2: MCLK_SAR = MCLK_NET = 82 MHz, and Upclk = 32.768 MHz Min Typical 0 0 1.5 0 upclkp - 4 upclkp - Max. 640 680 720 760 760 820 Table Write Access Time Zarlink Semiconductor Inc. MT92210 Max Unit Notes Test Unit Conditions ns Note 1 ...
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... Table Read Access Time Zarlink Semiconductor Inc. Unit Test Conditions ns Note 1 ns Note 2 ns Note 1 ns Note 2 ns Note 1 ns Note 2 ns Note 1 ns Note 2 ns Note 1 ...
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... Burst Length 128 128 Table Read Access Time (continued Figure 89 - UTOPIA / POS-PHY / Ethernet Timing Zarlink Semiconductor Inc. Max. Unit Test Conditions 700 ns Note 1 760 ns Note 2 740 ns Note 1 920 ns Note 2 860 ns Note 1 960 ...
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... H.110 Output t10 t10 t11 t11 ct_c8 ct_c8 ct_c8 H.110 Frame Sampling H.110 Frame Sampling t20 t21 t20 t21 ct_c8 ct_c8 ct_frame ct_frame Figure 90 - H.110 Input Output Zarlink Semiconductor Inc. Typ Max Units Test Conditions ...
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... H.110 Message Transmission Delay H.110 Message Transmission Delay H.110 Message Transmission Delay t40 t40 t40 t41 t41 t41 H.110 Message Reception Delay H.110 Message Reception Delay t50 t50 ct_mc ct_mc ct_mc mc_rx mc_rx mc_rx Figure 91 - H.110 Message Handling Zarlink Semiconductor Inc. MT92210 175 ...
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... Min 102 102 Table 54 - Fields and Description Zarlink Semiconductor Inc. Typical Max Unit 122 ...
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... Clock to data change t5 Clock rising to signal driven t6 Clock rising to signal tri-state Min 3 3 Table 54 - Fields and Description (continued Min Typical 3.1 0 1.1 1.9 Table 55 - Fields and Description Zarlink Semiconductor Inc. Typical Max Unit Max Unit ...
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... Because of this, the exponential section of the delay entries is located in the delay section in which early packet will arrive. In addition, the time_zero_delta field must be programmed to the total number of frames of latency with which the latest packet can be expected to arrive (from source to destination). Zarlink Semiconductor Inc. MT92210 179 ...
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... In RTP HDLC format, a complete RTP packet including RTP header is encapsulated. FLAG H0 Figure 93 - Supported RTP HDLC Packet Format (after zero extraction) 1. Address bytes can byte(s). 2. Control byte is optional. 3. CRC bytes are optional 4. Complete RTP packet starts from D0 H1 Cntrl Zarlink Semiconductor Inc CRC0 CRC1 FLAG MT92210 181 ...
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... Draft (draft-ietf-mpls-label-encaps-07): MPLS Label Stack Encoding ITU I.363.5: ATM Adaptation Layer 5 ATM Forum Af-lane-0021.000: LAN Emulation over ATM version 1.0 Af-lane-0084.000: LAN Emulation over ATM version 2 Af-lane-0112.000: LAN Emulation over ATM version 2 Af-mpoa-0114.000: Multi-protocol over ATM version 1.1 Zarlink Semiconductor Inc. MT92210 183 ...
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... Af-phy-0017.000: UTOPIA Specification Level 1, version 2.01 Af-phy-0039.000: UTOPIA Level 2, version 1.0 PMC-Sierra POS-PHY: Saturn Compatible Packet over SONET Interface Specification (Level 2) 184 Zarlink Semiconductor Inc. ...
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... LANE (Local Area Network Emulation): LANE is a method for emulating Ethernet behavior over ATM AAL5. It takes over the behavior of the MAC layer in Ethernet networks. LLC (Logical Link Control): The LLC method allows multiplexing of multiple protocols over a single ATM VC. LLC headers are 3 bytes. Zarlink Semiconductor Inc. MT92210 185 ...
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... VCI is a 16-bit number that is included in the header of an ATM cell. VPI (Virtual Path Identifier): A virtual path determines the way an ATM cell should be routed. The VPI is an 8-bit (in UNI) or 12-bit (in NNI) number that is included in the header of an ATM cell. WATOMIC: An uninterruptable Write operation. 186 Zarlink Semiconductor Inc. ...
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... VC: A Null VC contains data in which some or all of the headers have been encoded into the VC number itself. For example, a Null-application data VC's payload would begin with the application data itself (either RTP or the payload) with UDP header, and no SNAP/LLC, LANE or other headers. Null encapsulation is referred to in IETF RFC2684 as VC Multiplexing. Zarlink Semiconductor Inc. MT92210 187 ...
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