DSP56001AFE27 Motorola, DSP56001AFE27 Datasheet
DSP56001AFE27
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DSP56001AFE27 Summary of contents
Page 1
... Internal Data Bus Switch Program Interrupt Decode Control Controller Clock Generator Program Control Unit 2 2 IRQ Figure 1 DSP56001A Block Diagram ©1997 MOTOROLA, INC. For More Information On This Product Program X Data Host Memory Memory Interface 512 24 RAM 256 (HI ROM 256 ...
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... For More Information On This Product, TABLE OF CONTENTS 1 (800) 521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications. OH DSP56001A/D, Rev to: www.freescale.com Voltage MOTOROLA ...
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... Two 256 24-bit on-chip data ROMs containing sine, A-law and -law tables • External memory expansion with 16-bit address and 24-bit data buses • Bootstrap loading from external data bus or Host Interface MOTOROLA For More Information On This Product, DSP56001A/D, Rev to: www ...
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... Documentation is available from one of the following locations (see back cover for detailed information): • A local Motorola distributor • A Motorola semiconductor sales office • A Motorola Literature Distribution Center • The World Wide Web (WWW) iv For More Information On This Product, DSP56001A/D, Rev ...
Page 5
... Implementing IIR/FIR Filters Principles of Sigma-Delta Modulation for A-to-D Converters Full-Duplex 32-kbit/s CCITT ADPCM Speech Coding DSP56001 Interface Techniques and Examples MOTOROLA For More Information On This Product, Description Description Application Report; uses the DSP56001 look-up table Application Report; includes code and circuitry; features the DSP56001 Application Report ...
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... Application Report; -law and A-law companding routines for PCM mono- circuits Brochures from companies selling hardware and software that supports Motorola DSPs Flyer; Motorola’s program supporting Universities in DSP research and education Technical Training Schedule Audio Course Information Textbook by Mohamed El-Sharkawy; ...
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... Port B signals are GPIO signals multiplexed on the external pins also used with the HI signals. 3. Port C signals are GPIO signals multiplexed on the external pins also used by the SCI and SSI ports. Figure 1 diagram of DSP56001A signals by functional group. MOTOROLA For More Information On This Product, SECTION 1 ...
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... SC0–SC2 Synchronous SCK Serial Interface 2 SRD (SSI) Port STD DSP56001A/D, Rev to: www.freescale.com Interrupt mode IRQA IRQB Port B GPIO PB0–PB7 PB8–PB10 PB11 PB12 PB13 PB14 Port C GPIO PC0 PC1 PC2 Port C GPIO PC3–PC5 PC6 PC7 PC8 AA0885 MOTOROLA ...
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... Data Bus Ground—These lines connect system ground to the data bus. D GND (1) Host Interface Ground—These lines supply ground connections for the Host Interface logic. MOTOROLA For More Information On This Product, Table 1-2 Power Connections Description lines and the GND CCQ Table 1-3 Ground Connections Description DSP56001A/D, Rev ...
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... A0–A15 are tri-stated when the bus grant signal is asserted. Table 1-6 Data Bus Signals Signal Description Data Bus—These signals provide the bidirectional data bus for external program and data memory accesses. D0–D23 are tri-stated when the BG or RESET signal is asserted. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... BG or RESET signal is asserted. RD Output Tri-stated Read Enable—RD is asserted during external memory read cycles tri-stated when the BG or RESET signal is asserted. MOTOROLA For More Information On This Product, Table 1-7 Bus Control Signals Signal Description To prevent erroneous operation, pull up the BR/WT signal when it is not in use ...
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... When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET signal is deasserted, the initial chip operating mode is latched from MODA and MODB. The internal reset signal is deasserted synchronously with the internal clocks. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. DO NOT APPLY 10 VOLTS TO ANY PIN OF THE Subjecting any pin of the DSP56001A to voltages in excess of the specified TTL/CMOS levels will permanently damage the device. MOTOROLA For More Information On This Product, CAUTION DSP56001A (including DSP56001A/D, Rev to: www.freescale.com DSP56001A Interrupt and Mode Control ...
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... HR/W is low and HEN is asserted, H0–H7 are inputs and host data is transferred to the DSP. HR/W must be stable when HEN is asserted. Port B GPIO 11 (PB11)—This signal is a GPIO signal called PB11 when the Host Interface is not being used. After reset, the default state for this signal is GPIO input. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Input Tri-stated Host Acknowledge—This input has two functions. It provides a host PB14 Input or Output MOTOROLA For More Information On This Product, Signal Description When HEN is asserted and HR/W is high, H0–H7 become outputs and the host processor may read DSP56001A data. When HEN is asserted and HR/W is low, H0–H7 become inputs. Host data is latched in the DSP on the rising edge of HEN ...
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... Synchronous mode. The direction and function of the signal is defined by the RCM bit in the SCI Clock Control Register (SCCR). Port C GPIO 2 (PC2)—This signal is a GPIO signal called PC2 when the SCI TCLK function is not being used. After reset, the default state is GPIO input. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
Page 17
... Input or Tri-stated SSI Serial Receive Clock—This bidirectional signal provides the Output PC6 Input or Output MOTOROLA For More Information On This Product, Synchronous Serial Interface Port Signal Description whether the SCLK is in Synchronous or Asynchronous mode. • In Synchronous mode, this signal is used as a serial I/O flag. ...
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... After reset, the default state is GPIO input. from the SSI Transmitter Shift Register. Port C GPIO 8 (PC8)—This signal is GPIO signal PC8 when the SSI STD function is not being used. After reset, the default state is GPIO input. DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Table 2-2 Recommended Operating Conditions Rating Supply Voltage Operating Temperature Range (See Note 1) Table 2-3 Thermal Characteristics for 88-pin PGA Package Thermal Resistance Junction to Ambient (See Note 2) Junction to Case (estimated) (See Note 3) MOTOROLA For More Information On This Product, SECTION 2 Symbol (GND – 0. ...
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... Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature. 2-2 For More Information On This Product, Symbol 13.0 (PQFP) DSP56001A/D, Rev to: www.freescale.com Value Rating 40 (CQFP) C/W 47 (PQFP) 7.0 (CQFP) C/W MOTOROLA ...
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... Input Capacitance (Note 3) Note: 1. Section 4 Design Considerations describes how to calculate the external supply current order to obtain these results all inputs must be terminated (i.e., not allowed to float). 3. Periodically sampled and not 100% tested MOTOROLA For More Information On This Product, Symbol Min V CC 4.75 VIHC ...
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... V IL Rise Time – substitute with the numbers in Table 2-6. C CYC Table 2-6 Internal Clocks Symbol CYC DSP56001A/D, Rev to: www.freescale.com maximum MODA, and MODB. These High 90% 50% 10% AA0179 Expression MOTOROLA ...
Page 23
... MHz fundamental load reduce system cost, a ceramic resonator may be used instead of the crystal. Suggested source: Murata-Erie #CST4.00MGW040 (4 MHz with built-in load capacitors) Figure 2-2 Crystal Oscillator Circuits MOTOROLA For More Information On This Product, EXTAL L1 Suggested Component Values R1 = 470 330 ...
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... IHC ILC Table 2-7 Clock Operation 27 MHz Symbol Min Max 150 150 250 500 CYC DSP56001A/D, Rev to: www.freescale.com V ILC Midpoint V IHC AA0360 33 MHz Unit Min Max 4 33 MHz 13.5 150 ns 13.5 150 ns 30 250 ns 60 500 ns MOTOROLA ...
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... Mode Select Setup Time 15 Mode Select Hold Time 16 Minimum Edge-Triggered Interrupt Request Assertion Width 16a Minimum Edge-Triggered Interrupt Request Deassertion Width MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing = 5 for 33 MHz CC 27 MHz Min Max — ...
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... WS) – DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max + T — — — — WS) – — WS) – — – — WS) – MOTOROLA ...
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... Note 1) • Internal Crystal Oscillator Clock, OMR Bit • Stable External Clock, OMR Bit MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing 27 MHz Min Max — T – — ...
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... Min Max Min 65548 T — 65548 — and T will not be constant. Since this stabilization period typically allowed to assure that the oscillator is stable before C DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max — — MOTOROLA ...
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... A0–A15 EXTAL 12 RESET A0–A15, DS, PS, X/Y Figure 2-5 Synchronous Reset Timing RESET MODA, MODB Figure 2-6 Operating Mode Select Timing MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing 10 Figure 2-4 Reset Timing IHM V ILM DSP56001A/D, Rev to: www.freescale.com ...
Page 30
... General Purpose I/O 18 IRQA, IRQB Figure 2-7 External Level-Sensitive Fast Interrupt Timing IRQA, IRQB IRQA, IRQB Figure 2-8 External Interrupt Timing (Negative Edge-Triggered) 2-12 For More Information On This Product, First Interrupt Instruction Execution/Fetch General Purpose I/O 16 16A DSP56001A/D, Rev to: www.freescale.com AA0889 AA0890 MOTOROLA ...
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... IRQA A0–A15, DS, PS, X/Y Figure 2-10 Recovery from Stop State Using IRQA IRQA A0–A15, DS, PS, X/Y Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing T0 DSP56001A/D, Rev to: www ...
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... DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max — — — — — — — — — ns — — — ns MOTOROLA ...
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... This timing must be adhered to only if two consecutive reads from one of these registers are executed without polling the corresponding status bits or HREQ. 5. HREQ is pulled resistor. 6. Specifications are periodically sampled and not 100% tested. 7. May decrease for future versions. MOTOROLA For More Information On This Product, 27 MHz Min Max 0 — 4 — ...
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... H0–H7 Data (Output) Valid Figure 2-13 Host Read Cycle (Non-DMA Mode) 2-16 For More Information On This Product Data Valid 49 RXM Read 32 44 Address Valid 42 38 Data Valid DSP56001A/D, Rev to: www.freescale.com 37 AA0223 47 RXL Read Address Valid Data Valid AA0224 MOTOROLA ...
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... Valid Figure 2-15 Host DMA Read Cycle HREQ (Output TXH HEN Write (Input) 33 H0–H7 Data (Input) Valid Figure 2-16 Host DMA Write Cycle MOTOROLA For More Information On This Product, 49 TXM Write 32 44 Address Valid 40 34 Data Valid 32 46 RXM Read ...
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... Max 8 T — – 13 — – 13 — — — — – — – T – — — — – — — — — ns MOTOROLA ...
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... Clock High Period 70 < intentionally blank > 71 Output Data Setup to Clock Rising Edge (Internal Clock) 72 Output Data Hold After Clock Rising Edge (Internal Clock) MOTOROLA For More Information On This Product, Serial Communication Interface (SCI) Timing 27 MHz Min Max 64 T — – ...
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... In the Wired-OR mode, TXD can be pulled Figure 2-18 SCI Asynchronous Mode Timing 2-20 For More Information On This Product Data Valid 61 62 Data Valid a) Internal Clock Data Valid 65 66 Data Valid b) External Clock Data Valid DSP56001A/D, Rev to: www.freescale.com AA0892 AA0893 MOTOROLA ...
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... SRD Rising Edge to FSR Out (wl) High 87 RXC Rising Edge to FSR Out (wl) Low 88 Data In Setup Time Before RXC (SCK in Synchronous Mode) Falling Edge MOTOROLA For More Information On This Product, Synchronous Serial Interface (SSI) Timing = 5 for 33 MHz; CC Table 2-12 SSI Timing 27 MHz Min Max Min 4 T — ...
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... MOTOROLA ...
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... Falling Edge 106 Flag Output Valid After TXC Rising Edge Note: 1. For internal clock, External Clock Cycle is defined Periodically sampled and not 100% tested MOTOROLA For More Information On This Product, Synchronous Serial Interface (SSI) Timing 27 MHz Min Max Min — ...
Page 42
... In the Normal mode, the output flag state is asserted for the entire frame period. Figure 2-19 SSI Transmitter Timing 2-24 For More Information On This Product 100 100 99 First Bit 105 103 104 105 106 DSP56001A/D, Rev to: www.freescale.com 98 101A 101 Last Bit See Note AA0894 MOTOROLA ...
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... In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. Figure 2-20 SSI Receiver Timing MOTOROLA For More Information On This Product, Synchronous Serial Interface (SSI) Timing ...
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... Go to: www.freescale.com 33 MHz Unit Min Max + — — – — — ns MOTOROLA ...
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... Data Out Setup Time to WR Deassertion • • WS > 0 126 RD Deassertion to Address Not Valid 127 Address Valid to RD Deassertion • • WS > 0 MOTOROLA For More Information On This Product, External Bus Asynchronous Timing 27 MHz Min Max ...
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... H C DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Max 0 — 5.5 — ns — — ( — 5 — — ( — 6.5 — — — 6.5 — 6.5 — MOTOROLA ...
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... Note) RD 120 (See Note) 135 WR 123 D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. Figure 2-22 External Bus Asynchronous Timing MOTOROLA For More Information On This Product, External Bus Asynchronous Timing 115 116 117 118 127 131 129 122 ...
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... — — 4 — 12 — 2 — DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Min Max — 10.5 ns — 3.5 — — — — ns MOTOROLA ...
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... CKOUT A0–A15, DS, PS, X/Y 140 RD 141 WR D0–D23 145 Note: During Read-Modify-Write Instructions, the address lines do not change states. Figure 2-23 Synchronous Bus Timing MOTOROLA For More Information On This Product, External Bus Synchronous Timing 27 MHz Min Max the corresponding signal(s ...
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... H DSP56001A/D, Rev to: www.freescale.com 33 MHz Unit Min Max 2 2.5 — – — 6 – – 4.5 — 6.5 — MOTOROLA ...
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... RD D0–D23 120 WR D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. Figure 2-24 Asynchronous Timings MOTOROLA For More Information On This Product, 27 MHz Min Max 12 — 158 123 ...
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... During Read-Modify-Write Instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. Figure 2-25 Synchronous Timings 2-34 For More Information On This Product 152 153 147 145 Data Out DSP56001A/D, Rev to: www.freescale.com 149 154 144 148 Data In 142 146 AA0397 MOTOROLA ...
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... Pin Grid Array (PGA), type ‘RC’ Top and bottom views of the each package are shown, together with their pin-outs. MOTOROLA For More Information On This Product, SECTION 3 PACKAGING DSP56001A/D, Rev ...
Page 54
... Figure 3-1 Top View of the 132-pin Plastic (FC) Quad Flat Package 3-2 For More Information On This Product, (Top View) DSP56001A/D, Rev to: www.freescale.com nc D20 D19 D18 GNDD GNDD nc D17 D16 nc D15 D14 D13 nc D12 V CCD V CCD D11 nc D10 GNDD GNDD AA0898 MOTOROLA ...
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... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-2 Bottom View of the 132-pin Plastic (FC) Quad Flat Package MOTOROLA For More Information On This Product, Orientation Mark (chamfered edge ...
Page 56
... Figure 3-3 Top View of the 132-pin Ceramic (FE) Quad Flat Package 3-4 For More Information On This Product, Orientation Mark (Top View) DSP56001A/D, Rev to: www.freescale.com nc D20 D19 D18 GNDD GNDD nc D17 D16 nc D15 D14 D13 nc D12 V CCD V CCD D11 nc D10 GNDD GNDD AA0900 MOTOROLA ...
Page 57
... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-4 Bottom View of the 132-pin Ceramic (FE) Quad Flat Package MOTOROLA For More Information On This Product, (Bottom View) DSP56001A/D, Rev to: www ...
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... VCCQ VCCH (Top View) GNDN VCCN GNDN A11 A10 DSP56001A/D, Rev to: www.freescale.com HEN HR HREQ RXD GNDH TXD SC0 SCLK GNDQ VCCQ SCK SC2 SRD STD BG/BS SC1 RD BR/ X/Y AA0902 MOTOROLA ...
Page 59
... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-6 Bottom View of the 88-pin Ceramic (RC) Pin Grid Array Package MOTOROLA For More Information On This Product, Orientation Mark ...
Page 60
... C13 H1 H2 C12 B13 H3 B12 H4 A13 H5 A12 H6 B11 H7 B8 HA0 HA1 A8 A7 HA2 A11 HR/W A10 HEN B10 HREQ A9 HACK DSP56001A/D, Rev to: www.freescale.com Port GPIO ID PB0 PB1 PB2 PB3 PB4 PB5 PB6 B PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 MOTOROLA ...
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... D19 A2 D21 A3 D22 A4 MODB/IRQB A5 RESET A6 XTAL A7 HA2/PB10 A8 HA1/PB9 A9 HACK/PB14 A10 HEN/PB12 A11 HR/W/PB11 MOTOROLA For More Information On This Product, Pin Number 88 pin Primary “RC” PGA Function RXD D13 E13 TXD F13 SCLK F12 SC0 K13 SC1 SC2 H13 G13 SCK ...
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... GNDD N7 J12 SRD/PC7 N8 J13 STD/PC8 N10 K2 D5 N11 K12 BG/BS N12 K13 SC1/PC4 N13 L1 D4 — — DSP56001A/D, Rev to: www.freescale.com — PGA Signal Name A14 A13 A12 A10 X/Y — — MOTOROLA ...
Page 63
... H7/PB7 12 V CCH 13 V CCH 14 H6/PB6 15 H5/PB5 16 H4/PB4 H3/PB3 20 H2/PB2 H1/PB1 23 GNDH 24 GNDH 25 H0/PB0 MOTOROLA For More Information On This Product, Pin No. Signal Name RXD/PC0 28 TXD/PC1 29 SCLK/PC2 SC0/PC3 32 SCK/PC6 33 GNDQ 34 GNDQ 35 V CCQ 36 V CCQ 37 SC2/PC5 38 nc ...
Page 64
... D17 128 110 nc 129 111 GNDD 130 112 GNDD 131 113 D18 132 DSP56001A/D, Rev to: www.freescale.com — PQFP & CQFP Signal Name D19 D20 nc nc D21 D22 D23 MODB/IRQB nc MODA/IRQA RESET nc XTAL EXTAL V CCQ V CCQ GNDQ GNDQ nc MOTOROLA ...
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... A12 76 A13 77 A14 79 A15 MOTOROLA For More Information On This Product, 88 pin Signal “FC” PQFP or “RC” PGA Name “FE” CQFP Pin Pin No. M11 D8 N11 D9 N10 D10 M9 D11 N9 D12 M8 D13 N8 D14 N7 D15 ...
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... PC4 A11 PC5 B10 PC6 B5 PC7 DSP56001A/D, Rev to: www.freescale.com 88 pin “RC” PGA Pin No. No C12 19 B13 16 B12 15 A13 14 A12 11 B11 A11 8 A10 10 B10 D13 28 E13 29 F13 31 F12 40 K13 37 H13 32 G13 42 J12 MOTOROLA ...
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... CCN V 64 CCN V 35 CCQ V 36 CCQ V 128 CCQ V 129 CCQ WR 46 MOTOROLA For More Information On This Product, 88 pin Signal “FC” PQFP or “RC” PGA Name “FE” CQFP Pin Pin No. A4 PC8 none RESET D12 RXD C13 ...
Page 68
... L13 nc N13 pin “RC” PGA Power Supply Pin No CCN L6 L9 GNDN DSP56001A/D, Rev to: www.freescale.com 88 pin “RC” PGA Pin No. No. 103 107 110 116 117 122 125 132 Circuit Supplied Address Bus Buffers MOTOROLA ...
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... PQFP or “FE” CQFP Pin No. 100 101 90 91 111 112 35 36 128 129 33 34 130 131 MOTOROLA For More Information On This Product, 88 pin “RC” PGA Power Supply Pin No CCD D3 J3 GNDD C6 G12 V CCQ B7 G11 GNDQ C9 ...
Page 70
... D1 0.012 0.016 0.008 D2 0.011 E 0.006 0.008 0.005 E1 0.007 F 0.014 0.014 G 0.025 BSC J 0.950 BSC J1 0.475 BSC 0.034 K 0.044 K1 0.010 BSC P 0.950 BSC P1 0.475 BSC R1 0.013 REF S 1.080 BSC S1 0.540 BSC U 0.025 REF V 1.080 BSC V1 0.540 BSC 0.006 W 0.008 0 8 MOTOROLA ...
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... PIN 1 L IDENT 0.008 4X 33 TIPS 0. 132X VIEW AE Figure 3-8 132-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information MOTOROLA For More Information On This Product, 117 VIEW AC 3 PLACES 116 L-N M VIEW AE NOTES: SEATING PLANE 1. ...
Page 72
... Go to: www.freescale.com NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. PIN DIAMETER DOES NOT INCLUDE SOLDER DIP OR CUSTOM FINISHES. G INCHES DIM MIN MAX A 1.340 1.380 B 1.340 1.380 C 0.085 0.120 D 0.017 0.020 G 0.100 BSC K 0.165 0.200 2 7 AA0617 MOTOROLA ...
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... Freescale Semiconductor, Inc. Orientation Marks Figure 3-11 PQFP Shipping Tray Orientation Marks Figure 3-12 CQFP Shipping Tray MOTOROLA For More Information On This Product, Top View Top View DSP56001A/D, Rev to: www.freescale.com DSP56001A Pin-out and Package Information 4 9 AA1132 AA0897 3-21 ...
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... Freescale Semiconductor, Inc. DSP56001A Pin-out and Package Information 3-22 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
Page 75
... DSP56001A signals exhibit faster rise and fall times than the same signals on the DSP56001. These faster edges may generate more radiated noise and EMI, and may require more attention to these issues (e.g., the DSP56001A based circuit may require better decoupling). MOTOROLA For More Information On This Product, SECTION ...
Page 76
... MOVEP instructions to/from Data ALU registers take 2 instruction cycles on the DSP56001. On the DSP56001A, these instructions take only 1 instruction cycle. DSP56001 software which is dependent on the timing of this form of the MOVEP instruction must be modified when ported to the DSP56001A. 4-2 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
Page 77
... On the DSP56001A, the SCI and SSI clocks are stopped when the peripherals are not enabled in order to save power result, the initialization time of the SCI and SSI is longer on the DSP56001A than on the DSP56001. MOTOROLA For More Information On This Product, Substituting the DSP56001A for the DSP56001 ...
Page 78
... Writing this bit will result Written as zero. in behavior differences between the 001 and the 001A. DSP56001A DEFINITION — — Reserved Read This bit should be written with as don’t care. only a zero on the 56001A. DSP56001A/D, Rev to: www.freescale.com EXPLAINATION OF DIFFERENCE EXPLAINATION OF DIFFERENCE MOTOROLA ...
Page 79
... Values for thermal resistance presented in this document, unless JA JC estimated, were derived using the procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for MC68XX Microcomponent Devices”, and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup ...
Page 80
... This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V • All inputs must be terminated (i.e., not allowed to float) using CMOS levels. 4-6 For More Information On This Product, CAUTION ). CC power source to GND. CC and GND circuits. CC DSP56001A/D, Rev to: www.freescale.com pin on the DSP, CC and CC MOTOROLA ...
Page 81
... Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the Host Interface. The following paragraphs present considerations for proper operation. MOTOROLA For More Information On This Product, – ...
Page 82
... HI port programming (e.g., by setting the INIT bit in ICR then polling it and waiting cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HREQ pin). 4-8 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... A very small probability exists that the DSP will read the status bits during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. MOTOROLA For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com ...
Page 84
... When in Reset, IRQA and IRQB must be deasserted by external peripherals. Figure 4-1 No Glue Logic, Low Cost Memory Port Bootstrap—Mode 1 4-10 For More Information On This Product, DSP56001A D23 BR HACK MODA/IRQA PS 11 A0–A10 8 D0–D7 RESET MBD301* MODB/IRQB DSP56001A/D, Rev to: www.freescale.com 2716 CE A0–A10 D0–D7 AA0904 MOTOROLA ...
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... Figure 4- IRQB IRQA RESET Note: 1. All resistors are 15 K unless noted otherwise. 2. When in Reset, IRQA and IRQB must be deasserted by external peripherals. Figure 4-2 Port A Bootstrap with External Data RAM—Mode 1 MOTOROLA For More Information On This Product, DSP56001A HACK DS X/Y A0– ...
Page 86
... Figure 4-3 DSP56001A Host Bootstrap Example—Mode 5 4-12 For More Information On This Product, DSP56001A HEN F32 BR Address Decode HACK F32 LS09 MODB/ IRQB HR/W F32 MODA/ IRQA HA0–HA2 3 RESET H0–H7 8 D23 DSP56001A/D, Rev to: www.freescale.com MC68000 12.5 MHz LDS A4–A23 DTACK R/W F32 A1–A3 D0–D7 AA0906 MOTOROLA ...
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... RAM with DSP algorithms by using the MOVEM instruction IRQB IRQA RESET Note: 1. All resistors are 15 K unless noted otherwise. 2. When in Reset, IRQA and IRQB must be deasserted by external peripherals. Figure 4-4 32K Words of External Program ROM MOTOROLA For More Information On This Product, DSP56001A RD BR HACK PS A0–A14 MODB/ ...
Page 88
... DSP56001A is at least 4.5 V before initiating CC + (1) C DLY DLY DLY Where 75,000 T minimum DLY 8 MHz OSC DSP56001A/D, Rev to: www.freescale.com is C RESET 2 0 20% DLY AA0908 MOTOROLA ...
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... D02 A07 D01 A08 D00 A09 A00 A31 A01 A30 A02 A29 Note: 1. Connector ISA Bus. 2. All series resistors are 15 K Figure 4-6 DSP56001A-to-ISA Bus Interface Schematic MOTOROLA For More Information On This Product, +5V L13 1 B10 A10 5 16 ...
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... Freescale Semiconductor, Inc. DSP56001A Application Examples 4-16 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Package Type DSP56001A Ceramic Pin-Grid Array (PGA) Plastic Quad Flat Pack (PQFP) Ceramic Quad Flat Pack (CQFP) MOTOROLA For More Information On This Product, SECTION 5 Frequency Pin Count (MHz) 88 132 132 DSP56001A/D, Rev to: www.freescale.com Order Number 27 DSP56001ARC27 33 DSP56001ARC33 27 DSP56001AFC27 33 DSP56001AFC33 27 DSP56001AFE27 33 DSP56001AFE33 5-1 ...
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... Freescale Semiconductor, Inc. DSP56001A 5-2 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... M_11 DC $3C7C00 ; 3871 M_12 DC $3A7C00 ; 3743 M_13 DC $387C00 ; 3615 M_14 DC $367C00 ; 3487 M_15 DC $347C00 ; 3359 MOTOROLA For More Information On This Product, mu-Law / A-Law Expansion Tables APPENDIX A -Law / A-law Expansion Table M_16 DC M_17 DC M_18 DC M_19 DC M_1A DC M_1B DC M_1C DC M_1D DC M_1E ...
Page 94
... M_7A DC $002800 M_7B DC $002000 M_7C DC $001800 M_7D DC $001000 M_7E DC $000800 M_7F DC $000000 DSP56001A/D, Rev to: www.freescale.com ; 163 ; 155 ; 147 ; 139 ; 131 ; 123 ; 115 ; 107 ; MOTOROLA ...
Page 95
... A_A3 DC $5A0000 ; 2880 A_A4 DC $460000 ; 2240 A_A5 DC $420000 ; 2112 A_A6 DC $4E0000 ; 2496 A_A7 DC $4A0000 ; 2368 A_A8 DC $760000 ; 3776 MOTOROLA For More Information On This Product, mu-Law / A-Law Expansion Tables A_A9 DC A_AA DC A_AB DC A_AC DC A_AD DC A_AE DC A_AF DC A_B0 DC A_B1 DC A_B2 DC A_B3 DC A_B4 ...
Page 96
... A_FA DC $03F000 ; 126 A-4 For More Information On This Product, 15 A_FB DC 13 A_FC DC 3 A_FD DC 1 A_FE DC 7 A_FF DSP56001A/D, Rev to: www.freescale.com $03D000 ; 122 $033000 ; 102 $031000 ; 98 $037000 ; 110 $035000 ; 106 MOTOROLA ...
Page 97
... S_15 DC $3F174A ; +0.4928981960 S_16 DC $41CE1E ; +0.5141026974 S_17 DC $447ACD ; +0.5349975824 S_18 DC $471CED ; +0.5555701852 S_19 DC $49B415 ; +0.5758082271 MOTOROLA For More Information On This Product, Table A-2 Sine Wave Table S_1A DC $4C3FE0 S_1B DC $4EBFE9 S_1C DC $5133CD S_1D DC $539B2B S_1E DC $55F5A5 S_1F DC $5842DD S_20 DC $5A827A ...
Page 98
... MOTOROLA ...
Page 99
... S_AB DC $90A0FD ; -0.8700870275 S_AC DC $8F1D34 ; -0.8819212914 S_AD DC $8DAAD3 ; -0.8932244182 S_AE DC $8C4A14 ; -0.9039893150 S_AF DC $8AFB2D ; -0.9142097235 S_B0 DC $89BE51 ; -0.9238795042 MOTOROLA For More Information On This Product, S_B1 DC $8893B1 S_B2 DC $877B7C S_B3 DC $8675DC S_B4 DC $8582FB S_B5 DC $84A2FC S_B6 DC $83D604 S_B7 DC $831C31 S_B8 DC $8275A1 S_B9 DC ...
Page 100
... S_F6 DC $E0E607 ; -0.2429800928 S_F7 DC $E3F47E ; -0.2191012055 S_F8 DC $E70748 ; -0.1950902939 S_F9 DC $EA1DEC ; -0.1709619015 S_FA DC $ED37F0 ; -0.1467303932 S_FB DC $F054D9 ; -0.1224106997 S_FC DC $F3742D ; -0.0980170965 S_FD DC $F69570 ; -0.0735644996 S_FE DC $F9B827 ; -0.0490676016 S_FF DC $FCDBD5 ; -0.0245412998 A-8 For More Information On This Product, DSP56001A/D, Rev to: www.freescale.com MOTOROLA ...
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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or ...