KXPC860ENZP80D4 Freescale Semiconductor, Inc, KXPC860ENZP80D4 Datasheet
KXPC860ENZP80D4
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KXPC860ENZP80D4 Summary of contents
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... Freescale Semiconductor, Inc. Advance Information MPC860EC Rev. 6.3 9/2003 MPC860 Family Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC860 family. This hardware specification covers the following topics: Topic Section 1, “ ...
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... Freescale Semiconductor, Inc. Overview Overview 1 Overview The MPC860 Quad Integrated Communications Controller (PowerQUICC™ versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. It particularly excels in communications and networking systems. The PowerQUICC unit is referred to as the MPC860 in this hardware specification. ...
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... Freescale Semiconductor, Inc. – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — MMUs with 32-entry TLB, fully-associative instruction, and data TLBs — ...
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... Freescale Semiconductor, Inc. Features Features • Interrupts — Seven external interrupt request (IRQ) lines — 12 port pins with interrupt capability — 23 internal interrupt sources — Programmable priority between SCCs — Programmable highest priority request • 10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when using ATM over UTOPIA interface) • ...
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... Freescale Semiconductor, Inc. — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) — Totally transparent (bit streams) — Totally transparent (frame-based with optional cyclic redundancy check (CRC)) • Two SMCs (serial management channels) — ...
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... Freescale Semiconductor, Inc. Maximum Tolerated Ratings Maximum Tolerated Ratings — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = — Each watchpoint can generate a break-point internally. • 3.3-V operation with 5-V TTL compatibility except EXTAL and EXTCLK • ...
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... Freescale Semiconductor, Inc. 4 Thermal Characteristics Table 3 shows the thermal characteristics for the MPC860. Table 3. MPC860 Thermal Resistance Data Rating 1 Junction-to-ambient Natural convection Airflow (200 ft/min) 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package top Natural convection Airflow (200 ft/min) 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air fl ...
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... Freescale Semiconductor, Inc. Power Dissipation Power Dissipation 5 Power Dissipation Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1, where CPU frequency is twice the bus speed. Die Revision A.3 and previous B.1 and C.1 D.3 and D.4 (1:1 mode) D.3 and D.4 (2:1 mode) 1 Typical power dissipation is measured at 3 ...
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... Freescale Semiconductor, Inc. Table 5. DC Electrical Specifications (continued) Characteristic Input high voltage (all inputs except EXTAL and EXTCLK) Input low voltage EXTAL, EXTCLK input high voltage Input leakage current 5.5 V (except TMS, in TRST, DSCK, and DSDI pins) Input leakage current ...
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... Freescale Semiconductor, Inc. Thermal Calculation and Measurement Thermal Calculation and Measurement 7 Thermal Calculation and Measurement For the following discussions drivers. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature where ambient temperature (º package junction-to-ambient thermal resistance (ºC/W) ...
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... Freescale Semiconductor, Inc Board Temperature Rise Above Ambient Divided by Package Power Board Temperture Rise Above Ambient Divided by Package Figure 1. Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known, an estimate of the junction temperature in the environment can be made ...
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... Freescale Semiconductor, Inc. Layout Practices Layout Practices T = thermocouple temperature on top of package power dissipation in package D The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package ...
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... Freescale Semiconductor, Inc. The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. Num Characteristic B1 CLKOUT period B1a EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz and MF <= 2) B1b EXTCLK to CLKOUT phase skew (EXTCLK > 10 MHz and MF < 10) B1c CLKOUT phase jitter (EXTCLK > ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 6. Bus Operation Timings (continued) Num Characteristic B9 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, AT(0:3), PTR High-Z B11 CLKOUT to TS, BB assertion B11a CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA interface) B12 CLKOUT to TS, BB negation ...
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... Freescale Semiconductor, Inc. Table 6. Bus Operation Timings (continued) Num Characteristic B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 6. Bus Operation Timings (continued) Num Characteristic B29a WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 B29b CS negated to D(0:31), DP(0:3), High-Z GPCM write access, ACS = 00, TRLX = 0, 1, and CSNT = 0 B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write access, ...
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... Freescale Semiconductor, Inc. Table 6. Bus Operation Timings (continued) Num Characteristic B30b WE(0:3) negated to A(0:31), invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31), Invalid GPCM, write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 B30c WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 6. Bus Operation Timings (continued) Num Characteristic B32b CLKOUT rising edge to BS valid—as requested by control bit BST2 in the corresponding word in UPM B32c CLKOUT rising edge to BS valid—as requested by control bit BST3 in the corresponding word in UPM B32d CLKOUT falling edge to BS valid— ...
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... Freescale Semiconductor, Inc. Table 6. Bus Operation Timings (continued) Num Characteristic B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid—as requested by control bit GxT4 in the corresponding word in UPM B37 UPWAIT valid to CLKOUT falling 9 edge B38 CLKOUT falling edge to UPWAIT 9 valid B39 AS valid to CLKOUT rising edge ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 2 is the control timing diagram. 2.0 V CLKOUT B 2.0 V Outputs 0.8 V Outputs Inputs Inputs A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure 3 provides the timing for the external clock. ...
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... Freescale Semiconductor, Inc. Figure 4 provides the timing for the synchronous output signals. CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 4. Synchronous Output Signals Timing Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 6 provides the timing for the synchronous input signals. CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure 6. Synchronous Input Signals Timing Figure 7 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller ...
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... Freescale Semiconductor, Inc. Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA D[0:31], DP[0:3] Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing CLKOUT B11 TS B8 A[0:31] CSx OE D[0:31], DP[0:3] Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] CSx OE D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) 24 MPC860 Family Hardware Specifications ...
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... Freescale Semiconductor, Inc. CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MOTOROLA MPC860 Family Hardware Specifications For More Information On This Product, B12 B8 B22a B27 B27a B18 B22b B22c Go to: www.freescale.com Bus Signal Timing B23 ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) 26 MPC860 Family Hardware Specifi ...
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... Freescale Semiconductor, Inc. CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MOTOROLA MPC860 Family Hardware Specifications For More Information On This Product, B12 B28b B28d B25 B28a B28c B8 Go to: www.freescale.com Bus Signal Timing ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) 28 MPC860 Family Hardware Specifications For More Information On This Product, B12 B8 B22 B28b B28d B25 B8 B28a B28c Go to: www ...
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... Freescale Semiconductor, Inc. Figure 16 provides the timing for the external bus controlled by the UPM. CLKOUT B8 A[0:31] CSx BS_A[0:3], BS_B[0:3] B35 GPL_A[0:5], GPL_B[0:5] Figure 16. External Bus Timing (UPM Controlled Signals) MOTOROLA MPC860 Family Hardware Specifications For More Information On This Product, B31a B31d ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. ...
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... Freescale Semiconductor, Inc. Figure 19 provides the timing for the synchronous external master access controlled by the GPCM. CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 7 provides interrupt timing for the MPC860. Num Characteristic I39 IRQx valid to CLKOUT rising edge (setup time) I40 IRQx hold time after CLKOUT I41 IRQx pulse width low I42 IRQx pulse width high ...
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... Freescale Semiconductor, Inc. Table 8 shows the PCMCIA timing for the MPC860. Num Characteristic P44 A(0:31), REG valid to PCMCIA 1 Strobe asserted P45 A(0:31), REG valid to ALE negation P46 CLKOUT to REG valid P47 CLKOUT to REG invalid P48 CLKOUT to CE1, CE2 asserted P49 CLKOUT to CE1, CE2 negated ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 24 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] P46 REG P48 CE1/CE2 PCOE, IORD P52 ALE D[0:31] Figure 24. PCMCIA Access Cycle Timing External Bus Read 34 MPC860 Family Hardware Specifications ...
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... Freescale Semiconductor, Inc. Figure 25 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS A[0:31] P46 REG P48 CE1/CE2 PCWE, IOWR P52 ALE D[0:31] Figure 25. PCMCIA Access Cycle Timing External Bus Write Figure 26 provides the PCMCIA WAIT signal detection timing. CLKOUT WAITx Figure 26 ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 9 shows the PCMCIA port timing for the MPC860. Num Characteristic P57 CLKOUT to OPx valid P58 HRESET negated to OPx drive P59 IP_Xx valid to CLKOUT rising edge P60 CLKOUT rising edge to IP_Xx invalid ...
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... Freescale Semiconductor, Inc. Table 10 shows the debug port timing for the MPC860. Num Characteristic P61 DSCK cycle time P62 DSCK clock pulse width P63 DSCK rise and fall times P64 DSDI input data setup time P65 DSDI data hold time P66 ...
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... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 11 shows the reset timing for the MPC860. Num Characteristic R69 CLKOUT to HRESET high impedance R70 CLKOUT to SRESET high impedance R71 RSTCONF pulse width R72 — R73 Configuration data to HRESET rising edge setup time R74 Confi ...
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... Freescale Semiconductor, Inc. Figure 31 shows the reset timing for the data bus configuration. HRESET RSTCONF D[0:31] (IN) Figure 31. Reset Timing—Configuration from Data Bus Figure 32 provides the reset timing for the data bus weak drive during configuration. CLKOUT HRESET RSTCONF ...
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... Freescale Semiconductor, Inc. IEEE 1149.1 Electrical Specifications IEEE 1149.1 Electrical Specifications Figure 33 provides the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 33. Reset Timing—Debug Port Configuration 10 IEEE 1149.1 Electrical Specifications Table 12 provides the JTAG timings for the MPC860 shown in Figure 34 through Figure 37. ...
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... Freescale Semiconductor, Inc. TCK J82 J84 Figure 34. JTAG Test Clock Input Timing TCK TMS, TDI TDO Figure 35. JTAG Test Access Port Timing Diagram TCK TRST Figure 36. JTAG TRST Timing Diagram TCK Output Signals Output Signals Output Signals Figure 37. Boundary Scan (JTAG) Timing Diagram MOTOROLA MPC860 Family Hardware Specifi ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 11 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC860. 11.1 PIP/PIO AC Electrical Specifications Table 13 provides the PIP/PIO AC timings as shown in Figure 38 through Figure 42. ...
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... Freescale Semiconductor, Inc. DATA-OUT STBO (Output) STBI (Input) Figure 39. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 40. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 41. PIP TX (Pulse Mode) Timing Diagram MOTOROLA MPC860 Family Hardware Specifications ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics CLKO DATA-IN DATA-OUT Figure 42. Parallel I/O Data-In/Data-Out Timing Diagram 11.2 Port C Interrupt AC Electrical Specifications Table 14 provides the timings for port C interrupts. Num 35 Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt minimum time between active edges 1 External bus frequency of greater than or equal to 33 ...
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... Freescale Semiconductor, Inc. Num Characteristic 40 DREQ setup time to clock high 41 DREQ hold time from clock high 42 SDACK assertion delay from clock high 43 SDACK negation delay from clock low 44 SDACK negation delay from TA low 45 SDACK negation delay from clock high 46 TA assertion to falling edge of the clock setup time (applies to ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 45. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 46. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA 46 MPC860 Family Hardware Specifications ...
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... Freescale Semiconductor, Inc. CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 47. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA 11.4 Baud Rate Generator AC Electrical Specifications Table 16 provides the baud rate generator timings as shown in Figure 48. Table 16. Baud Rate Generator Timing Num Characteristic 50 BRGO rise and fall time ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 11.5 Timer AC Electrical Specifications Table 17 provides the general-purpose timer timings as shown in Figure 49. Num Characteristic 61 TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low to TOUT valid ...
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... Freescale Semiconductor, Inc. Num Characteristic 76 L1RXD valid to L1CLK edge (L1RXD setup time) 77 L1CLK edge to L1RXD invalid (L1RXD hold time) 78 L1CLK edge to L1ST(1–4) valid 78A L1SYNC valid to L1ST(1–4) valid 79 L1CLK edge to L1ST(1–4) invalid 80 L1CLK edge to L1TXD valid 80A L1TSYNC valid to L1TXD valid ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RXD (Input) 76 L1ST(4-1) (Output) Figure 50. SI Receive Timing Diagram with Normal Clocking (DSC = 0) 50 MPC860 Family Hardware Specifications For More Information On This Product, 70 71a 72 RFSD=1 ...
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... Freescale Semiconductor, Inc. L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 51. SI Receive Timing with Double-Speed Clocking (DSC = 1) MOTOROLA MPC860 Family Hardware Specifications For More Information On This Product, 72 83a RFSD=1 77 BIT0 to: www.freescale.com ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) 80a L1TXD BIT0 (Output) 80 L1ST(4-1) (Output) Figure 52. SI Transmit Timing Diagram (DSC = 0) 52 MPC860 Family Hardware Specifications For More Information On This Product TFSD to: www ...
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... Freescale Semiconductor, Inc. L1RCLK (FE=0, CE=0) (Input) 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 53. SI Transmit Timing with Double Speed Clocking (DSC = 1) MOTOROLA MPC860 Family Hardware Specifications For More Information On This Product, CPM Electrical Characteristics ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 54 MPC860 Family Hardware Specifications For More Information On This Product, Figure 54. IDL Timing Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. 11.7 SCC in NMSI Mode Electrical Specifications Table 19 provides the NMSI external clock timing. Table 19. NMSI External Clock Timing Num Characteristic 100 RCLK1 and TCLK1 width high 101 RCLK1 and TCLK1 width low 102 RCLK1 and TCLK1 rise/fall time ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics Figure 55 through Figure 57 show the NMSI timings. RCLK1 102 106 RxD1 (Input) CD1 (Input) CD1 (SYNC Input) Figure 55. SCC NMSI Receive Timing Diagram TCLK1 102 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) ...
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... Freescale Semiconductor, Inc. TCLK1 102 102 TxD1 (Output) RTS1 (Output) CTS1 (Echo Input) Figure 57. HDLC Bus Timing Diagram 11.8 Ethernet Electrical Specifications Table 21 provides the Ethernet timings as shown in Figure 58 through Figure 62. Num Characteristic 120 CLSN width high 121 RCLK1 rise/fall time ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics Table 21. Ethernet Timing (continued) Num Characteristic 135 RSTRT active delay (from TCLK1 falling edge) 136 RSTRT inactive delay (from TCLK1 falling edge) 137 REJECT width low 138 CLKO1 low to SDACK asserted 139 ...
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... Freescale Semiconductor, Inc. TCLK1 128 131 TxD1 (Output) 133 TENA(RTS1) (Input) RENA(CD1) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 11.9 SMC Transparent AC Electrical Specifications Table 22 provides the SMC transparent timings as shown in Figure 63. Table 22. SMC Transparent Timing Num Characteristic 1 150 SMCLK clock period 151 SMCLK width low 151A SMCLK width high 152 ...
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... Freescale Semiconductor, Inc. 11.10 SPI Master AC Electrical Specifications Table 23 provides the SPI master timings as shown in Figure 64 and Figure 65. Num Characteristic 160 MASTER cycle time 161 MASTER clock (SCK) high or low time 162 MASTER data setup time (inputs) 163 Master data hold time (inputs) ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 65. SPI Master ( Timing Diagram 11.11 SPI Slave AC Electrical Specifications Table 24 provides the SPI slave timings as shown in Figure 66 and Figure 67. ...
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... Freescale Semiconductor, Inc. SPISEL (Input) SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 66. SPI Slave ( Timing Diagram SPISEL (Input) 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 SPIMISO Undef msb (Output) 175 ...
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... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 11. Electrical Specifications 2 Table 25 provides the I C (SCL < 100 kHz) timings. Table 25. I Num Characteristic 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 Bus free time between transmissions ...
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... Freescale Semiconductor, Inc. 2 Table 26 provides the I C (SCL > 100 kHz) timings. Table 26 Num Characteristic 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 Bus free time between transmissions 203 Low period of SCL 204 High period of SCL 205 Start condition setup time ...
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... Freescale Semiconductor, Inc. UTOPIA AC Electrical Specifications UTOPIA AC Electrical Specifications Table 27. UTOPIA AC Electrical Specifications (continued) Num Signal Characteristic U1a UtpClk rise/fall time (external clock option) Duty cycle Frequency U2 RxEnb and TxEnb active delay U3 UTPB, SOC, Rxclav and Txclav setup time U4 UTPB, SOC, Rxclav and Txclav hold time ...
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... Freescale Semiconductor, Inc. Figure 70 shows signal timings during UTOPIA transmit operations. UtpClk U5 5 PHSELn TxClav HighZ at MPHY TxEnb UTPB SOC Figure 70. UTOPIA Transmit Timing 13 FEC Electrical Characteristics This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the timing specifi ...
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... Freescale Semiconductor, Inc. FEC Electrical Characteristics FEC Electrical Characteristics Figure 71 shows MII receive signal timing. MII_RX_CLK (Input) MII_RXD[3:0] (Inputs) MII_RX_DV MII_RX_ER Figure 71. MII Receive Signal Timing Diagram 13.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – ...
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... Freescale Semiconductor, Inc. Figure 72 shows the MII transmit signal timing diagram. MII_TX_CLK (Input) MII_TXD[3:0] (Outputs) MII_TX_EN MII_TX_ER Figure 72. MII Transmit Signal Timing Diagram 13.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 30 provides information on the MII async inputs signal timing. Table 30. MII Async Inputs Signal Timing ...
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... Freescale Semiconductor, Inc. FEC Electrical Characteristics FEC Electrical Characteristics 13.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 31 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation ...
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... Freescale Semiconductor, Inc. 14 Mechanical Data and Ordering Information Table 32 provides information on the MPC860 revision D.3 and D.4 derivative devices. Table 32. MPC860 Family Revision D.3 and D.4 Derivatives Device MPC855T MPC860DE MPC860DT MPC860DP MPC860EN MPC860SR MPC860T MPC860P 1 Serial communications controller (SCC channels at 40 MHz or 2 channels at 25 MHz MOTOROLA MPC860 Family Hardware Specifi ...
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... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information Table 33 identifies the packages and operating frequencies available for the MPC860. Table 33. MPC860 Family Package/Frequency Availability Package Type Ball grid array (ZP suffix) Ball grid array (CZP suffix) 1 Where nn specifi ...
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... Freescale Semiconductor, Inc. Table 34. MPC860P Package/Frequency Availability (continued) Ball grid array (CZP suffix) 1 Where nn specifies version D.3 (as D3) or D.4 (as D4) MOTOROLA MPC860 Family Hardware Specifications For More Information On This Product, Mechanical Data and Ordering Information 50 –40° to 95°C 66 –40° to 95°C Go to: www ...
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... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information 14.1 Pin Assignments Figure 75 shows the top view pinout of the PBGA package. For additional information, see the MPC860 PowerQUICC User’s Manual, or the MPC855T User’s Manual. NOTE: This is the top view of the device. ...
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... Freescale Semiconductor, Inc. 14.2 Mechanical Dimensions of the PBGA Package Figure 76 shows the mechanical dimensions of the PBGA package TOP VIEW BOTTOM VIEW Figure 76 ...
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... Freescale Semiconductor, Inc. Document Revision History Document Revision History 15 Document Revision History Table 35 lists significant changes between revisions of this hardware specification. Table 35. Document Revision History Revision Date 5.1 11/2001 Revised template format, removed references to MAC functionality, changed Table 6 B23 max value @ 66 MHz from 2ns to 8ns, added this revision history table ...
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... Freescale Semiconductor, Inc. Document Revision History Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK 77 MPC860 Family Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Document Revision History Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK 78 MPC860 Family Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Document Revision History Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK 79 MPC860 Family Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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