PUMX1T/R PMC-Sierra Inc, PUMX1T/R Datasheet
PUMX1T/R
Related parts for PUMX1T/R
PUMX1T/R Summary of contents
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S/UNI-622-MAX DATASHEET PMC-1980589 USER NETWORK INTERFACE PMC-Sierra, Inc. PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN (622-MAX UNI- 622-MAX DATASHEET RELEASED ISSUE 5: DECEMBER 1999 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM5356 S/UNI-622-MAX ...
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... THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR MONITOR (RASE) ............................................................................................................................45 10.5 RECEIVE PATH OVERHEAD PROCESSOR (RPOP) ....................................................46 10.6 RECEIVE ATM CELL PROCESSOR (RXCP)..................................................................50 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR IT’S CUSTOMER’S INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) ...
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... PARALLEL LINE INTERFACE.......................................................................................256 14.2 ATM UTOPIA LEVEL 2 SYSTEM INTERFACE .............................................................257 14.3 ATM UTOPIA LEVEL 3 SYSTEM INTERFACE .............................................................258 15 ABSOLUTE MAXIMUM RATINGS...............................................................................................260 16 D.C. CHARACTERISTICS...........................................................................................................261 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR IT’S CUSTOMER’S INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) ii ...
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... UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING ........................................................274 18.6 JTAG TEST PORT TIMING ...........................................................................................276 19 ORDERING AND THERMAL INFORMATION .............................................................................278 20 MECHANICAL INFORMATION....................................................................................................279 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR IT’S CUSTOMER’S INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) iii ...
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... Industrial temperature range (- +85 C). 304 pin Super BGA package. 1.2 The SONET Receiver Provides a serial interface at 622.08 Mbit/s with clock and data recovery. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) ...
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... Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support to read extracted cells from an internal four-cell FIFO buffer. 1.4 The SONET Transmitter Synthesizes the 622.08 MHz transmit clock from a 77.76 MHz reference. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX ...
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... FIFO. Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support for writing cells into an internal four-cell FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... APPLICATIONS WAN and Edge ATM switches. LAN switches and hubs. Routers and Layer 3 Switches Network Interface Cards and Uplinks PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) ...
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... Design Hierarchy (SDH)”, January 1994. ITU, Recommendation G.783 - "Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks", 1996. ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
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... Loss of Frame LOH Line Overhead LOP Loss of Pointer LOS Loss of Signal LOT Loss of Transition NC No Connect, indicates an unused pin PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 6 ...
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... Transmit Section Overhead Processor TXCP Transmit ATM Cell Processor UI Unit Interval UNI User-Network Interface VCI Virtual Connection Indicator VPI Virtual Path Indicator PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 7 ...
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... S/UNI-622-MAX DATASHEET PMC-1980589 WAN Wide Area Network XOR Exclusive OR logic operator PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 8 ...
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... An application with a UTOPIA Level 2 system side interface is shown in Figure 1. An application with a UTOPIA Level 3 system side is shown in Figure 2. The initial configuration and ongoing control and monitoring of the S/UNI-622-MAX are normally provided via a generic microprocessor interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
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... Interface ATM Layer Device TxClk TxEnb TxClav TxSOC TxPrty TxData[15:0] RxClk RxEnb RxClav RxSOC RxPrty RxData[15:0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX TFCLK TENB TCA LIFSEL TSOC TPRTY TDAT[15:0] RXD+/- SD ...
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... Interface ATM Layer Device TxClk TxEnb TxClav TxSOC TxPrty TxData[7:0] RxClk RxEnb RxVal RxSOC RxPrty RxData[7:0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX TFCLK TENB TCA LIFSEL TSOC TPRTY TDAT[7:0] RXD+/- SD ...
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TXD+/- TDREF1, TDREF0 ATP[0] Tx Line Tx I/F Section O/H Processor PTCLK POUT[7:0] FPOUT Section Trace Buffer Trace Buffer RBYP PECLV REFCLK+/- RXD+/- Rx RRCLK+/- Section O/H SD Processor Rx Line ATP[1] I/F PICLK PIN[7:0] FPIN OOF JTAG Test Access ...
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... FIFO contains less than one complete cell. The S/UNI-622-MAX provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... TTL/CMOS compatible digital outputs. High speed inputs and outputs support 3.3V and 5.0V compatible pseudo-ECL (PECL). The S/UNI-622-MAX is packaged in a 304 pin SBGA package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... PMC-1980589 8 PIN DIAGRAM The S/UNI-622-MAX is available in a 304 pin SBGA package having a body size and a ball pitch of 1.27 mm. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) ...
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... RXD+ Differential RXD- PECL Input RRCLK+ Differential RRCLK- PECL Input PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. E21 The receive bypass (RBYP) input disables clock recovery. If RBYP is high, RXD+/- is sampled on the rising edge of RRCLK+/- ...
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... Type SD PECL Input R2 TXD+ Differential TXD- PECL Output PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. The receive signal detect PECL input (SD) indicates the presence of valid receive signal power from the Optical Physical Medium Dependent Device ...
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... Pin Name Type LIFSEL Input PICLK Input OOF Output PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. C23 The line interface select (LIFSEL) selects between serial and parallel line interface modes of operation. ...
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... PIN[4] PIN[5] PIN[6] PIN[7] PTCLK Input FPOUT Output PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. AB17 The active-high framing position input (FPIN) signal indicates the SONET/SDH frame position on the PIN[7:0] bus. In parallel interface operation, the byte on the PIN[7:0] bus indicated by FPIN is the third A2 of the SONET/SDH framing pattern ...
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... POUT[0] Output POUT[1] POUT[2] POUT[3] POUT[4] POUT[5] POUT[6] POUT[7] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. AA14 In parallel interface operation, the parallel outgoing stream, AB14 (POUT[7:0]) carries the scrambled STS-12c/STM-4-4c or STS- AC13 3c/STM-1 stream in byte-serial format ...
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... Output RALRM Output TCLK Output TFPO Output TFPI Input PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. AC20 The receive clock (RCLK) provides a timing reference for the S/UNI-622-MAX receive function outputs. RCLK is a 77.76 MHz, 50% duty cycle clock ...
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... PMC-1980589 Pin Name Type APS[0] I/O APS[1] APS[2] APS[3] APS[4] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. A19 The APS Port bus (APS[4:0 bi-directional control bus that C18 can be used to implement a 1+1 APS system. When the B18 APSPOE register bit is set low, the APS[4:0] bus is an input ...
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... DATASHEET PMC-1980589 9.4 ATM (UTOPIA) System Interface Pin Name Type SYSSEL Input PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. AA23 The system interface select (SYSSEL) pin selects between the 16-bit UTOPIA Level 2 mode and the 8-bit UTOPIA Level 3 mode of the system side interfaces for ATM ...
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... TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. M22 UTOPIA transmit FIFO write clock (TFCLK) is used to write ATM cells to the four cell transmit FIFO. ...
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... DATASHEET PMC-1980589 Pin Name Type TSOC Input TENB Input PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. L21 The UTOPIA transmit start of cell (TSOC) signal marks the start of a cell structure on the TDAT bus. ...
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... DATASHEET PMC-1980589 Pin Name Type TCA Output RFCLK Input PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. L23 The UTOPIA transmit cell available (TCA) signal provides direct status indication of when cell space is available in the transmit FIFO ...
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... RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RVAL Output PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. W21 UTOPIA receive cell data (RDAT[15:0]) bus carries the ATM cell W22 octets that are read from the receive FIFO. ...
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... DATASHEET PMC-1980589 Pin Name Type RSOC Output RPRTY Output PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. P23 The UTOPIA receive start of cell (RSOC) signal marks the start of a cell structure on the RDAT bus. ...
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... DATASHEET PMC-1980589 Pin Name Type RENB Input RCA Output PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. N23 The UTOPIA receive read enable (RENB) is used to initiate reads from the receive FIFO. The system may de-assert RENB unable to accept more data ...
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... A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] Input PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. C11 The active-low chip select (CSB) signal is low during S/UNI-622- MAX register accesses. When CSB is high, the RDB and WRB inputs are ignored. ...
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... Pin Name Type RSTB Input ALE Input INTB Output PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. B10 The active-low reset (RSTB) signal provides an asynchronous S/UNI-622-MAX reset. RSTB is a Schmitt triggered input with an integral pull-up resistor ...
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... TMS Input TDI Input TDO Output TRSTB Input PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. A9 The test clock (TCK) signal provides clock timing for test operations that are carried out using the IEEE P1149.1 test access port ...
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... Analog Signals Pin Name Type TDREF0 Analog TDREF1 ATP[0] Analog ATP[1] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. K1 The transmit data reference (TDREF0 and TDREF1) analog pins K2 are provided to create calibrated currents for the PECL output transceivers TXD+/- ...
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... QAVD[0] Analog QAVD[1] Power QAVS[0] Analog QAVS[1] Ground PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. Digital input biases (VBIAS). When tied to +5V, the VBIAS E20 inputs are used to bias the wells of the digital inputs so that the pads can tolerate their inputs without forward biasing internal ESD protection devices ...
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... S/UNI-622-MAX DATASHEET PMC-1980589 Pin Name Type VDD Digital Power PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. A1 The digital power (VDD) pins should be connected to a well- A23 decoupled +3.3 V digital power supply. ...
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... S/UNI-622-MAX DATASHEET PMC-1980589 Pin Name Type VSS Digital Ground PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. A2 The digital ground (VSS) pins should be connected to the digital A6 ground of the digital power supply. ...
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... AVD[23] AVD[24] AVD[25] AVD[26] AVD[27] AVD[28] AVD[29] AVD[30] AVD[31] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. D3 The analog power (AVD) pins for the analog core. The AVD pins D2 should be connected through passive filtering networks to a well- F2 decoupled +3 ...
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... AVS[31] AVS[32] AVS[33] AVS[34] AVS[35] AVS[36] AVS[37] AVS[38] AVS[39] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Pin Function No. E4 The analog ground (AVS) pins for the analog core. The AVS C1 pins should be connected to the analog ground of the analog G3 power supply ...
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... I/O pins to power supply pins. Under extreme conditions it is possible to damage these ESD protection devices or trigger latch up. Please adhere to the recommended power supply sequencing as described in the Operation section of this document. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
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... The jitter tolerance setup used a Hewlett Packard HFBR-5208M multi-mode fiber optic transceiver with approximately -10 dBm input power. The RTYPE register bit in CRSI-622 was set to logic zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... RSOP to the new frame alignment. While in frame, the CRSI-622 maintains the byte alignment of the serial-to-parallel converter until RSOP declares out of frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 1000 ...
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... The Error Monitor Block calculates the received section BIP-8 error detection code (B1) based on the scrambled data of the complete STS-12c/STM-4-4c frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 code is compared PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line AIS is removed when any pattern other than 111 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
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... A protection switching byte failure alarm is declared when twelve successive frames have been received, where no three consecutive frames contain identical K1 bytes. The protection switching byte failure alarm is removed upon detection of three consecutive PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Illegal values are interpreted a zero errors ...
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... STS-12c/STM-4-4c stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm three states are defined as shown below: NORM_state (NORM) AIS_state (AIS) LOP_state (LOP) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX ...
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... The following table defines the events (indications) shown in the state diagram. Table 1: Pointer Interpreter Event (Indications) Description Event (Indication) norm_point NDF_enable AIS_ind inc_ind PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE eq_new_point inc_ind / NDF_enable dec_ind ...
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... When the received pointer returns to an in-range value, the S/UNI-622-MAX will interpret it correctly. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 inverted + previous NDF_enable, inc_ind or dec_ind more than 3 ...
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... Pointer Interpreter block via register bits. An invalid NDF code is any NDF code that does not match the NDF enabled or NDF disabled definitions. The third occurrence of equal PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
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... The ERDIV[2:0] signal reflects the state of the filtered ERDI value (G1 byte bits 5, 6, & 7). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in Figure 5. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... RXCP Match Header Pattern and RXCP Match Header Mask registers. Idle/Unassigned cells are assumed to contain the all zeros pattern in the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
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... No Errors Detected (Pass Cell) DELTA consecutive correct HCS’s (From PRESYNC state) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Figure 6: HCS Verification State Diagram ATM DELINEATION SYNC STATE Apparent Multi-Bit Error (Drop Cell) ...
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... UI RMS when measured using a high pass filter with a 12 kHz cutoff frequency. The REFCLK reference should be within ±20 ppm to meet the SONET/SDH free-run accuracy requirements specified in GR-253-CORE. The CSU may require a software reset when the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... Note that the framing bytes and the identity bytes are not scrambled. All zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
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... The concatenation indication (the NDF field set to 1001, I-bits and D-bits set to all ones, and unused bits set to all zeros) is inserted in the second and third pointer byte locations in the transmit stream. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... HCS generation and insertion, and performs ATM cell scrambling. The TXCP contains a four cell transmit FIFO. An idle or unassigned cell is transmitted if a complete ATM cell has not been written into the FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... In general, the management functions include filling the receive FIFO, indicating when the receive FIFO contains cells, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... If the programmed depth is less than four, more than one cell may be written after TCA is asserted as the TXCP still allows four cells to be stored in its FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... S/UNI-622-MAX APS Control and Status 007 S/UNI-622-MAX Miscellaneous Configuration 008 S/UNI-622-MAX Auto Line RDI Control 009 S/UNI-622-MAX Auto Path RDI Control PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Table 3: Register Memory Map Register Description PM5356 S/UNI-622-MAX ...
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... Reserved 027 Reserved 028 Reserved 029 Reserved 02A Reserved 02B Reserved 02C Reserved 02D Reserved 02E Reserved PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Register Description PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 60 ...
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... TPOP Reserved 04C TPOP Reserved 04D TPOP Reserved 04E TPOP Concatenation LSB 04F TPOP Concatenation MSB 050 Reserved PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Register Description PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 61 ...
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... RXCP Idle Cell Count MSB 071 RXCP Reserved 072 RXCP Reserved 073 RXCP Reserved 074 RXCP Reserved 075 RXCP Reserved PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Register Description PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 62 ...
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... Reserved 095 Reserved 096 DLL RFCLK 097 DLL RFCLK 098 Reserved 099 Reserved 09A DLL TFCLK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Register Description PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 63 ...
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... S/UNI-622-MAX Concatenation Interrupt Status 0FE Reserved 0FF Reserved 100 S/UNI-622-MAX Master Test Register 101 -- Reserved for Test 1FF PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Register Description PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 64 ...
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... For all register accesses, CSB must be low. Addresses that are not shown must be treated as Reserved. A[8] is the test resister select (TRS) and should be set low for normal mode register access. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
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... Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-622-MAX operates as intended, reserved register bits must be written with their default value as indicated by the register bit description. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
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... S/UNI-622-MAX in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Otherwise, the effect of a software reset is equivalent to that of a hardware reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... The Diagnostic Loopback, DLE bit enables the S/UNI-622-MAX diagnostic loopback where the S/UNI-622-MAX’s Transmit are directly connected to the Receive ATM. When DLE is logic one, loopback is enabled. Under this operating condition, the S/UNI-622-MAX does not PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... The Transmit Frame Pulse Enable (TFPEN) enables the TFP input. When TFPEN is set low, the TFP input is disabled. When TFPEN is set high, the TFP input is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
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... S/UNI-622-MAX Line RDI Control Registers. DPLE: The Diagnostic Path Loopback, DPLE bit enables the S/UNI-622-MAX diagnostic loopback where the S/UNI-622-MAX’s Transmit Path Overhead Processor (TPOP) is directly PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
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... RXD+/- differential inputs is mapped to the TXD+/- differential outputs. Under this operating condition, the S/UNI-622-MAX continues to operates normally in the receive direction. The SDLE, SLLE or LOOPT bits should not be set high simultaneously. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 76
... The TFCLK active (TFCLKA) bit monitors for low to high transition on the TFCLK transmit system interface clock input. TFCLKI is set high on a rising edge of PTLCKI and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 77
... The TCLK active (TCLKA) bit monitors for low to high transition on the TCLK transmit line rate clock. TCLKA is set high on a rising edge of TCLKI and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 78
... RXCP Interrupt Enable/Status Register. TXCPI: The TXCPI bit is high when an interrupt request is active from the TXCP block. The TXCP interrupt sources are enabled in the TXCP Interrupt Control/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 79
... The CONCATI bit is high when an interrupt request is active from the Concatenation Interrupt Status Register. The CONCAT interrupt sources are enabled in the Concatenation Status and Enable Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 80
... The CSPII bit is high when an interrupt request is active from the Clock Synthesis and PISO block (CSPI-622). The CSPII interrupt sources are enabled in the Clock Synthesis Interrupt Control/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 81
... RDI information on the APS[4:0] pins is transmitted by TPOP. When APSRDI is set low, the RDI information from RPOP is transmitted by TPOP. The APSOE bit must be set low when APSRDI is set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 82
... FIFO is held in reset. When APSFRST is set low, the FIFO may be reset during system reset. The APSFRST should be set high for at least 4 TCLK cycles when either S/UNI-622-MAX devices in the 1+1 APS configuration are reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 83
... When TSOC3 is set low, the transmit side of the S/UNI-622-MAX is configured for STS-12c/STM-1 operation. Setting TSOC3 high when LIFSEL is equal is low is invalid as the analog interface only operate at STS-12c/STM-4-4c line rates. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 84
... When TX_LIFINV is set high, the polarity of the LIFSEL input is inverted. When TX_LIFINV is set low, the LIFSEL input operates normally for the transmit side. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 85
... When SFLRDI is set high, the transmit line RDI will be inserted. When SFLRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 86
... When SDLRDI is set high, the transmit line RDI will be inserted. When SDLRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 87
... The Line Alarm Indication Signal PRDI (ALRMPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of one of the following alarm conditions: Loss of Signal (LOS), Loss of Frame (LOF) and Line Alarm Indication Signal (LAIS). When PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 88
... RDI in the transmit data stream upon detection of this alarm. When LCDPRDI is set high, the transmit path RDI will be inserted. When LCDPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 89
... PAIS occurs, bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high. NOPAISEPRDI has precedence over PSLMERDI, TIMEPRDI and UNEQERDI. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 90
... G1 byte is set high while bit 7 of the G1 byte is set low. When LCDEPRDI is set low, loss of ATM cell delineation has no effect on path RDI. In addition, this bit has no effect when EPRDI_EN is set low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 91
... When set high, the NOPAISCONEPRDI bit disables enhanced path RDI assertion when path AIS concatenation (PAISCON) events are detected in the receive stream. When NOPAISCONEPRDI is set high and PAISCON occurs, bit 6 of the G1 byte is set low while bit PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 92
... When set high, the PAISCONPRDI bit enables path RDI assertion when path AIS concatenation (PAISCON) events are detected in the receive stream. When PAISCONPRDI is set low, path AIS concatenation events have no effect on path RDI. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 93
... The SDINS bit enables the insertion of path AIS in the receive direction upon the declaration of signal degrade (SD). If SDINS is a logic one, path AIS is inserted into the SONET/SDH frame when SD is declared. Path AIS is terminated when SD is removed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 94
... When PAISCONPAIS is set low, Path AIS concatenation events will not assert path AIS. Reserved: The reserved bit must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 95
... RALRM output. When the enable bit is high, the corresponding alarm indication is combined with other alarm indications and output on RALRM. When the enable bit is low, the corresponding alarm indication does not affect the RALRM output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 96
... PAIS PRDI PERDI PSLM CON Reserved: The reserved bit must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Description Loss of signal Loss of frame Out of Frame Line Alarm Indication Signal ...
Page 97
... ALGO2 bit position, the framer is enabled to use the first of the framing algorithms where all the A1 framing bytes and all the A2 framing bytes are examined. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 98
... BLKBIP bit position, one or more errors in the BIP-8 byte result in a single error being accumulated in the B1 error counter. When a logic zero is written to the BLKBIP bit position, all errors in the B1 byte are accumulated in the B1 error counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 99
... The LOSI bit is the loss of signal interrupt status bit. LOSI is set high when a change in the loss of signal state occurs. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 100
... BIPEI: The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is set high when a section layer (B1) bit error is detected. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 101
... The count can also be polled by writing to the S/UNI-622-MAX Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, RXCP and TXCP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 102
... The DS bit is set to logic one to disable the scrambling of the STS-12c/STM-4-4c stream. When logic zero, scrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 103
... When DBIP8 is set to logic one, the B1 byte is inverted. DLOS: The DLOS bit controls the insertion of all zeros in the STS-12c/STM-4-4c stream. When DLOS is set to logic one, the transmit stream is forced to 0x00. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 104
... The LRDIDET bit determines the line RDI alarm detection algorithm. When LRDIDET is set to logic one, line RDI is declared when a 110 binary pattern is detected in bits 6, 7 and 8 of PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
Page 105
... B2 error event counter is incremented only once per frame whenever one or more B2 bit errors occur during that frame. When BIPWORD is logic zero, the B2 error event counter is increment for each and every B2 bit error that occurs during that frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 106
... RDI state changes. LAISE: The LAISE bit is an interrupt enable for line AIS. When LAISE is set to logic one, an interrupt is generated when line AIS changes state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 107
... FEBEE: The FEBEE bit is an interrupt enable for the line far end block errors. When FEBEE is set to logic one, an interrupt is generated when FEBE (Z2) is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 108
... Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default LBE[7] X LBE[6] X LBE[5] X LBE[4] X LBE[3] X LBE[2] X LBE[1] ...
Page 109
... The count can also be polled by writing to the S/UNI-622-MAX Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, RXCP and TXCP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 110
... Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default LFE[7] X LFE[6] X LFE[5] X LFE[4] X LFE[3] X LFE[2] X LFE[1] ...
Page 111
... The count can also be polled by writing to the S/UNI-622-MAX Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, RXCP and TXCP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 112
... APSREG is a logic one, the transmit APS channel is inserted from the TLOP Transmit K1 Register and the TLOP Transmit K2 Register. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 113
... Bit 0 R/W DBIP96: The DBIP96 bit controls the insertion of bit errors continuously in the line BIP-96 bytes (B2). When DBIP96 is set to logic one, the B2 bytes are inverted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default ...
Page 114
... The contents of this register, and the TLOP Transmit K2 Register are inserted in the SONET/SDH stream starting at the next frame boundary. Successive writes to this register must be spaced at least two frames (250 µs) apart. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 115
... TLOP Transmit K1 Register. A coherent APS code value is ensured by writing the desired K2 APS code value to this register before writing the TLOP Transmit K1 Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 116
... TS1[3] is the most significant bit, corresponding to the first bit transmitted. TS1[0] is the least significant bit, corresponding to the last bit transmitted. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 117
... SDH_J0/Z0 register. J0/Z0[7] is the most significant bit, corresponding to the first bit (bit 1) transmitted. J0/Z0[0] is the least significant bit, corresponding to the last bit (bit 8) transmitted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 118
... S/UNI-622-MAX has declared path RDI. PAISV: The PAISV bit is read to determine the path AIS state. When PAISV is a logic one, the S/UNI- 622-MAX has declared path AIS. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 119
... The PLOPV bit is read to determine the loss of pointer state. When PLOPV is a logic one, the S/UNI-622-MAX has declared LOP. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 120
... PSL5 is set low, the PSL is updated when the same value is received for 3 consecutive frames. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 121
... The PAISI bit is the path alarm indication signal interrupt status bit. PAISI is a logic one when a change in the path AIS state occurs. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
Page 122
... The current path signal label can be read from the RPOP Path Signal Label register. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
Page 123
... ERDII: The ERDII bit is set high when a change is detected in the received enhanced RDI state. This bit is cleared when the RPOP Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 124
... RPOP Pointer Interrupt Status register is read. DISCOPAI: The DISCOPAI bit is set to logic one when the RPOP detects a discontinuous change of pointer. DISCOPAI is cleared when the RPOP Pointer Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 125
... ILLJREQI: The ILLJREQI bit is set to logic one when the RPOP detects an illegal pointer justification request event. ILLJREQI is cleared when the RPOP Pointer Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 126
... RDI state changes. PAISE: The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic one, an interrupt is generated when the path AIS state changes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 127
... The PSLE bit is the interrupt enable for changes in the received path signal label. When PSLE is a logic one, an interrupt is generated when the received C2 byte changes. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 128
... This register allows interrupt generation to be enabled for path level alarm and error events. ERDIE: When REDIE is a logic one, an interrupt is generated when a path enhanced RDI is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 129
... NDF code is received. DISCOPAE: When a logic one is written to the DISCOPAE interrupt enable bit position, an interrupt is generated when a change of pointer alignment event occurs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 130
... When a logic one is written to the ILLJREQE interrupt enable bit position, an interrupt is generated when an illegal pointer justification request is received. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 131
... S0, S1: The S0 and S1 bits contain the two S bits received in the last H1 byte. These bits should be software debounced to ensure the proper values are recieved. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 132
... EXTD: The EXTD bit extends the registers to facilitate additional mapping. If this bit is set high, the register mapping, for registers 0x30, 0x31 and 0x33, are extended. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 133
... The PSL[7:0] bits contain the path signal label byte (C2). The value in this register is updated to a new path signal label value if the same new value is observed for three of five consecutive frames, depending on the status of the PSL5 bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 134
... This transfer and reset is carried out in a manner that ensures that coincident events are not lost. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 135
... RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register addresses. Such a write transfers the internally accumulated error count to the Path FEBE Registers within approximately 7 µs and simultaneously resets the internal counter to PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 136
... FEBE code for that block is between 1 and 8 inclusive. When BLKFEBE is set low, path FEBE errors are accumulated on a error basis. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 137
... When a logic zero is written to this bit, pointer justification indications in the receive stream are followed without regard to the proximity of previous active offset changes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 138
... S/UNI-622-MAX DATASHEET PMC-1980589 Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 134 ...
Page 139
... RDI bits of the G1 byte not overwritten by the TPOP block, regardless of EPRDISRC. When EPRDIEN is logic one and EPRDISCR is logic zero, the extended RDI bits of the G1 byte, bits 6 and 7, are inserted according to the value in the G1[1:0] register PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 140
... RDI scheme is used and the three G1[7:5] bits are used to indicate PRDI. The actual three bit code will be controlled according to the EPRDISRC. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 141
... NDF pattern for the first frame; subsequent frames have the new data flag bit positions set to the normal pattern (0110) unless the NDF bit described above is set to a logic one. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 142
... H1 and H2 bytes of the transmit stream. At least one corrupted pointer is guaranteed to be sent. If FTPTR is a logic zero, a valid pointer is inserted. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 143
... Arbitrary Pointer LSB and MSB Registers inserting positive and negative pointer movements using the PSE and NSE register bits recommended the CPTR[9:0] value be software debounced to ensure a correct value is received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 144
... If the FTPTR bit in the TPOP Pointer Control register is a logic one, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the transmit stream. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 145
... PLD bit in the TPOP Pointer Control Register) or when new data flag generation is enabled using the NDF bit in the TPOP Pointer Control Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 146
... Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W This register allows control over the path trace byte. J1[7:0]: The J1[7:0] bits are inserted in the J1 byte position in the transmit stream PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default J1[7] 0 J1[6] 0 J1[5] 0 ...
Page 147
... This register allows control over the path signal label. Upon reset the register defaults to 0x01, which signifies an equipped unspecific payload. C2[7:0]: The C2[7:0] bits are inserted in the C2 byte position in the transmit stream. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 148
... FEBEs accumulated on primary input FEBE during the last frame. When reading this register, a non-zero value in these bit positions indicates that the insertion of this value is still pending. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 149
... STS-1 #5 and STS the concatenated stream. The default values represent the normal concatenation indication (all ones in the pointer bits, zeros in the unused bits, and NDF indication). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 150
... The ROOLI bit is the reference out of lock interrupt status bit. ROOLI is set high when the ROOLV register goes high, indicating that the PLL is not locked to the reference clock REFCLK. ROOLI is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 151
... Clock Synthesis Unit may lose lock to the reference. When this occurs, the ROOLV will remain high until the CSU is reset using the CSURESETLPF and CSURSET registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 152
... When CSURESET is set low, the CSU RESET input is controlled by the system reset and digital test mode. The CSURESETLPF and CSURESET should be held high for 10ms to properly reset the CSU. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 153
... When PFPEN is a logic zero, the FPIN input is ignored and the SONET/SDH framing is performed on the PIN[7:0] data. When PFPEN is logic one, the SONET/SDH framer is ignored and the PIN[7:0] bus is assumed to PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 154
... SD input is logically XOR’ed with the value of the SDINV register. Therefore, when SDINV is a logic zero, valid signal power is indicated by the SD input high. When SDINV is a logic one, valid signal power is indicated by the SD input low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 155
... The recovered reference out of lock status indicates the clock recovery phase locked loop is unable to lock to the reference clock on REFCLK. ROOLV is a logic one if the divided down synthesized clock frequency is not within approximately 488ppm of the REFCLK frequency. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 156
... LOCK is a logic zero if the CRU is locking or locked to the reference clock. LOCK is a logic one if the CRU is locking or locked to the receive data. LOCK is invalid if the CRU is not used. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 157
... When RTYPE is a logic zero, the CRU operates with improved tolerance and relaxed jitter transfer. When RTYPE is a logic one, the CRU operates with improved jitter transfer. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 158
... When DDSCR is set high, cell payload descrambling is disabled. When DDSCR is set low, payload descrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 159
... HCS error. When HCSPASS is a logic zero, cells containing an uncorrectable HCS error are dropped. When HCSPASS is a logic one, cells are passed to the receive FIFO regardless of PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 160
... RXCP is passed into its FIFO without the requirement of having to find cell delineation first. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 161
... When RCAINV is a logic zero, the polarity of RCA is not inverted. RCAINV must be set low when the system interface is configured for Level 3 operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 162
... RPRTY is the even parity bit for outputs RDAT[15:0]. When RXPTYP is set low, RPRTY is the odd parity bit for outputs RDAT[15:0]. RXPTYP must be set low when the system interface is configured for Level 3 operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 163
... XFERI being logic one) has not been acknowledged before the next accumulation interval has occurred and that PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
Page 164
... This update is initiated by writing to one of the RXCP Count register locations or to the S/UNI-622-MAX, Master Reset and Identity register. XFERI is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 165
... LCD Count Threshold register. When LCD is low, no OCD has persisted for the number of cells specified PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 166
... When OOCDV is low, the cell delineation state machine is in the ’SYNC’ state and cells are passed through the receive FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 167
... Likewise, LCD is not de-asserted until receive cell processor is in cell delineation for the number of cell periods specified by LCDC[10:0]. The default value of LCD[10:0] is 360, which translates to an average cell period of 0.71 µs and a default LCD integration period of 255 µs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 168
... Match Header Mask Register. The IDLEPASS bit in the RXCP Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 169
... This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter. A logic one in this bit position enables the MCLP bit in the pattern register to be compared. A logic zero causes the masking of the MCLP bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 170
... The contents of these registers are valid a maximum of 40 RCLK periods after a transfer is triggered by a write to one of RXCP’s performance monitor counters or to the S/UNI-622-MAX Master Reset, and Identity register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 171
... The contents of these registers are valid a maximum of 40 RCLK periods after a transfer is triggered by a write to one of RXCP’s performance monitor counters or to the S/UNI-622-MAX Master Reset and Identity register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 172
... Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default RCELL[7] X RCELL[6] X RCELL[5] X RCELL[4] X RCELL[3] X RCELL[2] X RCELL[1] ...
Page 173
... The contents of these registers are valid a maximum of 67 RCLK periods after a transfer is triggered by a write to one of RXCP’s performance monitor counters or to the S/UNI-622-MAX Master Reset and Identity register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 174
... Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default ICELL[7] X ICELL[6] X ICELL[5] X ICELL[4] X ICELL[3] X ICELL[2] X ICELL[1] ...
Page 175
... RCLK periods after a transfer is triggered by a write to one of RXCP's performance monitor counters or to the S/UNI-622-MAX’s Master Reset, and Identity register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 176
... The Header Scramble enable bit, HSCR, enables scrambling of the ATM five octet header along with the payload. When set to logic one, the ATM header and payload are both PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ...
Page 177
... TPRTY is the odd parity bit for the TDAT input bus. TPTYP must be set low when the system interface is configured for Level 3 operation. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 178
... TCA is deasserted. Note that regardless of what fill level FIFODP[1:0] is set to, the transmit cell processor can store 4 complete cells. The selectable FIFO cell depths are shown below: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 179
... When TCAINV is a logic zero, the polarity of TCA is not inverted. TCAINV must be set low for when the system interface is configured for Level 3 operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 180
... Transmit Cell Count registers. When XFERE is set high, the interrupt is enabled. Reserved: These bits should be set to their default values for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 181
... The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO when it is already full. When FOVRE is set to logic one, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 182
... The TPRTYE bit enables transmit parity interrupts. When set to logic one, parity errors are indicated on INTB and TPRTYI. When set to logic zero, parity errors are indicated using bit TPRTYI, but are not indicated on output INTB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 183
... Idle/unassigned cells are transmitted when the TXCP detects that no outstanding cells exist in the transmit FIFO. The all zeros pattern is transmitted in the VCI and VPI fields of the idle cell. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 184
... TXCP detects that the transmit FIFO contains no outstanding cells. PAYLD[7] is the most significant bit and is the first bit transmitted. PAYLD[0] is the least significant bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 185
... Type Bit 7 R Bit 6 R Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default TCELL[7] X TCELL[6] X TCELL[5] X TCELL[4] X TCELL[3] X TCELL[2] X TCELL[1] ...
Page 186
... The contents of these registers are valid after a maximum of 67 TCLK cycles after a transfer is triggered by a write to a TXCP Transmit Cell count Register or the S/UNI-622-MAX Master Reset and Identity register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 187
... RDAT[7:0]. When RL3PP is set to low, RPRTY is the odd parity bit for outputs RDAT[7:0]. RL3PP is ignored when the system interface is configured for Level 2 operation. RL3PP is ignored when the system interface is configured for Level 2 operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 188
... TDAT[7:0]. When TL3PP is set to low, TPRTY is the odd parity bit for input RDAT[7:0]. TL3PP is ignored when the system interface is configured for Level 2 operation. TL3PP is ignored when the system interface is configured for Level 2 operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 189
... Writing to this register performs a software reset of the DLL. The software reset will disrupt the Receive Level 2/3 interface controlled by RFCLK clock. Any FIFOs associated with the RFCLK (RXCP) must be reset using FIFORST after the DLL is reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 190
... When the RFCLK input changes from a logic zero to a logic one, the RFCLKI register bit is set to logic one. The RFCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 191
... Writing to this register performs a software reset of the DLL. The software reset will disrupt the Transmit Level 2/3 interface controlled by TFCLK clock. Any FIFOs associated with the TFCLK (TXCP) must be reset using FIFORST after the DLL is reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 192
... When the TFCLK input changes from a logic zero to a logic one, the TFCLKI register bit is set to logic one. The TFCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 193
... When OVERRIDE is set high, the system interface output propagation will not meet the specified timing. This feature provides a back- up strategy for very low frequency PTCLK operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 194
... S/UNI-622-MAX DATASHEET PMC-1980589 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX) 190 ...
Page 195
... Bit 1 R Bit 0 R Writing to this register performs a software reset of the DLL. The software reset will disrupt the Transmit parallel interface controlled by PTCLK clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function Default Unused ...
Page 196
... When the PTCLK input changes from a logic zero to a logic one, the PTCLKI register bit is set to logic one. The PTCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 ...
Page 197
... PSBFE: The PSBF interrupt enable is an interrupt mask for protection switch byte failure alarms. When PSBFE is a logic one, an interrupt is generated when PSBF is declared or removed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 198
... SFBERI: The SFBERI bit is set high when the signal failure threshold crossing alarm is declared or removed. This bit is cleared when the RASE Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...
Page 199
... PSBFI: The PSBFI bit is set high when the protection switching byte failure alarm is declared or removed. This bit is cleared when the RASE Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 PM5356 ...
Page 200
... RASE BIP accumulation logic is disabled, and the RASE logic is reset to the declaration monitoring state. All RASE accumulation period and threshold registers should be set up before SDBERTEN is written. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-Sierra, Inc. ISSUE 5 Function ...