PM7344-RI PMC-Sierra Inc, PM7344-RI Datasheet
PM7344-RI
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... DATA SHEET PMC-950449 SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 TM S/ UNI- MPH S/UNI-MPH DATA SHEET ISSUE 6: JUNE 1998 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE ...
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... June 1998 5 August 8, 1996 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Details of Change Data Sheet Reformatted — No Change in Technical Content. Generated R6 data sheet from PMC-940873, R7. Eng Doc, Issue 6 released PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE ...
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... T1/E1 FRAMING INSERTIONS (TRAN) ..................................... 47 9.10 T1 INBAND LOOPBACK CODE GENERATOR (XIBC) .............. 47 9.11 T1 PULSE DENSITY ENFORCER (XPDE)................................. 47 9.12 T1 BIT ORIENTED CODE GENERATOR (XBOC)...................... 48 9.13 T1 HDLC TRANSMITTER (T1 XFDL) ......................................... 48 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE i ...
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... USING THE DIGITAL JITTER ATTENUATOR .......................... 240 14.2.1 DEFAULT APPLICATION ............................................... 241 14.2.2 DATA BURST APPLICATION ......................................... 241 14.3 JTAG SUPPORT ....................................................................... 242 14.3.1 BOUNDARY SCAN CELLS ............................................ 247 15 ABSOLUTE MAXIMUM RATINGS ....................................................... 250 16 CAPACITANCE .................................................................................... 251 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE ii ...
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... DATA SHEET PMC-950449 17 D.C. CHARACTERISTICS .................................................................. 252 18 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 255 19 S/UNI-MPH I/O TIMING CHARACTERISTICS .................................... 260 20 ORDERING AND THERMAL INFORMATION...................................... 274 21 MECHANICAL INFORMATION............................................................ 275 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE iii ...
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... REGISTERS 012H, 112H, 212H AND 312H: CDRC INTERRUPT STATUS .... 98 REGISTERS 013H, 113H, 213H AND 313H: ALTERNATE LOSS OF SIGNAL STATUS ................................................................................................. 99 REGISTERS 014H, 114H, 214H AND 314H: ALMI CONFIGURATION.......... 100 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE iv ...
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... STATUS INTERRUPT INDICATION .................................................... 123 REGISTERS 026H, 126H, 226H AND 326H: E1-FRMR FRAMING STATUS 124 REGISTERS 027H, 127H, 227H AND 327H: E1-FRMR MAINTENANCE/ALARM STATUS ............................................................................................... 125 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE v ...
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... REGISTERS 042H, 142H, 242H AND 342H: XIBC CONTROL...................... 149 REGISTERS 043H, 143H, 243H AND 343H: XIBC LOOPBACK CODE ........ 151 REGISTERS 044H, 144H, 244H AND 344H: E1-TRAN CONFIGURATION .. 152 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE vi ...
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... REGISTERS 065H, 165H, 265H AND 365H: RXCP UNCORRECTABLE HCS ERROR EVENT COUNT MSB............................................................. 173 REGISTERS 068H, 168H, 268H AND 368H: RXCP CORRECTABLE HCS ERROR EVENT COUNT LSB.............................................................. 174 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE vii ...
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... REGISTERS 077H, 177H, 277H AND 377H: RXCP IDLE/UNASSIGNED CELL MASK: H1 OCTET ............................................................................... 192 REGISTERS 078H, 178H, 278H AND 378H: RXCP IDLE/UNASSIGNED CELL MASK: H2 OCTET ............................................................................... 193 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE viii ...
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... REGISTERS 08AH, 18AH, 28AH AND 38AH: TXCP IDLE/UNASSIGNED CELL PATTERN: H1 OCTET ......................................................................... 210 REGISTERS 08BH, 18BH, 28BH AND 38BH: TXCP IDLE/UNASSIGNED CELL PATTERN: H2 OCTET ..........................................................................211 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE ix ...
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... REGISTERS 08EH, 18EH, 28EH AND 38EH: TXCP IDLE/UNASSIGNED CELL PATTERN: H5 OCTET ......................................................................... 214 REGISTERS 08FH, 18FH, 28FH AND 38FH: TXCP IDLE/UNASSIGNED CELL PAYLOAD............................................................................................. 215 REGISTER 00BH: MASTER TEST ................................................................ 217 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE x ...
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... FIGURE 18- ARBITRARY RATE TRANSMIT INTERFACE ............................ 225 FIGURE 19- ARBITRARY RATE RECEIVE INTERFACE .............................. 225 FIGURE 20- J2 (6.312 MBIT/S) TRANSMIT INTERFACE ............................. 226 FIGURE 21- J2 (6.312 MBIT/S) RECEIVE INTERFACE................................ 227 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE xi ...
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... FIGURE 41- TCLKI INPUT TIMING ............................................................... 262 FIGURE 42- DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM..... 263 FIGURE 43- TRANSMIT DATA LINK INPUT TIMING DIAGRAM................... 265 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE xii 227 ...
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... FIGURE 48- TRANSMIT CELL INTERFACE TIMING DIAGRAM .................. 270 FIGURE 49- RECEIVE CELL INTERFACE TIMING DIAGRAM ..................... 271 FIGURE 50- JTAG PORT INTERFACE TIMING DIAGRAM........................... 272 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE xiii ...
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... TABLE 17 - RECEIVE CELL INTERFACE TIMING (FIGURE 49)................. 270 TABLE 18 - JTAG PORT INTERFACE TIMING (FIGURE 50)....................... 272 TABLE 19 - S/UNI-MPH ORDERING INFORMATION .................................. 274 TABLE 20 - S/UNI-MPH THERMAL INFORMATION .................................... 274 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE xiv ...
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... Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. Low power, +5V, CMOS technology 128 pin rectangular (14mm x 20mm) PQFP package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE TM ) FIFO buffers in both 1 ...
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... Supports polled, interrupt-driven, or DMA servicing of the HDLC interface. Extracts the data link in ESF mode. The T1 transmitter section: Formats data ESF format DS1 signals. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 2 ...
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... CRC multiframe alignment. Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for counting: CRC-4 errors to 1000 per second; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 3 ...
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... Supports HDB3 or AMI line code. Provides dual rail or single rail digital PCM output signals. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 4 ...
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... All four transmit ATM cell processors are serviced via a single 8-bit wide multi-PHY interface. Loopback features: Provides for DS1 or E1 line loopback, payload loopback, or diagnostic loopback. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 5 ...
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... ATM Switches Supporting STS-3/STM-1 Or Other SONET/SDH Ports Carrying Tributary Mapped DS1 or E1 UNI Signals ATM Customer Premise Equipment Supporting Multiple DS1 or E1 UNI Ports PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 6 ...
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... ITU-T Recommendation G.703, - "Physical/Electrical Characteristics of Hierarchical Digital Interfaces", Rev.1, 1991. 13. ITU-T Recommendation G.704, - "Synchronous Frame Structures Used at Primary and Secondary Hierarchical Levels", Rev.1, 1991. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 7 ...
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... Networks: Frame and Multiplexing Structures”, January 1993. 26. ETSI DE/TM-1015 - "Transmission and Multiplexing (TM); Generic Functional Requirements for SDH Transmission Equipment, Part 1: Generic Processes and Performance", Version 1.0, November, 1993. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 8 ...
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... ATM Forum, Level 2, V0.8 - “UTOPIA, An ATM-PHY Interface Specification”, April 1995. 30. PMC-Sierra, Inc., “(SCI-PHY Devices”, Issue 2, July 1994. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE SATURN Compliant Interface For ATM PHY PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 9 ...
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... ATM Cell Bus Generic Microprocessor Bus Example 1 shows the PM7344 S/UNI-MPH used with the PM4314 QDSX to implement a quad T1/E1 UNI where the DS1 or E1 signals are presented on DSX electrical interfaces. In this example, the DSX line interface functions are provided by the QDSX and the DS1 or E1 framing functions are provided by the S/UNI-MPH ...
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... Microprocessor 12.352 MHz Bus Example 2 shows seven PM7344 S/UNI-MPH devices used with a PM8313 D3MX device and a generic DSX-3 LIU device being used to implement a DS3 port where the DS3 carries a multiplex of DS1 (or E1) UNI signals. In this example, each S/UNI-MPH provides four duplex DS1 signals to the D3MX device which, in turn, performs the asynchronous multiplex and demultiplex function required to map these into a DS3 signal ...
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... IMASTER IPOLL IBUS8 Example 3 shows N (where number from PM7344 S/UNI-MPH devices used with UTOPIA Level 2 compliant ingress and egress devices. The S/UNI-MPH supports PHY address polling by sampling the two least significant address bits (RRA[1:0] and TWA[1:0]) and generating the cell available status for the selected PHY entity ...
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... DS-1 port. Thus, the aggregate throughput is less than 6.144 Mbyte/s with 32 DS-1 ports; therefore, the clock oscillator frequency can be as low as 6.5 MHz. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 13 ...
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... PAYLOAD LOOPBACK T1/E1 Rx ATM Cell Framer Bit Inband Performance Alarms Oriented Code Monitor Integrator Code Detector Receiver PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE TSOC JTAG Test TDAT[7:0] Access Port TXPRTY TCA[4:1] TCAMPH/TWRENB[4] TWA[1]/TWRENB[3] Tx ATM TWA[0]/TWRENB[2] 4 Cell TWRMPHB /TWRENB[1] FIFO TFCLK ...
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... PMC-950449 6 DESCRIPTION The PM7344 SATURN Quad T1/E1 Multi-PHY User Network Interface (S/UNI- MPH monolithic integrated circuit that implements the T1/E1 processing and ATM mapping functions for four 1.544 Mbit/s or 2.048 Mbit/s ATM User Network Interfaces. It can also be used in conjunction with external framing devices, to implement ATM user network interfaces for other bit rates ...
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... The S/UNI-MPH also provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 A multi-PHY interface allows the four transmit FIFOs PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 16 ...
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... TXPRTY TFCLK PIN 38 PIN 39 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH Top View PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE PIN 103 PIN 102 TDI TDO RDLSIG[4]/RDLINT[4] RDLSIG[3]/RDLINT[3] RDLSIG[2]/RDLINT[2] RDLSIG[1]/RDLINT[1] ...
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... RDP and RDN inputs. 33 Receive Digital Data (RDD). When the 7 S/UNI-MPH is configured to receive single-rail 4 data or when the T1/E1 framers are bypassed, 1 this signal contains the receive data stream. RDD may be enabled to be sampled on the rising or falling edge of RCLKI. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 18 ...
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... NRZ sample the RDD and RLCV/ROH inputs on its rising or falling edge when the input format is enabled for single-rail, or when the T1/E1 framers are bypassed. RCLKI must operate at frequencies less than or equal to 25 MHz. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 19 ...
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... RDLSIG is updated on the falling edge of RDLCLK. Receive Data Link Interrupt (RDLINT). The RDLINT signal is available on this pin when RFDL is enabled. RDLINT goes high when an event occurs which changes the status of the HDLC receiver. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 20 ...
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... TDLINT signal is output on this pin when XFDL is enabled. TDLINT goes high when the last data byte written to the XFDL has been set up for transmission and processor intervention is required to either write control information to end the message provide more data. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 21 ...
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... TCLKO. Transmit Digital Data (TDD). This signal is available on the pin when the S/UNI-MPH is configured to transmit single-rail data, or when the T1/E1 framers are bypassed. The TDD signal may be enabled to be updated on the rising or falling edge of TCLKO. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 22 ...
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... TCLKI input and utilize XCLK instead. The default requirement is for TCLKI 1.544 MHz clock for 2.048 MHz clock for E1. For arbitrary bit rates, TCLKI must be less than or equal to 25 MHz. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 23 ...
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... S/UNI-MPH. This clock may be tied low if the T1/E1 framers are bypassed. The default requirement is for XCLK 37.056 MHz clock for 49.152 MHz clock for E1. Vector Clock (VCLK). The VCLK signal is used during S/UNI-MPH production test to verify internal functionality. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 24 ...
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... TWRENB[4:1] and RRDENB[4:1] are active. 74 Receive FIFO Read Clock (RFCLK). This signal is used to read ATM cells from the receive FIFOs. RFCLK must cycle MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflow. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 25 ...
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... RDAT[7:0] and RSOC are tristated. RRDENB[1] must operate in conjunction with RFCLK to access the FIFOs at a high enough instantaneous rate as to avoid FIFO overflows. The ATM layer device may deassert RRDENB[1] at anytime it is unable to accept another byte. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 26 ...
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... RDAT[7:0] and RSOC are tristated. RRDENB[2] must operate in conjunction with RFCLK to access the FIFOs at a high enough instantaneous rate as to avoid FIFO overflows. The ATM layer device may deassert RRDENB[2] at anytime it is unable to accept another byte. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 27 ...
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... RDAT[7:0] and RSOC are tristated. RRDENB[3] must operate in conjunction with RFCLK to access the FIFOs at a high enough instantaneous rate as to avoid FIFO overflows. The ATM layer device may deassert RRDENB[3] at anytime it is unable to accept another byte. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 28 ...
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... Receive Cell Data Bus (RDAT[7:0]). This bus 90 carries the ATM cell octets that are read from 91 the selected receive FIFO. RDAT[7: updated on the rising edge of RFCLK and is 93 tristated when RRDENB[n]/RRDMPHB is high PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 29 ...
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... Transmit Cell Data Bus (TDAT[7:0]). This bus 67 carries the ATM cell octets that are written to the 68 selected transmit FIFO. TDAT[7:0] is sampled 69 on the rising edge of TFCLK and is considered 70 valid only when TWRENB[n]/TWRMPHB is 71 simultaneously asserted PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 30 ...
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... TFCLK, no write is performed. TWRENB[1] must operate in conjunction with TFCLK to access the FIFOs at a high enough instantaneous rate as to avoid FIFO overflows. The ATM layer device may deassert TWRENB[1] at anytime it is unable to provide another byte. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 31 ...
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... TFCLK, no write is performed. TWRENB[2] must operate in conjunction with TFCLK to access the FIFOs at a high enough instantaneous rate as to avoid FIFO overflows. The ATM layer device may deassert TWRENB[2] at anytime it is unable to provide another byte. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 32 ...
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... TFCLK, no write is performed. TWRENB[3] must operate in conjunction with TFCLK to access the FIFOs at a high enough instantaneous rate as to avoid FIFO overflows. The ATM layer device may deassert TWRENB[3] at anytime it is unable to provide another byte. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 33 ...
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... TFCLK, no write is performed. TWRENB[4] must operate in conjunction with TFCLK to access the FIFOs at a high enough instantaneous rate as to avoid FIFO overflows. The ATM layer device may deassert TWRENB[4] at anytime it is unable to provide another byte. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 34 ...
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... Active low Chip Select (CSB). This signal must be low to enable S/UNI-MPH register accesses. If CSB is not used, (RDB and WRB determine register reads and writes) then it should be tied to an inverted version of RSTB. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 35 ...
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... Active low Reset (RSTB). This signal is set low to asynchronously reset the S/UNI-MPH. RSTB is a Schmitt-trigger input with an integral pull-up resistor. 117 Address Bus (A[10:0]). This bus selects specific 118 registers during S/UNI-MPH register accesses. 119 120 121 122 123 124 125 126 127 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 36 ...
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... common with VDD_DC[3:0] 116 DC Power (VDD_DC[3:0]). These pins should 86 be connected to a well decoupled + common with VDD_AC[2:0 Pad Ring Ground (VSS_AC[2:0]). These pins 51 should be connected to GND in common with 19 VSS_DC[3:0]. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 37 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Pin Function No. 115 DC Ground (VSS_DC[3:0]). These pins should 85 be connected to GND in common with 53 VSS_AC[2:0]. 21 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 38 ...
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... TDLCLK frequency of 4 kHz (ESF FDL at the full 4 kHz rate), the time-out is 1.0 ms; 2) for a TDLCLK frequency of 2 kHz (half the ESF FDL), the time-out is 2.0 ms; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 39 ...
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... Intervals peak-to-peak), at the expense of the low frequency PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE with 14 zero restriction). The CDRC PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 40 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 IN SPEC. REGION CDRC MAX. TOLERANCE (ALGSEL=0) 0.70 SINEWAVE JITTER FREQUENCY, kHz - LOG SCALE 15 -1 sequence. The E1 jitter tolerance PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE CDRC MAX. TOLERANCE (ALGSEL=1) AT&T SPEC. BELLCORE SPEC. 100 10 41 ...
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... DATA SHEET PMC-950449 Figure Jitter Tolerance Specification (ALGSEL = 1) Measurement Limit 10 1.0 G823 Jitter Tolerance Specification 0.1 0.01 . PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Jitter Frequency (Hz) PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE Measured CDRC Jitter Tolerance (ALGSEL = 1) 42 ...
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... An interrupt is generated to signal a 16 consecutive zero event or a change of state on the pulse density violation indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 G823 Jitter Tolerance Specification Jitter Frequence (Hz) PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE Measured CDRC Jitter Tolerance (ALGSEL = 0) 43 ...
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... CFA is declared when an out-of-frame condition has been present for 2.55 sec (± 40 ms); the red CFA is removed when the out-of-frame PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 44 ...
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... For an E1 data stream, the PMON accumulates CRC-4 error events, frame synchronization bit error events, line code violation events, and far end block PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE -3 bit ...
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... Received data is placed into a 4-level FIFO buffer. The Status Register contains bits which indicate overrun, end of message, flag detected, and buffered data available. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 46 ...
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... T1 Pulse Density Enforcer (XPDE) The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is enabled by a register bit within the XPDE. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 47 ...
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... Register. After the last data frame byte is transmitted, the CRC word (if CRC insertion has been enabled flag (if CRC insertion has not been enabled) is transmitted. The XFDL then returns to the transmission of flag characters. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 48 ...
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... XCLK input according to the phase difference between the generated TCLKO and the input data clock to DJAT (TCLKI or RCLKO). Phase variations in the input clock with a jitter frequency above 8.8 Hz (for the E1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 49 ...
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... Hz UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK divided by 24 and that of the input data clock. These tolerances are shown in Figure 9 and Figure 10 below: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 50 ...
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... PMC-950449 Figure Jitter Tolerance 100 28 10 Jitter Amplitude, UIpp 1.0 0.1 0.01 1 4.9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 10 100 0.3k 1k Jitter Frequency, Hz PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE DJAT minimum tolerance acceptable unacceptable 10k 100k 51 29 0.2 ...
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... PLL reference clock and XCLK/24 are shown in Figure 11 and Figure 12. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 ITU G.823 unacceptable Region 100 Jitter Frequency, Hz PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 35 DJAT minimum tolerance acceptable 0.2 10k 100k ...
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... Hz (for E1 interfaces more than 0.1 dB greater than the input jitter, excluding the 0.042 UI residual jitter. Jitter frequencies above 6.6/8.8 Hz are PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 200 250 0 32 200 49 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 300 354 Hz 100 ± ppm 42 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 62411 max DJAT response 10 100 Jitter Frequency, Hz G.737, G738, G.739, G.742 max DJAT response 10 100 1k 40 Jitter Frequency, Hz PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 43802 max 1k 10k -19.5 10k 54 ...
Page 71
... In this state synchronization is not relinquished until ALPHA consecutive incorrect HCS patterns are found. In such an event a transition is made back to the HUNT state. The state diagram of the cell delineation process is shown in Figure 15. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 55 ...
Page 72
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 correct HCS (bit by bit) Incorrect HCS (cell by cell) SYNC The cell header is not descrambled added (modulo 2) to the PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE PRESYNC DELTA consecutive correct HCS's (cell by cell ...
Page 73
... HCS. The mth cell is not discarded (see Figure 16). Note that the dropping of cells due to HCS errors only occurs while the cell delineation state machine is in the SYNC state (see Figure 15). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 57 ...
Page 74
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 ATM DELINEATION SYNC STATE HCS Multi-bit Error Detected (Cell discarded) Correction HCS Single-bit Error Detected (Error corrected & cell accepted) Detection Consecutive Cells (M'th Cell Accepted) PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE ALPHA consecutive incorrect HCS's (To HUNT state) Cell Discarded 58 ...
Page 75
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE FIFO is provided. This synchronous The header portion of the cells is not added (modulo 2) to the calculated HCS octet as PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE The coset 59 ...
Page 76
... The cell available status for each of the transmit and receive FIFOs is directly available on RCA[4:1] and TCA[4:1]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE FIFO is provided. This synchronous PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 60 ...
Page 77
... DATA SHEET PMC-950449 9.21 Microprocessor Interface (MPIF) The Microprocessor Interface allows the S/UNI-MPH to be configured, controlled and monitored using internal registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 61 ...
Page 78
... Update Source Selection/Interrupt ID Clock Activity Monitor 20BH 30BH Reserved 20CH 30CH Reserved 20DH 30DH Reserved 20EH 30EH Reserved 20FH 30FH Reserved 210H 310H CDRC Configuration 211H 311H CDRC Interrupt Enable 212H 312H CDRC Interrupt Status PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 62 ...
Page 79
... E1-FRMR Maintenance/Alarm Status Interrupt Enable 224H 324H E1-FRMR Framing Status Interrupt Indication 225H 325H E1-FRMR Maintenance/Alarm Status Interrupt Indication 226H 326H E1-FRMR Framing Status 227H 327H E1-FRMR Maintenance/Alarm Status 228H 328H E1-FRMR International/National Bits 229H 329H PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 63 ...
Page 80
... IBCD Activate Code 23FH 33FH IBCD Deactivate Code 240H 340H T1-TRAN Configuration 241H 341FH T1-TRAN Alarm Transmit 242H 342H XIBC Control 243H 343H XIBC Loopback Code 244H 344H E1-TRAN Configuration 245H 345H E1-TRAN Transmit Alarm/Diagnostic Control PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 64 ...
Page 81
... RXCP Uncorrectable HCS Error Count LSB 265H 365H RXCP Uncorrectable HCS Error Count MSB 266H 366H Reserved 267H 367H Reserved 268H 368H RXCP Correctable HCS Error Count LSB 269H 369H RXCP Correctable HCS Error Count MSB PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 65 ...
Page 82
... RXCP Idle/Unassigned Cell Mask: H3 octet 27AH 37AH RXCP Idle/Unassigned Cell Mask: H4 octet 27BH 37BH RXCP User-Programmable Cell Pattern: H1 octet 27CH 37CH RXCP User-Programmable Cell Pattern: H2 octet 27DH 37DH RXCP User-Programmable Cell Pattern: H3 octet PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 66 ...
Page 83
... TXCP Idle/Unassigned Cell Pattern: H3 octet 28DH 38DH TXCP Idle/Unassigned Cell Pattern: H4 octet 28EH 38EH TXCP Idle/Unassigned Cell Pattern: H5 octet 28FH 38FH TXCP Idle/Unassigned Cell Payload 290H - 390H - Reserved 2FFH 3FFH Reserved for Test PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 67 ...
Page 84
... Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. Writing into read-only normal mode register bit locations does not affect S/UNI-MPH operation unless otherwise noted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 68 ...
Page 85
... RDLEOM output so that RDLINT is forced to logic 0 when RDLEOM is logic 1. When RXDMAGAT is set to logic 0, the RDLINT[x] and RDLEOM[x] outputs operate independently. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default WORDERR 0 CNTNFAS 0 RXDMAGAT 0 Unused X Unused X Unused X MODE[1] 0 MODE[0] 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 69 ...
Page 86
... Mbit/s T1 ATM UNI 1 2.048 Mbit/s E1 ATM UNI 0 6.312 Mbit/s J2 ATM UNI This configuration requires an external J2 framer. 1 Arbitrary Format UNI ( 25 Mbit/s) This configuration relies on an external device to identify the overhead bits in the arbitrary transmission format. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 70 ...
Page 87
... When REDEN is logic 1, declaration of the red CFA causes a yellow alarm (T1) or remote alarm indication (E1 transmitted for the duration of the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default LCDEN 1 AISEN 1 REDEN 1 OOFEN 1 LOSEN 1 TAISEN 0 MODE[1] 0 MODE[0] 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 71 ...
Page 88
... S/UNI-MPH. The four interfaces must be configured identically by writing these bits in each of the four Transmit Configuration registers. MODE[1] MODE[0] 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Configuration 0 1.544 Mbit/s T1 ATM UNI PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 72 ...
Page 89
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Configuration 1 2.048 Mbit/s E1 ATM UNI 0 6.312 Mbit/s J2 ATM UNI This configuration requires an external J2 framer. 1 Arbitrary Format UNI ( 25 Mbit/s) This configuration relies on an external device to insert the overhead bits in the arbitrary transmission format. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 73 ...
Page 90
... T1-ESF the extracted timeslot 0 National bits or timeslot 16 for E1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RXDMASIG 0 Unused X TXDMASIG 0 Unused X RDLINTE 0 RDLEOME 0 TDLINTE 0 TDLUDRE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 74 ...
Page 91
... TXDMASIG is logic 1) also causes an interrupt to be generated on the INTB output. When TDLUDRE is set to logic 0, an underrun event in the XFDL does not cause an interrupt on INTB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 75 ...
Page 92
... RDN/RLCV/ROH[x] input. When RDNINV is set to logic 0, the interface passes the RDN/RLCV/ROH[x] signal unaltered. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X BPV 0 RDNINV 0 RDPINV 0 RUNI 0 RFALL 0 Unused X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 76 ...
Page 93
... RDP/RDD[x] and RDN/RLCV/ROH[x] inputs on the falling RCLKI[x] edge. When RFALL is set to logic 0, the interface is enabled to sample the inputs on the rising RCLKI[x] edge. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 77 ...
Page 94
... When TDPINV is set to logic 1, the TDP/TDD[x] output is inverted. When TDPINV is set to logic 0, the TDP/TDD[x] output is not PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default TOCTA 0 TOHINV 0 TDNINV 0 TDPINV 0 TUNI 0 TFALL 0 TRISE 0 TRZ 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 78 ...
Page 95
... NRZ waveforms with duration equal to the TCLKO[x] period, updated on the selected edge of TCLKO[x]. The TRZ bit can only be used when TUNI is set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 79 ...
Page 96
... RXSA8EN is logic 1, the RDLSIG value is extracted from bit 8 of Time Slot 0 of non-frame alignment signal frames. The other enable bits operate in PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X SACE 0 SACI 0 RXSA4EN 1 RXSA5EN 0 RXSA6EN 0 RXSA7EN 0 RXSA8EN 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 80 ...
Page 97
... HDLC receiver and the RDLINT/RDLSIG and RDLEOM/RDLCLK pins operate as a data link interrupt (RDLINT) and a end-of-message (RDLEOM) indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 81 ...
Page 98
... E1 TRAN block International/National Control register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X TXSA4EN 1 TXSA5EN 0 TXSA6EN 0 TXSA7EN 0 TXSA8EN 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 82 ...
Page 99
... In this mode the jitter attenuation is disabled and the input clock must PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default FIFOBYP 0 XCLKSEL 0 Unused 0 OCLKSEL 0 TREF[1] 0 TREF[0] 0 Unused X Unused X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 83 ...
Page 100
... Receive clock output (RCLKO) as selected by the RCLK[1:0] bits in the Source Selection/Interrupt ID register. 0 Receive clock from the RCLKI[x] input or recovered from the RDP[x]/RDN[x] inputs. 1 XCLK input divided depending on the setting of the XCLKSEL bit. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 84 ...
Page 101
... FIFO input FIFO data clock 1 00 DJAT PLL TREF[1:0] 24x reference clock for jitter attenuation 11 ÷ 8 XCLKSEL PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE FIFO output TCLKO[x] data clock OCLKSEL or FIFOBP or MODE[1] (register X01H). 0 "Jitter Attenuated" Clock "High-speed" clock for CDRC & T1-FRMR 85 ...
Page 102
... Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default DJAT 0 IBCD 0 FRMR 0 PDVD 0 SAC 0 RFDL 0 RBOC 0 ALMI 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 86 ...
Page 103
... Reading these registers does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X PMON 0 TXPRTY 0 XPDE 0 RXCP 0 TXCP 0 XFDL 0 CDRC/ALTLOS 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 87 ...
Page 104
... TRAN prior to transmission. When PAYLB is set to logic 0, the payload loopback mode is disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default TEVEN 0 REVEN 0 PAYLB 0 LINELB 0 Unused X DIALB 0 TPERRE 0 TPERRI 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 88 ...
Page 105
... When the TPERRI bit is logic 1, it indicates that a parity error was detected on the incoming transmit FIFO interface. When TPERRI is logic 0, no parity error was detected. Reading this register clears this bit to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 89 ...
Page 106
... While the DBCTRL bit is set, holding the CSB pin PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X A_TM[9] X A_TM[8] X PMCTST X DBCTRL 0 IOTST 0 HIZDATA 0 HIZIO 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 90 ...
Page 107
... The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 91 ...
Page 108
... TIP to be cleared. ID[2:0]: The ID[2:0] bits allows software to identify the version level of the S/UNI- MPH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RESET 0 TYPE[2] 1 TYPE[1] 0 TYPE[0] 1 TIP 0 ID[2] 0 ID[1] 0 ID[0] 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 92 ...
Page 109
... The RCLKI[1] input or the clock recovered from RDP[1] and RDN[1]. 1 The RCLKI[2] input or the clock recovered from RDP[2] and RDN[2]. 0 The RCLKI[3] input or the clock recovered from RDP[3] and RDN[3]. 1 The RCLKI[4] input or the clock recovered from RDP[4] and RDN[4]. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 93 ...
Page 110
... RFCLKA is set high on a rising edge of RFCLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default XCLKIA 0 RCLKI1A 0 RCLKI2A 0 RCLKI3A 0 RCLKI4A 0 TCLKIA 0 TFCLKA 0 RFCLKA 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 94 ...
Page 111
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default AMI 0 LOS[1] 0 LOS[0] 0 DCR 0 SYNC 0 ALGSEL 0 O162 0 Reserved 0 Threshold (bit periods (E1 format selected) 15 (T1 format or AMI line code selected 175 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 95 ...
Page 112
... If O162 is a logic 1, a line code violation is indicated by a LCV output pulse if a bipolar violation is of the same polarity as the last bipolar violation, as per Recommendation O.162. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 96 ...
Page 113
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default LCVE 0 LOSE 0 LCSDE 0 EXZE 0 Unused X Unused X Unused X Unused X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 97 ...
Page 114
... The current state of the LOS alarm can be determined by reading bit 0 of this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default LCVI 0 LOSI 0 LCSDI 0 EXZI 0 Unused X Unused X Unused X LOS 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 98 ...
Page 115
... E1 format specify that 255 bit periods are observed during which no sequence of four zeros is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default ALTLOSE 0 ALTLOSI X Unused X Unused X Unused X Unused X Unused X ALTLOS X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 99 ...
Page 116
... Reserved 0 0 Select ESF framing format & 4 kbit FDL Data Rate 0 1 Select ESF framing format & 2 kbit FDL Data Rate 1 0 Select ESF framing format & 2 kbit FDL Data Rate 1 1 Reserved PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 100 ...
Page 117
... AIS CFA's can be enabled to generate an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X FASTD 0 Reserved 0 YELE 0 REDE 0 AISE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 101 ...
Page 118
... The status bit positions (bits 5 through 3) are cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X YELI 0 REDI 0 AISI 0 YEL 0 RED 0 AIS 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 102 ...
Page 119
... ESF framing format with a 2 kHz data link. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X REDD X YELD X AISD X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 103 ...
Page 120
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 104 ...
Page 121
... FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI 0 UNDI 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 105 ...
Page 122
... Writing to this register will reset the PLL and, if the SYNC bit in the DJAT Configuration register is high, will also reset the FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 106 ...
Page 123
... Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 107 ...
Page 124
... FIFO error events are disabled from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Reserved 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 108 ...
Page 125
... When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 109 ...
Page 126
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default M2O[1] 0 M2O[0] 0 ESFFA 0 ESF 0 FMS1 0 FMS0 0 Unused X Unused X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 110 ...
Page 127
... Select ESF framing format & 4 kbit FDL Data Rate 1 Select ESF framing format & 2 kbit FDL Data Rate using frames 3, 7, 11, 15, 19, and 23. 0 Select ESF framing format & 2 kbit FDL Data Rate using frames 13, 17, and 21. 1 Reserved PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 111 ...
Page 128
... CRC-6 errors for ESF formatted data. When BEEE is set to logic 1, the detection of a bit error event is allowed to generate an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Reserved 0 COFAE 0 FERE 0 BEEE 0 SFEE 0 MFPE 0 INFRE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 112 ...
Page 129
... When INFRE is set to logic 1, the assertion or deassertion of the "inframe" state is allowed to generate an interrupt. When INFRE is set to logic 0, a change in the "inframe" state is disabled from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 113 ...
Page 130
... The bit position MFP and INFR indicate the current state of the mimic detection and of the frame alignment circuitry. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default COFAI 0 FERI 0 BEEI 0 SFEI 0 MFPI 0 INFRI 0 MFP 0 INFR 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 114 ...
Page 131
... The interrupt and the status bit positions (COFAI, FERI, BEEI, SFEI, MFPI, and INFRI) are cleared to logic 0 when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 115 ...
Page 132
... The CHKSEQ bit enables the use of the check sequence to verify the correct frame alignment in the presence of random imitative frame alignment signals. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default CRCEN 0 Reserved 0 AFAA 0 CHKSEQ 0 Reserved 0 REFR 0 REFCRCE 0 REFRDIS 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 116 ...
Page 133
... A logic 0 allows reframing to occur based on the various error criteria (FER, excessive CRC errors, etc). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 117 ...
Page 134
... NFAS frames; a logic 1 in the RADEB bit position enables the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default FASC 0 0 Reserved 0 Reserved 0 RADEB 0 Reserved 0 CMFACT X EXCRCE X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 118 ...
Page 135
... REFCRCE bit of the Frame Alignment Options register. The EXCRCE bit is reset to logic 0 after the register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 119 ...
Page 136
... A logic 1 in the CMFERE bit enables the generation of an interrupt when an error has been detected in the CRC multiframe alignment signal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X OOFE 0 Reserved 0 OOCMFE 0 COFAE 0 FERE 0 Reserved 0 CMFERE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 120 ...
Page 137
... When the CRCEE bit is a logic one, an interrupt is generated when calculated CRC differs from the received CRC remainder. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RRAE 0 Reserved 0 AISDE 0 Reserved 0 REDE 0 AISE 0 FEBEE 0 CRCEE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 121 ...
Page 138
... These bits are cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X OOFI X Unused X OOCMFI X COFAI X FERI X Unused X CMFERI X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 122 ...
Page 139
... The CRCEI bit becomes a logic one when a calculated CRC differs from the received CRC remainder. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RRAI X Unused X AISDI X Unused X REDI X AISI X FEBEI X CRCEI X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 123 ...
Page 140
... The OOCMF bit is a logic 0 when CRC multiframe has been acquired. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X OOF X Unused X OOCMF X Unused X Unused X Unused X Unused X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 124 ...
Page 141
... The AIS bit returns to a logic zero when the AIS condition has been absent for 104 ms. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RRA X Unused X AISD X Unused X RED X AIS X Unused X Unused X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 125 ...
Page 142
... The Si0, RAWRA and Sn[4:8] bits map to the timeslot 0 NFAS as follows Si[0] 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Si[1] X Si[0] X RAWRA X Sn[4] X Sn[5] X Sn[6] X Sn[7] X Sn[8] X Bit Position RAWRA Sn[4] Sn[5] PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE Sn[6] Sn[7] Sn[8] 126 ...
Page 143
... These registers contain the least significant byte of the 10-bit CRC error counter value, updated every second. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default CRCE7 X CRCE6 X CRCE5 X CRCE4 X CRCE3 X CRCE2 X CRCE1 X CRCE0 X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 127 ...
Page 144
... PMON relies on externally initiated transfers which may not be one second apart. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default OVR 0 NEWDATA 0 Unused X Unused X Unused X Unused X CRCE9 X CRCE8 X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 128 ...
Page 145
... BOC is detected. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X IDLE 0 AVC 0 BOCE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 129 ...
Page 146
... BOCI bit position indicates that no BOC has been detected. BOCI is cleared to logic 0 when the register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default IDLEI 0 BOCI 0 BOC[5] 1 BOC[4] 1 BOC[3] 1 BOC[2] 1 BOC[1] 1 BOC[0] 1 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 130 ...
Page 147
... Datalink Options register, the interrupt generated on the TDLINT[x] output is also generated on the microprocessor INTB pin. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X EOM 0 INTE 0 ABT 0 CRC PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 131 ...
Page 148
... FCS word is appended to the last data byte transmitted and a continuous stream of flags is generated. The EOM bit is automatically cleared before transmission of the next data packet begins. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 132 ...
Page 149
... The UDR bit can only be cleared by writing a logic 0 to the UDR bit position in this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X INT 1 UDR 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 133 ...
Page 150
... Transmit Data register must be written with the new data within 4 data bit periods to prevent the occurrence of an underrun. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default TD7 X TD6 X TD5 X TD4 X TD3 X TD2 X TD1 X TD0 X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 134 ...
Page 151
... If the Configuration register is read after this time, the TR bit value returned will be zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 135 ...
Page 152
... Default Unused X Unused X Unused X Unused X Unused X INTC1 0 INTC0 0 INT 0 Description 0 Disable interrupts (All sources) 1 Enable interrupt when FIFO receives data 0 Enable interrupt when FIFO has 2 bytes of data 1 Enable interrupt when FIFO has 3 bytes of data PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 136 ...
Page 153
... DATA SHEET PMC-950449 The contents of the RFDL Interrupt Control/Status register should only be changed when the RFDL is disabled to prevent any erroneous interrupt generation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 137 ...
Page 154
... The last byte in the HDLC frame (EOM) is being read from the RFDL Receive Data Register, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default FE 1 OVR 0 FLG 0 EOM 0 CRC 0 NVB2 1 NVB1 1 NVB0 1 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 138 ...
Page 155
... Status register read immediately following the Received Data register read which caused the underrun condition. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 139 ...
Page 156
... The underrun condition will be signaled in the next Status read by returning all zeros. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RD7 X RD6 X RD5 X RD4 X RD3 X RD2 X RD1 X RD0 X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 140 ...
Page 157
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Reserved 0 Unused X Unused X Unused X DSEL1 0 DSEL0 0 ASEL1 0 ASEL0 0 ACTIVATE Code ASEL1 ASEL0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE CODE LENGTH 5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits 141 ...
Page 158
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default LBACP 0 LBDCP 0 LBAE 0 LBDE 0 LBAI 0 LBDI 0 LBA 0 LBD 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 142 ...
Page 159
... A logic 1 in these bit positions indicate the presence of that code has been detected; a logic 0 in these bit positions indicate the absence of that code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 143 ...
Page 160
... Note that bit ACT7 corresponds to the first code bit received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default ACT7 0 ACT6 0 ACT5 0 ACT4 0 ACT3 0 ACT2 0 ACT1 0 ACT0 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 144 ...
Page 161
... Note that bit DACT7 corresponds to the first code bit received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default DACT7 0 DACT6 0 DACT5 0 DACT4 0 DACT3 0 DACT2 0 DACT1 0 DACT0 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 145 ...
Page 162
... DDS Zero Code Suppression (All zero data byte replaced with "10011000") Bell Zero Code Suppression (Bit all zero channel byte is replaced by a one.) PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 146 ...
Page 163
... Select ESF framing format & 4 kbit FDL Data Rate 1 Select ESF framing format & 2 kbit FDL Data Rate (frames 3, 7, 11, 15, 19, 23) 0 Select ESF framing format & 2 kbit FDL Data Rate (frames 13, 17, 21). 1 Reserved PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 147 ...
Page 164
... When XAIS is set to logic 0, the TDP/TDN[x] outputs operate normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X XYEL 0 XAIS 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 148 ...
Page 165
... The bit positions CL[1:0] (bits 1 & this register indicate the length of the inband loopback code sequence, as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X CL1 0 CL0 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 149 ...
Page 166
... Codes bits in length may be accommodated by treating them as half of a double-sized code (i.e. a 3-bit code would use the 6-bit code length setting). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Code Length PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 150 ...
Page 167
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default IBC7 X IBC6 X IBC5 X IBC4 X IBC3 X IBC2 X IBC1 X IBC0 X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 151 ...
Page 168
... FEBEDIS 0 Reserved 0 Reserved 0 MODE TS16 insertion disabled. TS16 is set to all ones. TS16 insertion enabled. TS16 data is taken directly from the TDLSIG input or from the HDLC transmitter. Reserved. TS16 insertion disabled. TS16 is set to all ones. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 152 ...
Page 169
... Register is used for the International bit in the frame alignment signal (FAS) frames and the Si[0] bit is used for the International bit in the non-frame alignment signal (NFAS) frames. Bits Sn[4:8] in the register are used for the National bits in NFAS frames. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 153 ...
Page 170
... CRC multiframe alignment signal is used for the International bit in the NFAS frames, with the Si[1:0] bits in the International/National Control Register used for the spare bits. Bit positions Sn[4:0] in the register are used for the National bits in NFAS frames. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 154 ...
Page 171
... The AIS bit enables the TRAN to generate an unframed all-ones AIS alarm. When AIS is set to logic 1, the TDP/TDN[x] outputs are forced to pulse PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Reserved 0 FPATINV 0 SPLRINV 0 Reserved 0 REMAIS 0 Reserved 0 Reserved 0 AIS 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 155 ...
Page 172
... DATA SHEET PMC-950449 alternately, creating an all-ones signal. When AIS is set to logic 0, the TDP/TDN[x] outputs operate normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 156 ...
Page 173
... Si[1] and Si[0] bit positions are inserted into the spare bit locations of frame 13 and frame 15, respectively, of the CRC multiframe. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Si[1] 1 Si[0] 1 Unused X Sn[4] 1 Sn[5] 1 Sn[6] 1 Sn[7] 1 Sn[8] 1 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 157 ...
Page 174
... A logic 0 indicates that no overrun has occurred. The OVR bit is cleared by reading this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X INTE 0 INT 0 OVR 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 158 ...
Page 175
... RXCP and TXCP blocks at the same time. The transfer in progress (TIP) bit in register 00CH is polled to determine when the transfer is complete. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 159 ...
Page 176
... Fe bit errors. When E1 format is enabled, the counter accumulates frame alignment signal (FAS) bit errors. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X FER[6] X FER[5] X FER[4] X FER[3] X FER[2] X FER[1] X FER[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 160 ...
Page 177
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default FEBE[7] X FEBE[6] X FEBE[5] X FEBE[4] X FEBE[3] X FEBE[2] X FEBE[1] X FEBE[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 161 ...
Page 178
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X FEBE[9] X FEBE[8] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 162 ...
Page 179
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default CRCE[7] X CRCE[6] X CRCE[5] X CRCE[4] X CRCE[3] X CRCE[2] X CRCE[1] X CRCE[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 163 ...
Page 180
... CRC-6 errors. When E1-CRC multiframe format is enabled, the counter accumulates CRC-4 errors. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X Unused X Unused X CRCE[9] X CRCE[8] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 164 ...
Page 181
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default LCV[7] X LCV[6] X LCV[5] X LCV[4] X LCV[3] X LCV[2] X LCV[1] X LCV[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 165 ...
Page 182
... The counting of Excessive Zeros can be disabled by the BPV bit of the Receive Interface Configuration register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X LCV[12] X LCV[11] X LCV[10] X LCV[9] X LCV[8] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 166 ...
Page 183
... When PDV is a logic 1, a violation of the pulse density rule has been PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X PDV 0 Z16DI 0 PDVI 0 Z16DE 0 PDVE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 167 ...
Page 184
... At its minimum, PDV may be asserted for only 1 bit time. Therefore, reading this bit may not return a logic 1 even though a pulse density violation has occurred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 168 ...
Page 185
... HDLC packets currently being transmitted. When the register is written with 111111, the XBOC is disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X BC[5] 1 BC[4] 1 BC[3] 1 BC[2] 1 BC[1] 1 BC[0] 1 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 169 ...
Page 186
... The STUFI bit is reset to logic 0 once this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default STUFE 0 STUFF 0 STUFI 0 PDV 0 Z16DI 0 PDVI 0 Z16DE 0 PDVE 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 170 ...
Page 187
... STUFE is logic 0). When PDVE is set to logic 0, interrupt generation by pulse density violations is disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 171 ...
Page 188
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default UHCSE[7] X UHCSE[6] X UHCSE[5] X UHCSE[4] X UHCSE[3] X UHCSE[2] X UHCSE[1] X UHCSE[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 172 ...
Page 189
... UHCSE counter will lose 1 occurance of an UHCSE (eg. UHCSE count will be 6 instead transition to the HUNT state). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default Unused X Unused X Unused X Unused X UHCSE[11] X UHCSE[10] X UHCSE[9] X UHCSE[8] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 173 ...
Page 190
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default CHCSE[7] X CHCSE[6] X CHCSE[5] X CHCSE[4] X CHCSE[3] X CHCSE[2] X CHCSE[1] X CHCSE[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 174 ...
Page 191
... X6FH (where value from 0 to 3). CHCS errors are not accumulated when the RXCP has declared an out of cell delineation defect state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Unused Unused Unused Unused CHCSE[11] CHCSE[10] CHCSE[9] CHCSE[8] PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 175 ...
Page 192
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default UICELL[7] X UICELL[6] X UICELL[5] X UICELL[4] X UICELL[3] X UICELL[2] X UICELL[1] X UICELL[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 176 ...
Page 193
... Idle/Unassigned Cells are not accumulated when the RXCP has declared an out of cell delineation defect state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default UICELL[15] X UICELL[14] X UICELL[13] X UICELL[12] X UICELL[11] X UICELL[10] X UICELL[9] X UICELL[8] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 177 ...
Page 194
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RCELL[7] X RCELL[6] X RCELL[5] X RCELL[4] X RCELL[3] X RCELL[2] X RCELL[1] X RCELL[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 178 ...
Page 195
... Cells are not passed through the RXCP when an out of cell delineation defect state is declared. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default RCELL[15] X RCELL[14] X RCELL[13] X RCELL[12] X RCELL[11] X RCELL[10] X RCELL[9] X RCELL[8] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 179 ...
Page 196
... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default TCELL[7] X TCELL[6] X TCELL[5] X TCELL[4] X TCELL[3] X TCELL[2] X TCELL[1] X TCELL[0] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 180 ...
Page 197
... X60H to X6FH (where value from 0 to 3). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default TCELL[15] X TCELL[14] X TCELL[13] X TCELL[12] X TCELL[11] X TCELL[10] X TCELL[9] X TCELL[8] X PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 181 ...
Page 198
... BLOCK, only idle/unassigned cells or user-programmed cells corresponding to the pattern specified in the Idle/Unassigned Cell Pattern and PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 Function Default HCSPASS 0 HCSDQDB 0 HCSADD 0 HCK 0 BLOCK 0 DSCR 0 OOCDV X FIFORST 0 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 182 ...
Page 199
... HCSPASS, cells containing detectable HCS errors are dropped. Note that all cells are dropped while an out of cell delineation defect is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 6 PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE ...
Page 200
... FIXPAT 0 DETHYST[1] 0 DETHYST[0] 0 Reserved 0 Cell Acceptance Threshold The first cell containing an error-free HCS The second consecutive cell containing no HCS errors. The fourth consecutive cell containing no HCS errors. The eighth consecutive cell containing no HCS errors. PM7344 S/UNI-MPH MULTI-PHY USER NETWORK INTERFACE 184 ...