DSPE56009FJ81 Freescale Semiconductor, Inc, DSPE56009FJ81 Datasheet

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... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS Motorola designed the Symphony™ family of high-performance, programmable Digital Signal Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, Dolby AC-3 Surround, MPEG1 Layer 2, and Digital Theater Sound (DTS) processing. Software ...

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... Freescale Semiconductor, Inc. SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “ ...

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... Freescale Semiconductor, Inc. FEATURES Digital Signal Processing Core • Efficient, object code compatible with the 24-bit DSP56000 core family engine • 81 MHz device can use a 27 MHz clock, eliminating the need for an externally generated clock signal, for instance in a DVD application • ...

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... Freescale Semiconductor, Inc. DSP56009 Features Peripheral and Support Circuits • Serial Audio Interface (SAI) includes two receivers and three transmitters, master or slave capability, implementation of I protocols; and two sets of SAI interrupt vectors • Serial Host Interface (SHI) features single master capability, 10-word receive FIFO, and support for 8-, 16-, and 24-bit words • ...

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... Freescale Semiconductor, Inc. PRODUCT DOCUMENTATION Table 2 lists the documents that provide a complete description of the DSP56009 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information) ...

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... Freescale Semiconductor, Inc. DSP56009 Product Documentation vi For More Information On This Product, DSP56009/D, Rev to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The DSP56009 input and output signals are organized into the nine functional groups, as shown in Table 1-1 . The individual signals are illustrated in Figure 1-1 . Table 1-1 DSP56009 Functional Group Signal Allocations Functional Group Power ( Ground (GND) Phase Lock Loop (PLL) ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions Signal Groupings Power Inputs V CCP 3 V CCQ 2 V CCA V CCD 2 V CCS Ground GND P 3 GND Q 4 GND A 2 GND D 3 GND S PCAP PINIT EXTAL 15 MA0–MA14 8 MD0–MD7 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS MCS0 MWR MRD MODA/IRQA ...

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... Freescale Semiconductor, Inc. POWER Power Name V PLL Power —V CCP voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V V Quiet Power —V CCQ input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions Clock and PLL signals CLOCK AND PLL SIGNALS Note: While the PLL on this DSP is identical to the PLL described in the DSP56000 Family Manual , two of the signals have not been implemented externally. Specifically, there is no PLOCK signal or CKOUT signal available. Therefore, the internal clock is not directly accessible and there is no external indication that the PLL is locked ...

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... Freescale Semiconductor, Inc. EXTERNAL MEMORY INTERFACE (EMI) Table 1-5 External Memory Interface (EMI) Signals Signal State during Signal Name Type Reset Table 1-6 MA0–MA14 Output Table 1-6 MA15 Output MCS3 Table 1-6 MA16 Output MCS2 MCAS Table 1-6 MA17 Output MCS1 MRAS Table 1-6 MCS0 Output ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions External Memory Interface (EMI) Table 1-5 External Memory Interface (EMI) Signals (Continued) Signal State during Signal Name Type Reset MD0–MD7 Bidi- Tri-stated rectional Table 1-6 EMI States during Reset and Stop States Signal Hardware Reset Software Reset Individual Reset MA0– ...

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... Freescale Semiconductor, Inc. INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the DSP’s operating mode as it comes out of hardware reset and receives interrupt requests from external sources after reset. Table 1-7 Interrupt and Mode Control Signals Signal State during ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions Interrupt and Mode Control Table 1-7 Interrupt and Mode Control Signals (Continued) Signal State during Signal Name Type Reset MODB Input Input (MODB) Mode Select B—This input signal has two functions: IRQB 1-8 For More Information On This Product, Signal Description • ...

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... Freescale Semiconductor, Inc. Table 1-7 Interrupt and Mode Control Signals (Continued) Signal State during Signal Name Type Reset MODC Input, Input (MODC) Mode Select C—This input signal has two functions: edge- triggered NMI RESET input active MOTOROLA For More Information On This Product, Signal Description • ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions Serial Host Interface (SHI) SERIAL HOST INTERFACE (SHI) The Serial Host Interface (SHI) has five I/O signals, which may be configured to operate in either SPI or I Table 1-8 Serial Host Interface (SHI) signals Signal Signal Name Type SCK Input or Tri-stated ...

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... Freescale Semiconductor, Inc. Table 1-8 Serial Host Interface (SHI) signals (Continued) Signal Signal Name Type MISO Input or Tri-stated Output SDA Input or Output MOSI Input or Tri-stated Output HA0 Input MOTOROLA For More Information On This Product, State during Signal Description Reset SPI Master-In-Slave-Out (MISO)—When the SPI is configured as a master, MISO is the master data input line ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions Serial Host Interface (SHI) Table 1-8 Serial Host Interface (SHI) signals (Continued) Signal Signal Name Type SS Input Tri-stated HA2 Input HREQ Input or Tri-stated Output 1-12 For More Information On This Product, State during Signal Description Reset SPI Slave Select (SS)—This signal is an active low Schmitt-trigger input when configured for the SPI mode ...

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... Freescale Semiconductor, Inc. SERIAL AUDIO INTERFACE (SAI) The SAI is composed of separate receiver and transmitter sections. SAI Receiver Section Table 1-9 Serial Audio Interface (SAI) Receiver signals Signal Signal State during Name Type SDI0 Input SDI1 Input SCKR Input or Output MOTOROLA For More Information On This Product, ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions Serial Audio Interface (SAI) Table 1-9 Serial Audio Interface (SAI) Receiver signals (Continued) Signal Signal State during Name Type WSR Input or Output 1-14 For More Information On This Product, Signal Description Reset Tri-stated Word Select Receive (WSR)—WSR is an output if the receiver section is configured as a master, and a Schmitt-trigger input if configured as a slave ...

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... Freescale Semiconductor, Inc. SAI Transmitter Section Table 1-10 Serial Audio Interface (SAI) Transmitter signals State Signal Signal during Name Type Reset SDO0 Output Driven High SDO1 Output Driven High SDO2 Output Driven High SCKT Input or Tri-stated Output WST Input or Tri-stated Output MOTOROLA ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions General Purpose I/O GENERAL PURPOSE I/O Table 1-11 General Purpose I/O (GPIO) Signals Signal Signal Name Type GPIO0– Standard GPIO3 Output, Open-drain Output, or Input ON-CHIP EMULATION (OnCE There are four signals associated with the OnCE port controller and its serial interface ...

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... Freescale Semiconductor, Inc. Table 1-12 On-Chip Emulation Port Signals (Continued) Signal Signal State during Name Type Reset DSCK Input Output, Driven Low OS1 Output DSO Output Driven High MOTOROLA For More Information On This Product, On-Chip Emulation (OnCE Signal Description Debug Serial Clock (DSCK)—The DSCK/OS1 signal, when an input, is the signal through which the serial clock is supplied to the OnCE port ...

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... Freescale Semiconductor, Inc. Signal/Connection Descriptions TM On-Chip Emulation (OnCE ) Port Table 1-12 On-Chip Emulation Port Signals (Continued) Signal Signal State during Name Type Reset DR Input Input 1-18 For More Information On This Product, Signal Description Debug Request (DR)—The debug request input provides a means of entering the Debug mode of operation. This signal, ...

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... Freescale Semiconductor, Inc. SPECIFICATIONS INTRODUCTION The DSP56009 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. MAXIMUM RATINGS This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings ...

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... Freescale Semiconductor, Inc. Specifications Thermal characteristics Table 2-1 Maximum Ratings (GND = 0 V Rating Supply Voltage All Input Voltages Current Drain per Pin excluding V Operating Temperature Range: • 81 MHz • 88 MHz Storage Temperature THERMAL CHARACTERISTICS Table 2-2 Thermal Characteristics Characteristic Junction-to-ambient thermal resistance ...

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... Freescale Semiconductor, Inc. DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics Characteristics Symbol Supply voltage V Input high voltage • EXTAL V • RESET V • MODA, MODB, V MODC 1 • SHI inputs V • All other inputs V Input low voltage • EXTAL V • MODA, MODB, V MODC 1 • SHI inputs V • ...

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... Freescale Semiconductor, Inc. Specifications AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS The timing waveforms in the AC Electrical Characteristics are tested with a V maximum of 0.5 V and a V MODA, MODB, MODC, and SHI pins (MOSI/HA0, SS/HA2, MISO/SDA, SCK/ SCL, HREQ). These pins are tested using the input levels set forth in the DC Electrical Characteristics ...

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... Freescale Semiconductor, Inc. EXTERNAL CLOCK (EXTAL PIN) The DSP56009 system clock is externally supplied via the EXTAL pin. Timings shown in this document are valid for clock rise and fall times maximum. The 81 MHz speed allows the DSP56009 to take advantage of the 27 MHz system clock in DVD applications ...

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... Freescale Semiconductor, Inc. Specifications Phase Lock Loop (PLL) Characteristics PHASE LOCK LOOP (PLL) CHARACTERISTICS Table 2-6 Phase Lock Loop (PLL) Characteristics Characteristics VCO frequency when PLL enabled PLL external capacitor (PCAP pin CCP Note: 1. Cpcap is the value of the PLL capacitor (connected between PCAP pin and V The recommended value for Cpcap is 400 pF for MF 4 and 540 pF for MF > ...

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... Freescale Semiconductor, Inc. Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (C No. Characteristics 27 Duration for Level Sensitive IRQA Assertion to ensure interrupt service (when exiting “STOP”) • Stable External Clock, OMR Bit • Stable External Clock, PCTL Bit Note: 1 ...

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... Freescale Semiconductor, Inc. Specifications RESET, Stop, Mode Select, and Interrupt Timing IRQA, IRQB, NMI IRQA, IRQB, NMI Figure 2-4 External Interrupt Timing (Negative Edge-triggered) General Purpose I/O (Output) 18 IRQA IRQB NMI Figure 2-5 External Level-sensitive Fast Interrupt Timing 25 IRQA Figure 2-6 Recovery from Stop State Using IRQA ...

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... Freescale Semiconductor, Inc. EXTERNAL MEMORY INTERFACE (EMI) DRAM TIMING ( TTL Loads) L Table 2-8 External Memory Interface (EMI) DRAM Timing No. Characteristics 41 Page Mode Cycle Time 42 RAS or RD Assertion to Data Valid 43 CAS Assertion to Data Valid 44 Column Address Valid to Data Valid 45 CAS Assertion to Data Active ...

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... Freescale Semiconductor, Inc. Specifications External Memory Interface (EMI) DRAM Timing Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued) No. Characteristics 54 CAS Deassertion Pulse Width (Page Mode Access Only) 55 Row Address Valid to RAS Assertion (Row Address Setup Time) 56 RAS Assertion to ROW Address Not Valid ...

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... Freescale Semiconductor, Inc. Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued) No. Characteristics 66 CAS Assertion to WR Deassertion 67 Data Valid to CAS Assertion (Data Setup Time) 68 CAS Assertion to Data Not Valid (Data Hold Time) 69 RAS Assertion to Data Not Valid 70 WR Assertion to CAS Assertion 71 WR Assertion Pulse Width ...

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... Freescale Semiconductor, Inc. Specifications External Memory Interface (EMI) DRAM Timing 48 MRAS 65 MCAS 55 MA0–MA10 MWR MRD MD0–MD7 Figure 2-8 DRAM Single Read Cycle 2-12 For More Information On This Product Row Address Last Column Address Data In DSP56009/D, Rev ...

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... Freescale Semiconductor, Inc. 48 MRAS 65 MCAS 55 Row Address MA0–MA10 MWR MRD MD0–MD7 Figure 2-9 DRAM Page Mode Read Cycle MOTOROLA For More Information On This Product, External Memory Interface (EMI) DRAM Timing Col. Address Col. Address 56 57 ...

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... Freescale Semiconductor, Inc. Specifications External Memory Interface (EMI) DRAM Timing 48 MRAS 65 MCAS 55 MA0–MA10 MWR MRD MD0–MD7 Figure 2-10 DRAM Single Write Cycle 2-14 For More Information On This Product Row Address Column Address Data Out DSP56009/D, Rev ...

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... Freescale Semiconductor, Inc. 48 MRAS 65 MCAS 55 MA0–MA10 Row Address MWR MRD MD0–MD7 Figure 2-11 DRAM Page Mode Write Cycle MOTOROLA For More Information On This Product, External Memory Interface (EMI) DRAM Timing Col. Address Col. Address 56 57 ...

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... Freescale Semiconductor, Inc. Specifications External Memory Interface (EMI) DRAM Refresh Timing EXTERNAL MEMORY INTERFACE (EMI) DRAM REFRESH TIMING (C = 50pF + 2 TTL Loads) L Table 2-9 External Memory Interface (EMI) DRAM Refresh Timing No. Characteristics 81 RAS Deassertion to RAS Assertion 82 CAS Deassertion to CAS Assertion 83 Refresh Cycle Time ...

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... Freescale Semiconductor, Inc. 81 MRAS 88 82 MCAS 89 MD0–MD7 Data In Figure 2-12 CAS before RAS Refresh Cycle EXTERNAL MEMORY INTERFACE (EMI) SRAM TIMING (C = 50pF + 2 TTL Loads) L Table 2-10 External Memory Interface (EMI) SRAM Timing No. Characteristics 91 Address Valid and CS Assertion Pulse Width 92 Address Valid ...

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... Freescale Semiconductor, Inc. Specifications External Memory Interface (EMI) SRAM Timing Table 2-10 External Memory Interface (EMI) SRAM Timing (Continued) No. Characteristics 98 RD Deassertion to Data Not Valid (Data Hold Time) 99 Address Valid to WR Deassertion 100 Data Setup Time to WR Deassertion 101 Data Hold Time from WR ...

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... Freescale Semiconductor, Inc. MA0–MA14 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS MCS0 WR RD MD0–MD7 MOTOROLA For More Information On This Product, External Memory Interface (EMI) SRAM Timing 100 102 Data Out 104 101 Figure 2-14 SRAM Write Cycle DSP56009/D, Rev to: www.freescale.com Specifications ...

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... Freescale Semiconductor, Inc. Specifications Serial Audio Interface (SAI) Timing SERIAL AUDIO INTERFACE (SAI) TIMING ( TTL Loads) L Table 2-11 Serial Audio Interface (SAI) Timing No. Characteristics 111 Minimum Serial Clock Cycle = t (min) SAICC 112 Serial Clock High Period 113 Serial Clock Low Period ...

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... Freescale Semiconductor, Inc. SCKR (RCKP = 1) SCKR (RCKP = 0) SDI0–SDI1 (Data Input) WSR (Input) WSR (Output) Figure 2-15 SAI Receiver Timing MOTOROLA For More Information On This Product, Serial Audio Interface (SAI) Timing 111 112 114 113 111 113 114 112 115 116 Valid ...

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... Freescale Semiconductor, Inc. Specifications Serial Audio Interface (SAI) Timing SCKT (TCKP = 1) SCKT (TCKP = 0) SDO0–SDO2 (Data Output) WST (Input) WST (Output) Figure 2-16 SAI Transmitter Timing 2-22 For More Information On This Product, 111 112 114 113 111 113 114 112 121 124 123 Valid DSP56009/D, Rev ...

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... Freescale Semiconductor, Inc. SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING ( pF 0.7 L IHS Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing No. Characteristics Mode — Tolerable Spike Width 5 on Clock or Data In 141 Minimum Serial Clock Cycle = t (min) SPICC For frequency below 33 1 MHz ...

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... Freescale Semiconductor, Inc. Specifications Serial Host Interface (SHI) SPI Protocol Timing Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics Mode 146 SS Assertion to First slave SCK Edge CPHA = 0 CPHA = 1 slave 147 Last SCK Edge to SS slave Not Asserted CPHA = 0 3 CPHA = 1 ...

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... Freescale Semiconductor, Inc. Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics Mode 153 SCK Edge to Data Out master Not Valid (Data Out Hold Time) slave 154 SS Assertion to Data slave Out Valid CPHA = 0 157 First SCK Sampling slave Edge to HREQ Output ...

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... Freescale Semiconductor, Inc. Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 142 SCK (CPOL = 0) (Output) 143 SCK (CPOL = 1) (Output) 148 MISO (Input) MOSI (Output) 161 HREQ (Input) Figure 2-17 SPI Master Timing (CPHA = 0) 2-26 For More Information On This Product, 143 144 142 ...

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... Freescale Semiconductor, Inc. SS (Input) 142 SCK (CPOL = 0) (Output) 143 SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Figure 2-18 SPI Master Timing (CPHA = 1) MOTOROLA For More Information On This Product, Serial Host Interface (SHI) SPI Protocol Timing 143 144 142 144 ...

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... Freescale Semiconductor, Inc. Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 MOSI (Input) 157 HREQ (Output) Figure 2-19 SPI Slave Timing (CPHA = 0) 2-28 For More Information On This Product, 143 ...

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... Freescale Semiconductor, Inc. SS (Input) 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 152 150 MISO (Output) MOSI (Input) HREQ (Output) Figure 2-20 SPI Slave Timing (CPHA = 1) MOTOROLA For More Information On This Product, Serial Host Interface (SHI) SPI Protocol Timing 143 144 142 ...

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... Freescale Semiconductor, Inc. Specifications Serial Host Interface (SHI) I2C Protocol Timing SERIAL HOST INTERFACE (SHI 0 IHS CC ILS ( OHS CC (R (min Table 2-13 SHI I No. Characteristics — Tolerable Spike Width on SCL or SDA Filters Bypassed Narrow Filters Enabled Wide Filters Enabled ...

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... Freescale Semiconductor, Inc. The Programmed Serial Clock Cycle, t HDM0 and HRS bits of the HCKR (SHI Clock control Register). The expression for CCP where • HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-by- eight prescaler is operational. When HRS is set, the prescaler is bypassed. ...

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... Freescale Semiconductor, Inc. Specifications Serial Host Interface (SHI) I2C Protocol Timing Example: for pF when operating with a DSP56009 SHI I must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum permissible CCP This implies a maximum I In general, bus performance may be calculated from the C Input Filter modes and operating frequencies of the master and the slave ...

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... Freescale Semiconductor, Inc. Table 2-15 SHI Improved I Improved I No. Char. Sym. Mode 175 SCL Low Period t master LOW slave 176 SCL High Period t master HIGH slave 177 SCL Rise Time Output Input 178 SCL Fall Time Output Input 179 Data Set-up Time t SU ...

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... Freescale Semiconductor, Inc. Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-15 SHI Improved I Improved I No. Char. Sym. Mode 184 HREQ In master bypassed Deassertion to Last SCL Edge (HREQ In Set-up Time) 186 First SCL slave Sampling Edge to HREQ Output Deassertion 187 Last SCL Edge to ...

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... Freescale Semiconductor, Inc. 173 176 SCL 177 172 SDA MSB Stop Start 174 188 HREQ MOTOROLA For More Information On This Product, Serial Host Interface (SHI) I2C Protocol Timing 171 175 180 178 179 LSB 186 182 189 184 2 Figure 2- Timing DSP56009/D, Rev ...

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... Freescale Semiconductor, Inc. Specifications General Purpose I/O (GPIO) Timing GENERAL PURPOSE I/O (GPIO) TIMING ( TTL Loads) L No. Characteristics 201 EXTAL Edge to GPIO Out Valid (GPIO Out Delay Time) 202 EXTAL Edge to GPIO Out Not Valid (GPIO Out Hold Time) 203 GPIO In Valid to EXTAL Edge (GPIO In Set-up Time) ...

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... Freescale Semiconductor, Inc. ON-CHIP EMULATION (OnCE ) TIMING ( TTL Loads) L No. Characteristics 230 DSCK Low 231 DSCK High 232 DSCK Cycle Time 233 DR Asserted to DSO (ACK) Asserted 234 DSCK High to DSO Valid 235 DSCK High to DSO Invalid 236 DSI Valid to DSCK Low (Set-up) ...

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... Freescale Semiconductor, Inc. Specifications On-Chip Emulation (OnCE ) Timing Table 2-17 OnCE Timing (Continued) No. Characteristics 250A DR Assertion Width to Recover from STOP • Stable External Clock, OMR Bit • Stable External Clock, OMR Bit • Stable External Clock, PCTL Bit 250B ...

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... Freescale Semiconductor, Inc. DSCK (Input) DSO (Output) 236 DSI (Input) Note: 1. High Impedance, external pull-down resistor Figure 2-25 DSP56009 OnCE Data I/O to Status Timing DSCK (Input) 234 DSO (Output) Note: 1. High Impedance, external pull-down resistor Figure 2-26 DSP56009 OnCE Read Timing OS1 (Output) 241 ...

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... Freescale Semiconductor, Inc. Specifications On-Chip Emulation (OnCE ) Timing EXTAL (Note 2) OS0–OS1 (Output) (Note 1) Note: 1. High Impedance, external pull-down resistor 2. Valid when the ratio between EXTAL frequency and clock frequency equals 1 Figure 2-28 DSP56009 OnCE EXTAL to Status Timing DSCK (Input) Figure 2-29 DSP56009 OnCE DSCK Next Command After Read Register Timing ...

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... Freescale Semiconductor, Inc. DR (Input) DSO (Output) Figure 2-32 Asynchronous Recovery from Stop State MOTOROLA For More Information On This Product, On-Chip Emulation (OnCE ) Timing 250 251 DSP56009/D, Rev to: www.freescale.com Specifications AA0286 2-41 ...

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... Freescale Semiconductor, Inc. Specifications On-Chip Emulation (OnCE ) Timing 2-42 For More Information On This Product, DSP56009/D, Rev to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. PIN-OUT AND PACKAGE INFORMATION This section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56009 is available in an 80-pin Quad Flat Pack (QFP) package. ...

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... Freescale Semiconductor, Inc. Packaging Pin-out and Package Information QFP Package Description Top and bottom views of the QFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs MD7 MD6 MD5 MD4 GND D MD3 MD2 MD1 V CCD MD0 GND D GPIO3 GPIO2 GPIO1 ...

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... Freescale Semiconductor, Inc CCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GND S V CCP PCAP GNDP PINIT GND Q V CCQ EXTAL SCK/SCL MA0 MA1 MA2 MA3 21 GND A Note: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration ...

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... Freescale Semiconductor, Inc. Packaging Pin-out and Package Information Table 3-1 DSP56009 Pin Identification by Pin Number Pin # Signal Name 1 GND A 2 MCS0 3 MA15/MCS3 4 MA14 5 MA13 6 V CCA 7 MA12 8 GND CCQ 10 GND Q 11 MA11 12 MA10 13 MA9 14 MA8 15 GND A 16 MA7 17 V CCA 18 MA6 ...

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... Freescale Semiconductor, Inc. Table 3-2 DSP56009 Pin Identification by Signal Name Signal Name Pin # DR 61 DSCK 60 DSI 59 DSO 58 EXTAL 27 GND 1 A GND 8 A GND 15 A GND 21 A GND 66 D GND 72 D GND 31 P GND 10 Q GND 29 Q GND 52 Q GND 34 S GND 44 S GND ...

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... Freescale Semiconductor, Inc. Packaging Pin-out and Package Information Table 3-3 DSP56009 Power Supply Pins Pin # Signal Name 6 V CCA 17 1 GND CCD 66 GND CCQ GND CCP 31 GND CCS 48 34 GND 3-6 For More Information On This Product, ...

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... Freescale Semiconductor, Inc - - 0.05 A -C- H SEATING PLANE G DATUM -H- PLANE DETAIL C Figure 3-3 80-pin Quad Flat Pack (QFP) Mechanical Information MOTOROLA For More Information On This Product - DETAIL A A DETAIL C ...

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... Freescale Semiconductor, Inc. Packaging Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56009 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: • The receiving facsimile telephone number including area code or country code • ...

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... Freescale Semiconductor, Inc. DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, T equation: Equation Where ambient temperature ˚ package junction-to-ambient thermal resistance ˚C power dissipation in package D Historically, thermal resistance has been expressed as the sum of a junction-to-case ...

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... Freescale Semiconductor, Inc. Design Considerations Thermal Design Considerations The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from R do not satisfactorily answer whether the thermal performance is adequate system level model may be appropriate. ...

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... Freescale Semiconductor, Inc. ELECTRICAL DESIGN CONSIDERATIONS This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e ...

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... Freescale Semiconductor, Inc. Design Considerations Power Consumption Considerations POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is Alternating Current (AC), which is charging and discharging the capacitances of the pins and internal nodes ...

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... Freescale Semiconductor, Inc. Current consumption test code: org p:RESET jmp MAIN org p:MAIN movep #$180000,x:$FFFD move #0,r0 move #0,r4 move #$00FF,m0 move #$00FF,m4 nop rep #256 move rep #256 mov r4,y:(r4)+ clr a move rep #30 mac x0,y0,a move jmp TP1 nop jmp MAIN MOTOROLA For More Information On This Product, ...

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... Freescale Semiconductor, Inc. Design Considerations Power-Up Considerations POWER-UP CONSIDERATIONS To power-up the device properly, ensure that the following conditions are met: • Stable power is applied to the device according to the specifications in Table 2-3 (DC Electrical Characteristics). • The external clock oscillator is active and stable. • RESET is asserted according to the specifications in Table 2-7 (Reset, Stop, Mode Select, and Interrupt Timing). • ...

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... This part can be ordered only by customers licensed for DTS. To request specific support for this chip, call your local Motorola Semiconductor sales office or authorized distributor. MOTOROLA For More Information On This Product, SECTION 5 Package Type Pin Count DSP56009/D, Rev to: www.freescale.com Frequency Order Number (MHz) 81 DSPE56009FJ81 88 DSPE56009FJ88 81 DSPF56009FJ81 88 DSPF56009FJ88 81 DSPH56009FJ81 88 DSPH56009FJ88 81 DSPI56009FJ81 88 DSPI56009FJ88 5-1 ...

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... Freescale Semiconductor, Inc. OnCE and Mfax are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...