LH28F160BJD-TTL80 Sharp, LH28F160BJD-TTL80 Datasheet
LH28F160BJD-TTL80
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LH28F160BJD-TTL80 Summary of contents
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... Flash Memory LH28F160BJD-TTL80 Date Jul. 14. 2003 ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 Read.............................................................................. ...
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... Thirty-one 32K-word Main Blocks Top Boot Location Extended Cycling Capability Minimum 100,000 Block Erase Cycles SHARP’s LH28F160BJD-TTL80 Flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F160BJD-TTL80 can operate at V cellular phone application. Its Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers ...
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... Low power consumption Enhanced Suspend Capabilities Boot Block Architecture 1.2 Product Overview The LH28F160BJD-TTL80 is a high-performance 16M- bit Boot Block Flash memory organized as 1M-word of 16 bits. The 1M-word of data is arranged in two 4K-word boot blocks, six 4K-word parameter blocks and thirty-one 32K-word main blocks which are individually erasable, lockable and unlockable in-system ...
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... For example, changing data from "10111101" to "10111100" requires "11111110" programming. 1.3 Product Description supply voltage CC 1.3.1 Package Pinout LH28F160BJD-TTL80 Boot Block Flash memory is available in 42-lead DIP package (see Figure 2). CCR 1.3.2 Block Organization This product architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times ...
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DQ Output Buffer Identifier Register Register Comparator Y Input Y-Gating A -A Decoder 0 19 Buffer Address X Decoder Latch Address Counter Figure 1. Block Diagram ...
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Symbol Type ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle INPUT Main Block Address Boot and Parameter Block ...
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... PRINCIPLES OF OPERATION The LH28F160BJD-TTL80 flash memory includes an on- chip WSM to manage block erase, full chip erase, word write and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, word write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings ...
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Data Protection The CUI, with two-step block erase, full chip erase, word write or lock-bit configuration command sequences, provides protection from unwanted operations. All write functions are disabled when V is below the write CC lockout voltage V . ...
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Read Identifier Codes The read identifier codes operation manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically ...
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Mode Read Output Disable Standby Read Identifier Codes Write NOTES: 1. Refer to DC Characteristics can for control pins and addresses See Section 4.2 for read identifier code data. 4. Command ...
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... If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done. 9. Once the permanent lock-bit is set, permanent lock-bit reset is unable. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. ...
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Read Array Command Upon initial device power-up, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal ...
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Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address ...
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Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or word write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM ...
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Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a permanent lock- bit. The block lock-bits gates program and erase operations while the permanent lock-bit gates ...
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Permanent Operation Lock-Bit Block Erase or X Word Write Full Chip Erase X Set Block Lock-Bit 0 1 Clear Block 0 Lock-Bits 1 Set Permanent Lock-Bit X WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS) ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.1= Device ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H Write Word Data and Address Read Status Register No 0 Suspend SR.7= Word Write Yes 1 Full Status Check if Desired Word Write Complete FULL STATUS CHECK ...
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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Word Write Read Read or Word Write ? Read Array Data Word Write Loop No Done? Yes Write D0H Write FFH Read Array Data Block ...
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Start Write B0H Read Status Register 0 SR. Word Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word Write Resumed Read Array Data Figure 9. Word Write Suspend/Resume Flowchart ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.1= ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.1= Device ...
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... DESIGN CONSIDERATIONS 5.1 Two-Line Output Control The device will often be used in large memory arrays. SHARP provides two control inputs to accommodate multiple memory connections. Two-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word Write and Lock-Bit Configuration ................0°C to +85°C Storage Temperature During under Bias ............................... -10°C to +85°C During non Bias ................................ -65°C to +125°C ...
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AC INPUT/OUTPUT TEST CONDITIONS 3.0 INPUT 0.0 AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Auto Power-Save Current CCAS Read Current CCR Word Write or Set ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t OE# to Output Delay GLQV t CE# to Output in Low Z ELQX t CE# ...
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AC CHARACTERISTICS - WRITE OPERATIONS Sym. t Write Cycle Time AVAV t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t Address Setup to WE# Going High AVWH t Data Setup to WE# Going High ...
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ALTERNATIVE CE#-CONTROLLED WRITES Sym. t Write Cycle Time AVAV t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t Address Setup to CE# Going High AVEH t Data Setup to CE# Going High DVEH t ...
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BLOCK ERASE, FULL CHIP ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION (3) PERFORMANCE Sym. Parameter t Word Write Time WHQV1 t EHQV1 Block Write Time t Block Erase Time WHQV2 t EHQV2 Full Chip Erase Time t WHQV3 Set Lock-Bit ...
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ADDITIONAL INFORMATION 1 Block Erase Suspend and Resume command If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than 15ms and both commands are written repeatedly, a longer time is ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...