SAA8112HL/C201 Winbond, SAA8112HL/C201 Datasheet

SAA8112HL/C201

Manufacturer Part Number

SAA8112HL/C201

Description

DRAM Chip, DDR SDRAM, 8MByte, 2.5V Supply, Commercial, LQFP, 100-Pin

Manufacturer

Winbond

Datasheet

1.W946432AD-5H.pdf (39 pages)

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GENERAL DESCRIPTION

The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access

memory organized as 512K words x 4 banks x 32 bits.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at

the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory

controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for

WRITEs.

The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH

and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control

signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well as to both edges of CLK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location

and continue for a programmed number of locations in a programmed sequence. Accesses begin with

the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE command are used to select the bank and row to

be accessed. The address bits registered coincident with the READ or WRITE command are used to

select the bank and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 locations. An

AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at

the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for

concurrent operation, thereby providing high effective bandwidth by hiding row precharge and

activation time.

FEATURES

•

Double-data-rate architecture; two data transfers

Bidirectional, data strobe (DQS) is transmitted/

DQS is edge-aligned with data for READs;

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transitions with CLK

Programmable DLL on or DLL off mode

per clock cycle

received with data, to be used in capturing data

at the receiver

center-aligned with data for WRITEs

transitions

data and data mask referenced to both edges of

DQS

Commands entered on each positive CLK edge;

512K × 4 BANKS × 32 BITS DDR SDRAM

•

Four internal banks for concurrent operation

Data mask (DM) for write data

Burst lengths: 2, 4

CAS Latency: 3

AUTO PRECHARGE option for each burst

Auto Refresh and Self Refresh Modes

15.6us Maximum Average Periodic Refresh

SSTL_2 compatible I/O

For –5H V

For –55/-6 V

access

Interval

DD/

Q = 2.6V ± 0.1V

PRELIMINARY DATA:11/13/01

Q = 2.5V ± 6%

W946432AD

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SAA8112HL/C201 Summary of contents

Page 1

BANKS × 32 BITS DDR SDRAM GENERAL DESCRIPTION The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access memory organized as 512K words x 4 banks x 32 bits. A bidirectional data strobe (DQS) ...

Page 2

PIN CONFIGURATION 100 DQ3 DQ4 3 DQ5 DQ6 6 DQ7 DQ16 9 DQ17 10 ...

Page 3

PIN DESCRIPTION PIN NAME FUNCTION All address and control input signals are sampled on the crossing of the positive edge of CLK Differential clock and negative edge of CLK . Output (read) data is referenced to the crossings of CLK ...

Page 4

BLOCK DIAGRAM CLK DLL CLK CLOCK BUFFER CKE CONTROL CS SIGNAL GENERATOR RAS COMMAND CAS DECODER WE A8 MODE A0 REGISTER A7, ADDRESS A9,A10 BUFFER BA0 BA1 COLUMN REFRESH COUNTER COUNTER COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER Prefetch ...

Page 5

ABSOLUTE MAXIMUM RATINGS* SYMBOL V Input Voltage IN V Output Voltage OUT V Power Supply Voltage I/O Power Supply Voltage DD T Operating Temperature OPR T Storage Temperature STG T Soldering Temperature(10s) SOLDER P Power Dissipation D ...

Page 6

AC OPERATING CONDITIONS ≤ ≤ (0 ° ° +2. PARAMETER/CONDITION Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input ...

Page 7

AC CHARACTERISTICS ≤ ≤ (0 ° °C; for –55 / –6 VDD/VDDQ= 2.5V ± 6% for ”-5H” VDD/VDDQ = +2.6V ± 0.1V, VDD = +2.6V ± 0.1V) PARAMETER DQ output access time from CLK/ CLK DQS output access ...

Page 8

NOTES 1. All voltages referenced Outputs measured with equivalent load expected to be equal to 0.5*V REF of the same. Peak-to-peak noise not applied directly to the device. ...

Page 9

FUNCTIONAL DESCRIPTION The W946432AD is a high speed CMOS, dynamic random access memory containing 67,108,864 bits. The W946432AD is internally configured as a quad bank DRAM. The W946432AD uses a double data rate architecture to achieve high speed operation. The ...

Page 10

REGISTER DEFINITION MODE REGISTER The Mode Register is programmed by the MODE REGISTER SET command (MRS/EMRS) are idle and no bursts are in progress The Mode Register is used to define the operation specific mode of of the DDR SDRAM. ...

Page 11

Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Table 1: The burst length determines the maximum number of column locations that can be accessed for a ...

Page 12

Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency is set to 3 clocks READ command is ...

Page 13

COMMANDS Truth Table provides a quick reference of available commands. This is followed by a verbal description of each command. The additional Function Truth Tables provide current state/ next state information. Symbol Command ACT Bank Active PRE Bank Precharge PREA ...

Page 14

Function TRUTH TABLE (NOTE 1) CURRENT CS RAS CAS STATE Idle ...

Page 15

NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH. 2. ILLEGAL if any bank is not idle. 3. ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank ...

Page 16

DESELECT The Device Deselect command disables the command decoder so that the RAS CAS WE and Address inputs are ignored. This command is similar to the No-Operation command. NO OPERATION (NOP) The No Operation Command should be used in cases ...

Page 17

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute ...

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