W946432AD-5H Winbond, W946432AD-5H Datasheet
W946432AD-5H
Related parts for W946432AD-5H
W946432AD-5H Summary of contents
Page 1
... WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control signals) are registered at every positive edge of CLK ...
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... DM0 23 DM2 CAS 26 RAS BA0 29 BA1 512K × 4 BANKS × 32 BITS DDR SDRAM W946432AD DQ28 DQ27 77 DQ26 DQ25 74 DQ24 ...
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... Used to capture write data Power For –5H VDDQ = 2.6V ± 0.1V, For –55/-6 VDDQ = 2.5V ± 0. Ground Ground Supply Power For –5H VDD = 2.6V ± 0.1V,For –55/-6 VDD = 2.5V ± Ground Connection No connection V SSTL_2 reference voltage. REF W946432AD DESCRIPTION ...
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... COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER Prefetch Register DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 2048 * 256 * 32 W946432AD COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQn DQS DM COLUMN DECODER CELL ARRAY ...
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... DD A SYMBOL = +2. SYMBOL REF W946432AD UNIT +0 Q+0 ° C 0~70 ° C 260 ° MIN MAX UNITS Cl1 2.5 3.5 Cl2 2.5 3.5 Cl0 4.0 5.5 MIN MAX 2.5 2.7 2.5 2.7 1.25 1.35 V -0. 0.04 REF REF V +0 ...
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... (AC (AC +2.5V mA; OUT (MIN); All banks idle; IH ≥ V (MIN); CKE V (MIN 0.2V W946432AD MIN MAX UNITS V + REF 0. REF 0.35 0 0.6 DD 0.5*V Q-0.2 0.5*V Q+0 +0.76 REF V -0.76 REF SYMBOL MAX UNITS ICC1 165 mA ICC2P 2 mA ICC2N 60 mA ...
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... W946432AD 55 -6 UNIT NOTE tCK -0.1 0.1 -0.1 0.1 tCK -0.1 0.1 -0.1 0.1 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 tCK 5 0.5 0.5 ns tCK -0.1 0.1 -0.1 0.1 tCK -0.1 0.1 -0.1 0.1 ns 0.5 0.5 0.45 0.45 ns 0.2 0.2 tCK ...
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... ohms A.C TEST LOAD Q of the transmitting device, and to track variations in the DC level DD may not exceed +/-2% of the DC value. REF is a system supply for signal termination resistors, is expected TT CLK Vix CLK VssQ 8 W946432AD VTT ohms T 30pF . REF Vix PRELIMINARY DATA:11/13/01 ...
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... I/O pins. A single read or write access for the W946432AD consists of a single 32bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding 32bit wide, one half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented ...
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... Reserved 3 Reserved Reserved Reserved Reserved Operating Mode Normal Operation Normal Operation/Reset DLL Vendor Specific Test Mode All other states reserved 10 W946432AD EXTENDED MODE REGISTER DEFINITION BA0 BA1 A10 Operating Mode ...
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... Type = Sequential 0-1-2-3-4-5-6 1-2-3-4-5-6-7 2-3-4-5-6-7-0 3-4-5-6-7-0-1 4-5-6-7-0-1-2 5-6-7-0-1-2-3 6-7-0-1-2-3-4 7-0-1-2-3-4-5-6 11 W946432AD Order of Accesses Within a Burst Type = Interleaved – – 0 0–1–2-3 0-1-2-3 1–2–3–0 1-0-3-2 2–3–0–1 2-3-0-1 3–0–1–2 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 ...
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... Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength Programable DS0 Figure2:REQUIRED CAS LATENCIES REQUIRED CAS LATENCIES READ NOP NOP CL=3 12 W946432AD NOP NOP NOP DON'T CARE ...
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... X X Any Idle Idle Idle (S.R) Idle Active (5) Any (Power down) Active Active W946432AD BA0,1 A8 A10, CS RAS CAS A9 ...
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... Continue burst to end H X NOP Continue burst to end L X BST ILLEGAL H BA, CA,A8 Read, Read A ILLEGAL L BA, CA,A8 Write, Write A ILLEGAL H BA, RA ACT ILLEGAL L BA, A8 PRE, PRE A ILLEGAL H X AREF, SREF ILLEGAL L Op-Code MRS, EMRS ILLEGAL 14 W946432AD NOTE 6 ...
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... ACTIVE Read Read A Write A PRE PRE PRE PRE CHARGE PRE ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge BST = B nst Read Stpop 15 W946432AD SELF REFRESH AUTO REFRESH POWER DOWN Read Read Read A Read A Automatic Sequence Command Sequence ...
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... The Auto Refresh command is register when CS RAS CAS low with WE high. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The W946432AD requires AUTO REFRESH cycles at an average periodic interval of 15.6µs (maximum). ...
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... A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. W946432AD PRELIMINARY DATE: 11/13/ ...
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... READ command, where x equals the number of desired data element pairs. Note that part of the row precharge time is hIccen during the access of the last data elements. Figure4:tRCD and tRRD Definition tRCD and tRRD Definition NOP NOP ACT Row Bank y tRRD 18 W946432AD NOP NOP RD/WR NOP Col Bank y tRCD DON'T CARE PRELIMINARY DATE: 11/13/01 . ...
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... Figure5:READ BURST – REQUIRED CAS LATENCIES CK CK COMMAND READ ADDRESS DQS Data Out from column n Burst Length = 4 Show with nominal tAC, tDQSCK, and tDQSQ READ BURST - REQUIRED CAS LATENCIES NOP NOP NOP Bank, Col n CL=3 19 W946432AD NOP NOP DO n DON'T CARE PRELIMINARY DATE: 11/13/01 . ...
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... Data Out from column n (or column b) Burst Length = 4 Shown with nominal tAC, tDQSCK, and tDQSQ NOP READ NOP NOP Bank, Col n CL NOP NOP READ NOP Bank, Col b CL W946432AD NOP NOP DO b DON'T CARE NOP NOP DO b DON'T CARE PRELIMINARY DATE: 11/13/01 . ...
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... Shown with nominal tAC, tDQSCK, and tDQSQ RANDOM READ ACCESSES - REQUIRED CAS LATENCIES READ READ READ Bank, Bank, Bank, Col x Col b Col g CL TERMINATING A READ BURST - REQUIRED CAS LATENCIES NOP BST NOP CL=3 21 W946432AD READ NOP NOP DON'T CARE NOP NOP DO n ...
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... Shown with nominal tAC, tDQSCK, and tDQSQ READ TO WRITE - REQUIRED CAS LATENCIES BST NOP NOP CL READ TO PRECHARGE - REQUIRED CAS LATENCIES NOP PRE NOP Bank (a or all) CL=3 22 W946432AD NOP WRITE NOP Bank, Col b t DQSS DON'T CARE NOP ACT t RP Bank, Row DO ...
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... In power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later. 23 W946432AD ...
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... Col b t DQSS DQS Figure13:WRITE TO WRITE – DQSS WRITE TO WRITE - DQSS WRITE NOP WRITE NOP Bank, Bank, Col b Col n t DQSS W946432AD NOP DON'T CARE T10 T11 NOP NOP DON'T CARE PRELIMINARY DATE: 11/13/01 . ...
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... RANDOM WRITE CYCLES - DQSS WRITE WRITE WRITE Bank, Bank, Bank, Col b Col x Col n t DQSS W946432AD WRITE NOP Bank, Col DON'T CARE WRITE WRITE Bank, Bank, Col a Col ...
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... NOP Bank, Col b t DQSS DI b WRITE TO PRECHARGE - DQSS, NON-INTERRUPTING WRITE NOP NOP NOP Bank a, Col b t DQSS W946432AD T10 T11 NOP READ NOP t WTR Bank, Col n CL=3 DON'T CARE T10 T11 NOP PRE t ...
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... T5 WRITE NOP NOP NOP t WR Bank a, Col b t DQSS Figure19:POWER - DOWN POWER - DOWN t IS NOP Enter power-down mode 27 W946432AD T10 T11 PRE NOP Bank (a or all DON'T CARE t IS NOP VALID Enter power-down mode DON'T CARE PRELIMINARY DATE: 11/13/01 ...
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... DQS transitions in the center among DQ signal transitions. 4.Burst Length = 4 Figure20:DATA INPUT (WRITE) TIMING DATA INPUT (WRITE) TIMING t t DQSL DQSH Figure21:DATA OUTPUT (READ) TIMING t DQSQ max W946432AD DON'T CARE t DQSQ nom t DQSQ min PRELIMINARY DATE: 11/13/01 . ...
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... Precharge Power Down. If this command is an ACTIVE ( least one row is already active) then the Power-Down mode shown is Active Power Down Figure22:POWER – DOWN MODE t t POWER- DOWN MODE NOP Enter Power-Down Mode 29 W946432AD t IS NOP VALID VALID Exit Power-Down Mode DON'T CARE ...
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... NOP commands are shown for ease of illustration; other valid commands may be possible at these time DM, DQ and DQS signals are all "Do'nt Care"/High-z for operations shown Figure23:AUTO REFRESH MODE AUTO REFRESH MODE NOP NOP AR NOP W946432AD AR NOP NOP ACT DON'T CARE ...
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... CLK) are required befor READ command can be applied. Figure24:SELF REFRESH MODE clock must be before t CL exiting Self Refresh Mode Enter Self Refresh Mode 31 W946432AD VALID NOP VALID t XSNR/ t ...
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... NOP ALL BANKS ONE BANK *Bank DQSCK t RPRE min t LZ min min AC min t DQSCK t RPRE max max AC max 32 W946432AD NOP ACT NOP Bank RPST t HZ min t RPST t HZ max DON'T CARE NOP ...
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... READ-WITH AUTO PRECHARGE NOP NOP NOP NOP DQSCK t RPRE min t LZ min min AC min t DQSCK t RPRE max max AC max 33 W946432AD NOP ACT NOP Bank RPST t HZ min t RPST t HZ max NOP DON'T CARE ...
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... Note that tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting) Figure27:BANK READ ACCESS t BANK READ ACCESS CL NOP NOP READ NOP Col DIS AP Bank x t RAS t RCD 34 W946432AD NOP PRE NOP NOP ALL BANKS ONE BANK *Bank CL DQSCK RPST t RPRE min t ...
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... CH CL WRITE - WITHOUT AUTO PRECHARGE t IH NOP NOP NOP NOP DSH DSH t t DQSH WPST t DQSL DSS DSS t DQSH t WPST t DQSL W946432AD PRE NOP NOP ACT RA ALL BANKS RA ONE BANK *Bank DON'T CARE RA BA ...
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... NOP commands are shown for ease of illustration; other commands may be valid at these times WRITE - WITH AUTO PRECHARGE NOP NOP NOP NOP t t DSH DSH t t DQSH WPST t DQSL DSS DSS t DQSH t WPST t DQSL W946432AD NOP NOP NOP ACT DAL DON'T CARE ...
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... Col DIS AP *Bank RCD RAS t DSH t DQSH t DQSS t WPRES t WPRE DQSS t WPRES t WPRE 37 W946432AD NOP NOP NOP DSH t WPST t DQSL t t DSS DSS DQSH t WPST t DQSL DI n PRE ALL BANKS ONE BANK *Bank x DON'T CARE ...
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... Figure31:WRITE – DM OPERATION WRITE - DM OPERATION t IH NOP NOP NOP NOP DSH DSH t t DQSH WPST t DQSL DSS DSS t DQSH t WPST t DQSL W946432AD PRE NOP NOP ACT ALL BANKS ONE BANK *Bank DON'T CARE ...
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... D 14.00 0.547 0.551 0.555 13.90 E 19.90 20.00 0.783 0.787 0.791 e 0.498 0.020 0.026 0.032 0.65 H 0.626 0.634 0.630 15.90 16. 0.862 0.870 21.90 22.00 22.10 0.866 E L 0.024 0.030 0.45 0.60 0.018 L 0.039 1. 0.003 θ W946432AD c θ Max 0.15 1.45 0.38 0.20 14.10 20.10 0.802 16.10 0.75 0.08 7 ...