FW82439HX Intel Corporation, FW82439HX Datasheet
FW82439HX
Specifications of FW82439HX
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FW82439HX Summary of contents
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... Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 430TX PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property of their respective owners. © INTEL CORPORATION 1997 PRELIMINARY Fully Synchronous, Minimum Latency ...
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H D [63: Interface ...
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ARCHITECTURE OVERVIEW ........................................................................................................................6 2.0. SIGNAL DESCRIPTION ..................................................................................................................................8 2.1. MTXC Signals ...............................................................................................................................................8 2.1.1. Host Interface.........................................................................................................................................8 2.1.2. DRAM Interface ...................................................................................................................................10 2.1.3. Secondary Cache Interface .................................................................................................................12 2.1.4. PCI Interface ........................................................................................................................................13 2.1.5. Test and Clock .....................................................................................................................................14 2.1.6. Power Management .............................................................................................................................14 2.1.7. Power and ...
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PAM Programmable Attribute Map Registers (PAM[6:0])...............................................................34 3.1.22. DRB DRAM Row Boundary Registers............................................................................................38 3.1.23. DRTH DRAM Row Type Register High ..........................................................................................40 3.1.24. DRTL—DRAM Row Type Register Low............................................................................................41 3.1.25. MTT Multi-Transaction Timer Register (Reserved Test Mode Register)........................................41 3.1.26. ESMRAMC ...
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CLOCKS AND RESET ..................................................................................................................................70 5.1. Clock Generation and distribution...............................................................................................................70 5.2. RESET Sequencing ....................................................................................................................................70 6.0. PINOUT INFORMATION ...............................................................................................................................71 7.0. MTXC PACKAGE INFORMATION................................................................................................................76 8.0. TESTABILITY.................................................................................................................................................79 8.1. NAND Tree Mode .......................................................................................................................................79 8.2. NAND Chain Mode .....................................................................................................................................79 PRELIMINARY 82439TX (MTXC) 5 ...
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ARCHITECTURE OVERVIEW The MTXC host bridge provides a completely integrated solution for the system controller and datapath components in a Pentium processor system. The MTXC Supports all Pentium family processors since P54C, it has 64-bit Host and ...
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SUSSTAT1# signals are used for implementing Suspend Logic. The MTXC supports two SMRAM modes; Compatible SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM). The C_SMRAM is the traditional SMRAM feature implemented in Intel PCIsets. The E_SMRAM is a new feature that supports ...
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SIGNAL DESCRIPTION This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, ...
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Name Type AHOLD O Address Hold. The MTXC asserts AHOLD when a PCI initiator is performing a 3.3V/2.5V cycle to DRAM. AHOLD is held for the duration of the PCI burst transfer. The MTXC will negate AHOLD when the completion ...
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DRAM INTERFACE Name Type RAS[3:0]# O Row Address Strobe—RASx# (EDO/FPM). These pins select the DRAM row. or 3.3 V Chip Select—CSx# (SDRAM). These pins activate the SDRAMs. SDRAM accepts CS[3:0]#, any command when its CS# pin is ...
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Name Type CKEB/MAA1 O SDRAM Clock Enable (SDRAM) (second copy). SDRAM clock enable pin. When 3.3 V this signal is negated, SDRAM enters into power down mode. Note that this signal is not implemented in the “Suspend Well” and should ...
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SECONDARY CACHE INTERFACE Name Type CADV# O Cache Advance. Assertion causes the PBSRAM in the secondary cache to 3.3V advance to the next QWord in the cache line. CADS# O Cache Address Strobe. Assertion causes the PBSRAM ...
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PCI INTERFACE Name Type AD[31:0] I/O Address/Data. The standard PCI address and data lines. Address is driven with 3.3/5V FRAME# assertion, data is driven or received in following clocks. C/BE[3:0]# I/O Command/Byte Enable. The command is driven with FRAME# ...
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TEST AND CLOCK Name Type TEST# I Test In. NAND tree mode is activated by driving this pin low. The test mode selected 3.3/5V depends on the state of REQ[3:0]#. This pin should be pulled high with ...
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MTXC Strapping Options Name Type SCS A[31:30] Secondary Cache Size. Described in the Cache Control Register bits 7:6. L2RAMT A[29:28] Initial L2 RAM Type. Described in the Cache Control Register bits 5:4. DRAM KRQAK DRAM Cache L2 Present Upon ...
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NOTES: 1. KRQAK is not part of the suspend well. When this pin is used as the 5 considerations must be taken. 2.4. Power Sequencing Requirements The V 5REF signal must be tied system ...
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Signal States During And After A Hard Reset Table 2 shows the state of all the MTXC output and bi-directional signals when RST# is asserted. An undefined state means that the signal is driven either high or low, but ...
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REGISTER DESCRIPTION The MTXC contains two sets of software accessible registers (I/O Mapped and PCI configuration registers), accessed via the Host CPU I/O address space. The I/O mapped registers control access to PCI configuration space. Configuration registers ...
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PM2_CNTRL PM2 REGISTER BLOCK I/O Address: 0022h Default Value: 00h Access: Read/Write Bit 7:1 Reserved. 0 Arbiter Disable (ARB_DIS) When ARB_DIS=1, the MTXC does not respond to any REQ# signals (including PHOLD#) going active until this bit is set ...
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CONFDATA CONFIGURATION DATA REGISTER I/O Address: 0CFCh Default Value: 00000000h Access: Read/Write CONFDATA is a 32-bit read/write window into configuration space. The portion of configuration space that is referenced by CONFDATA is determined by the contents of ...
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Table 3. MTXC Configuration Space Address Register Offset Symbol 00 01h VID Vendor Identification 02 03h DID Device Identification 04 05h PCICMD PCI Command Register 06 07h PCISTS PCI Status Register 08 RID Revision Identification 09 0Bh CLASSC Class Code ...
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Table 3. MTXC Configuration Space Address Register Offset Symbol 69–6Ah Undefined 6B–6Fh Reserved 70h MTT Multi-Transaction Timer 71h ESMRAMC Extended System Management RAM Control 72h SMRAMC System Management RAM Control 73h Reserved 74h Undefined 76 78h Reserved 78h ...
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VID VENDOR IDENTIFICATION REGISTER Address Offset: 00–01h Default Value: 8086h Attribute: Read Only The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register ...
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Bit 2 Bus Master Enable (BME) (Not implemented) This bit is hardwired to 1. The MTXC does not support disabling of its bus master capability on the PCI Bus. 1 Memory Access Enable (MAE) When MAE=1, the MTXC ...
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RID REVISION IDENTIFICATION REGISTER Address Offset: 08h Default Value: 01h Access: Read Only This register contains the revision number of the MTXC. These bits are read only and writes to this register have no effect. Bit 7:0 Revision Identification ...
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HEDT HEADER TYPE REGISTER Address Offset: 0Eh Default Value: 00h Access: Read Only This register contains the Header Type of the MTXC. This code is 00h indicating that the MTXC’s configuration space map follows the basic format. ...
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PCON PCI CONTROL REGISTER Address Offset: 50h Default Value: 00h Access: Read/Write The PCON Register enables and disables features related to the PCI bus that are not already covered in the required PCI space. Bit 7:4 Reserved. 3 PCI ...
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Bit 5:4 L2 SRAM Type (L2SRAMT) This field reflects the inverted signal level on the A[29:28] pins at the rising edge of the RESET signal. The RESET values can be overwritten with subsequent writes to the CC Register. ...
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CEC EXTENDED CACHE CONTROL REGISTER Address Offset: 53h Default Value: 14h Access: Read/Write, Read Only This 8-bit register defines the refresh rate (in HCLKs) for a DRAM CACHE L2 cache implementation, if enabled. Bit 7:6 Reserved 5 DRAM CACHE ...
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Bit RAS# to CAS# Override (RCO) When set to 1, and the CL bit (CAS Latency (CAS 5 Latency=3), then a RAS# to CAS# delay of 2 HCLKs is provided for SDRAM. When set to 0, ...
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DRAMEC DRAM EXTENDED CONTROL REGISTER Address Offset: 56h Default Value: 52h Access: Read/Write This 8-bit register contains additional controls for main memory DRAM operating modes and features. Bit 7 Reserved. 6 Refresh RAS# Assertion(RRA). 1=5 clocks (RAS# asserted for ...
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DRAMC DRAM CONTROL REGISTER Address Offset: 57h Default Value: 01h Access: Read/Write This 8-bit register controls main memory DRAM operating modes and features. Bit 7:6 Hole Enable (HEN). This field enables a memory hole in DRAM space. ...
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DRAMT DRAM TIMING REGISTER Address Offset: 58h Default Value: 00h Access: Read/Write This 8-bit register controls main memory DRAM timings. For SDRAM specific timing control, see the SDRAMC timing register definition. Bit 7 Reserved. 6:5 DRAM Read Burst Timing ...
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Bit DRAM Leadoff Timing (DLT) The DRAM leadoff timings are controlled by the DLT bits. Slower 1:0 leadoffs may be required in certain system designs to support loose layouts or slower memories. The Row Miss leadoff timings are ...
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Read/Write Attribute Read Only Read cycles: CPU cycles are serviced by the DRAM in a normal manner. Write cycles: CPU initiated write cycles are ignored by the DRAM interface as well as the cache. Instead, the cycles are passed to ...
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After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Table 7. PAM Register and Associated Memory Segments PAM Reg. Attribute ...
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DOS Application Area (00000h–9FFFh) Read, write, and cacheability attributes are always enabled and are not programmable for the 0–640-Kbytes DOS application region. Video Buffer Area (A0000h–BFFFFh) This 128-Kbytes area is not controlled by attribute bits. CPU-initiated cycles in this region ...
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DRB DRAM ROW BOUNDARY REGISTERS Address Offset: 60–65h Default Value: 02h Access: Read/Write The MTXC supports 6 rows of DRAM. Each row is 64-bits wide. The DRAM Row Boundary Registers define upper and lower addresses for each ...
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RAS5# SIMM-5 Back RAS4# SIMM-5 Front RAS3# SIMM-3 Back RAS2# SIMM-3 Front RAS1# SIMM-1 Back RAS0# SIMM-1 Front CAS7# CAS5# CAS6# Figure 3. SIMMs and Corresponding DRB Registers The following 2 examples describe how the DRB Registers are programmed for ...
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DRTH DRAM ROW TYPE REGISTER HIGH Address Offset: 67h Default Value: S0000000 Access: Read/Write This 8-bit register identifies the type of DRAM (EDO, SPM (standard page mode)), or SDRAM (synchronous DRAM) used in rows 4 and 5 ...
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DRTL—DRAM ROW TYPE REGISTER LOW Address Offset: 68h Default Value: 00h Access: Read/Write This 8-bit register identifies the type of DRAM (EDO, SPM (standard page mode)), or SDRAM (synchronous DRAM) used in rows and should be ...
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ESMRAMC EXTENDED SYSTEM MANAGEMENT RAM CONTROL REGISTER Address Offset: 71h Default Value: 00h Access: Read/Write The Extended SMRAM register controls the configuration of Extended SMRAM space. MTXC supports two types of SMRAM memory: Compatible and Extended. The ...
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SMRAMC SYSTEM MANAGEMENT RAM CONTROL REGISTER Address Offset: 72h Default Value: 02h Access: Read/Write The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. MTXC supports two types of SMRAM memory: Compatible and Extended. The ...
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Table 8 summarizes the operation of SMRAM space cycles targeting the SMI space addresses. Table 8. SMRAM Space Cycles ...
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MCTL MISCELLANEOUS CONTROL REGISTER Address Offset: 79h Default Value: 00h Access: Read/Write Bit 7 Reserved. 6 ACPI Control Register Enable (ACRE) 0=Any CPU access to I/O address 0022h is passed on to the PCI bus. 1=Any CPU access to ...
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FUNCTIONAL DESCRIPTION 4.1. Host Interface The Host Interface of the MTXC is designed to support the Pentium microprocessor. The host interface of the MTXC supports 60-, and 66-MHz bus speeds. The Intel 430TX PCIset supports the Pentium ...
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Figure 4 and Figure 5 show the connections between the MTXC and the external tag RAM and data SRAM. MTXC 8Kx8 Tag RAM TIO[7:0] D[7:0] WE# TWE# OE# COE# CCS# CADS# CADV# GWE# BWE# Figure 4. MTXC Connections for 256K ...
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MTXC 16Kx8 Tag RAM D[7:0] TIO[7:0] WE# TWE# OE# COE# CCS# CADS# CADV# GWE# BWE# Figure 5. MTXC Connections for 512K Second Level Cache with PBSRAM 48 HA[18:5] HCLK 32Kx32 SRAM A[13:0] CLK HA[17:3] A[14:0] OE# CS1# ADSC# ...
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CLOCK LATENCIES Table 11 lists the latencies for various processor transfers to and from the second level cache. Table 11. Second Level Cache Latencies with Pipelined Burst SRAM Cycle Type Burst Read Burst Write (write back) Single Read Single ...
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DRAM CACHE SECOND LEVEL CACHE MODE DRAM Cache L2 cache implementation is similar to Pipelined Burst SRAM, except for the addition of the KRQAK bi-direct refresh handshake signal between the MTXC and L2 SRAM. A DRAM Cache ...
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Seven Programmable Attribute Map (PAM) Registers are used to specify the cacheability, PCI enable, and read/write status of the memory space between 640 Kbytes and 1 Mbytes. Each PAM Register defines a specific address area enabling the system to selectively ...
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HD[63:0] MD[63:0] RAS[3:0]# RAS[3:2]# RAS[1:0]# Host Data Bus Figure 6. FPM/EDO Four Row SIMM Configuration HD[63:0] MD[63:0] RAS/CS[3:0]# [3:2]# [1:0]# Host Data Bus NOTES configuration that supports suspend to RAM, only CKE is used. This ...
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Rules for Populating SIMM Modules (or x32 SO-DIMM modules) SIMM sockets can be populated in any order (i.e., memory for RAS0# does not have to be populated before memory for RAS[2:1]# or RAS[4:3]# are used). SIMM socket pairs (i.e., two, ...
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DRAM that can be implemented in the 5th row is limited (see the bullets below). The total memory supported is 256 MB, even though it is possible to populate ...
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Table 12. Minimum (Upgradeable) and Maximum Memory Size for each configuration (DRAM) DRAM DRAM DRAM DRAM SIMM Tech. Density Width SS x32 4M 512K 8 512K 16M ...
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The memory organization shown below represents the maximum 256 MB of address space. Accesses to memory space above Top-of-DRAM (< 256 MB), video buffer, or the memory gaps (if enabled) are forwarded to PCI, and these regions are ...
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DRAM ADDRESS TRANSLATION The multiplexed row/column address to the DRAM memory array is provided by the MA[11:0] signals (MA[13:0] for SDRAM 64-Mbit support). The MA bits are derived from the host or PCI address bus as defined by the ...
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Mobile PC’s. There are three grade parts defined for the 430TX. All of the speed grade conform to the SDRAM PC Specification. For information on the performance of each of the Speed grade parts, refer to ...
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AUTO DETECTION The SDRAM, FPM, and EDO detection is performed by BIOS. Note that when accessing any of the DRAM related registers (i.e., 54h–68h), refresh should be turned off via the DRAM Control register (DRAMC). 4.3.7. DRAM PERFORMANCE The ...
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Table 17. EDO/ Standard Page Mode Performance Summary (60 ns DRAMs) Processor Cycle Type (pipelined) Burst Read Page Hit 5-2-2-2 1 Read Row Miss 8-2-2-2 Read Page Miss 11-2-2-2 Back-to-Back Burst Reads Page Hit 5-2-2-2-3-2-2-2 Burst Read Page ...
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Table 18 lists the performance summary for SDRAM. The CL= 3 column represents a CAS latency of 3 part with a RAS to CAS (Trcd) of two clocks. The CL=2 column represents a CAS latency of two part. The performance ...
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DRAM REFRESH MTXC supports CAS-before-RAS# (CBR) refresh and Self refresh. The refresh rate is controlled via the DRAM Refresh Rate field in the DRAM Control Register (DRAMC). When a refresh request is generated placed in ...
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Mbytes. However once this is done, then SMI handlers execute at full processor performance. An error status bit is set in the Extended SMRAM Control register if the CPU tries to access the extended SMRAM space ...
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As with the Compatible SMRAM solution, MTXC does not claim any bus master access to the Extended SMRAM memory ranges defined above. The CPU can access these memory ranges by one of the following mechanisms: The processor generating ...
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The 430TX system maintains a very low power CPU complex by utilizing the different power down features available from the CPU, cache data RAMs and utilizing leading edge low power design techniques in the 430TX system components. The 430TX components ...
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CPU/L2 Interface Core Well MTXC PCI Interface Figure 9. MTXC Power Planes 4.6.2.1. Power Transition Changes The MTXC supports several suspend modes that support the PIIX4 system suspend states. Table 21 illustrates what suspend mode the MTXC enters ...
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PCI Interface The MTXC integrates a high performance interface to the PCI local bus taking full advantage of the high bandwidth and low latency of PCI. The MTXC is fully PCI 2.1 compliant. Table 22 lists the PCI bus ...
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System Arbitration The MTXC’s PCI Bus Arbiter allows PCI peer-to-peer traffic concurrent with CPU main memory/second level cache cycles. The arbiter supports five PCI masters. REQ[3:0]#/GNT[3:0]# are used by PCI masters other than the PCI-to-ISA expansion bridge ...
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CPU/PCI Priority Queue CPU PCI PCI PCI NOTES the PCI Priority Queue, the last agent granted is always dropped to the bottom of the queue for the next arbitration cycle, but the order of the chain is always ...
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Multi-Transaction Timer (MTT) The priority chain algorithm has been enhanced by the Multi-Transaction Timer (MTT) mechanism. Once a PCI agent is granted, the MTT is started. This timer then counts down in PCI clocks from its preset value ...
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PINOUT INFORMATION HD63 AD31 AD29 AD27 C/BE3# AD21 AD18 C/BE2# HD62 AD30 AD28 AD26 AD23 AD20 AD17 C/BE1# HD59 HD60 HD61 AD25 AD22 AD19 AD16 HD55 HD58 HD57 PHLD# PHLD- AD24 REQ0# ...
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Table 23. MTXC Alphabetical Table 23. MTXC Alphabetical Pin List Pin Ball A10 Y07 AD0 A11 W07 AD1 A12 U07 AD10 A13 Y06 AD11 A14 V06 AD12 A15 W06 AD13 A16 U06 AD14 A17 Y05 AD15 A18 W05 ...
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Table 23. MTXC Alphabetical Table 23. MTXC Alphabetical Pin List Pin Ball CAS6#/DQM6# P17 HD2 CAS7#/DQM7# T18 HD20 CCS# W13 HD21 CKE/MAA0 U20 HD22 CKEB/MAA1 W16 HD23 CLKRUN# C13 HD24 COE# V12 HD25 D/C# T07 HD26 DEVSEL# E09 HD27 EADS# ...
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Table 23. MTXC Alphabetical Table 23. MTXC Alphabetical Pin List Pin Ball M/IO# H05 MD23 MA0 V15 MD24 MA1 V16 MD25 MA10 U16 MD26 MA11/BA0 Y19 MD27 MA2 Y17 MD28 MA3 T14 MD29 MA4 U15 MD3 MA5 Y16 ...
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Table 23. MTXC Alphabetical Table 23. MTXC Alphabetical Pin List Pin Ball RAS3#/CS3# N17 TEST# RAS4#/CS4#/ V19 TIO0 BA1 TIO1 RAS5#/CS5#/ M16 MA13 TIO2 REQ0# D07 TIO3 REQ1# D09 TIO4 REQ2# D11 TIO5 REQ3# D13 TIO6 RST# T15 TIO7 SCASA# ...
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MTXC PACKAGE INFORMATION This specification outlines the mechanical dimensions for the MTXC. The package is a 324 pin ball grid array (BGA). TOP VIEW Pin #1 Corner Pin #1 I.D. f Figure 13. MTXC 324-pin Ball Grid ...
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Pin #1 Corner 324 Balls Matrix J I Figure 14. MTXC 324-pin Ball Grid Array (BGA) Ball Pattern PRELIMINARY ...
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Table 24. MTXC 324-pin Ball Grid Array (BGA) Symbol 1 Min A 1.95 A1 0.50 A2 1.12 D 26. 26. 1.44 REF. J 1.44 REF (Depopulated 324 b 0.60 ...
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TESTABILITY 8.1. NAND Tree Mode A NAND tree mode is provided for Automated Test Equipment (ATE) board level testing. The NAND tree allows the tester to set the connectivity of each of the MTXC’s signal pins. In Mobile/desktop mode, ...
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HCLK and PCLK need to run for a few clocks in the beginning to put the MTXC in the NAND chain mode. During the testing of chains 2 and 3, SUSSTAT# will be held high throughout the test. ...
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Table 27. Chain #1 (GNT#1) Table 27. Chain #1 (GNT#1) Pin Name Chain Element Pin Name A24 CH1_00 HD28 A27 CH1_01 HD21 A26 CH1_02 NA# A13 CH1_03 HD25 A8 CH1_04 BRDY# W/R# CH1_05 HD23 A11 CH1_06 HD35 A17 CH1_07 HD29 ...
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Table 28. Chain #2 (GNT#2) Pin Name Chain Element A28 CH2_00 CAS4# A29 CH2_01 SUSCLK A3 CH2_02 SRASA A30 CH2_03 MD11 A4 CH2_04 MD53 COE# CH2_05 SCASB# BWE# CH2_06 MD22 CCS# CH2_07 MD6 MA5 CH2_08 MD34 MA10 CH2_09 ...
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Table 29. Chain #3 (GNT#3) Table 29. Chain #3 (GNT#3) Pin Name Chain Element A22 CH3_00 CAS0# CADV# CH3_01 CAS2# A6 CH3_02 MWEB# TWE# CH3_03 RAS1# GWE# CH3_04 RAS3# CADS# CH3_05 RAS5# TIO1 CH3_06 SCASA TIO3 CH3_07 MD21 TIO7 CH3_08 ...