5962-9689601Q3A Cypress Semiconductor Corporation., 5962-9689601Q3A Datasheet
5962-9689601Q3A
Related parts for 5962-9689601Q3A
5962-9689601Q3A Summary of contents
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Features • Fibre-Channel-compliant • IBM ESCON -compliant • DVB-ASI-compliant • ATM-compliant • 8B/10B-coded or 10-bit unencoded • Standard HOTLink : 160–330 Mbps • High-speed HOTLink: 160–400 Mbps for high-speed applications • Low-speed HOTLink: 150–160 Mbps for low-cost fiber applications • ...
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HOST CY7B923 Transmitter Pin Configurations SOIC Top View OUTB 1 OUTC 2 OUTC CCN BISTEN 5 GND 6 MODE 7 7B923 CCQ SVS ...
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Pin Descriptions CY7B923 HOTLink Transmitter Name I/O Description D TTL In Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or on the next rising CKW ...
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CY7B923 HOTLink Transmitter (continued) Name I/O Description RP TTL Out Read Pulse 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X FIFOs. The frequency the same as CKW when enabled ...
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CY7B933 HOTLink Receiver (continued) Name I/O Description REFCLK TTL In Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL. REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream. REFCLK ...
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Unneeded outputs can be wired to VCC to disable and power down the unused output circuitry. Clock Generator The clock generator is an embedded phase-locked loop (PLL) that takes a byte-rate reference clock (CKW) ...
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Data is transferred to the Framer on each bit, and to the Decode register once per byte. Decode Register The Decode register accepts data from the Shifter once per byte as determined by the logic in the Clock Synchronization ...
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SERIAL DATA IN INX CKR Q0 7, DATA SC/D, RVS RDY RDY IS LOW FOR DATA Figure 2. CY7B933 Receiver Data Pipeline in Encoded Mode RF LATCHED ON FALLING EDGE OF CKR CKR SC/D, DATA DATA RVS ...
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Encoded Mode Operation In Encoded mode the input data is interpreted as eight bits of data (D0 – D7), a context control bit (SC/D), and a system diagnostic input bit (SVS). If the context of the data ...
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This automatic insertion of pad characters can be inhibited by insuring that the Transmitter is always ...
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Config MODE 25 FOTO 5 Control BISTEN 24 and ENN 23 Status ENA SC Data SVS 21 CKW 26 ...
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BIST LOOP Tx START ERROR BIST TEST LOOP START Rx BEGIN TEST BIST Mode BIST mode functions as follows: 1. Set BISTEN LOW to begin test pattern generation. Trans- mitter begins sending bit rate ...1010... 2. Set either ENA or ...
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BIST mode is intended to check the entire function of the Transmitter (except the Transmitter input pins and the bypass function in the Encoder), the serial link, and the Receiver. It augments normal factory ATE testing and provides the designer ...
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The framer function in Bypass mode is identical to Encoded mode K28.5 pattern can still be used to reframe the serial bit stream. Parallel Output Function The 10 outputs (Q , SC/D, and RVS) all transition simulta- 0-7 ...
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Receiver Test Mode Description The CY7B933 Receiver offers two types of test mode operation, BIST mode and Test mode normal system application, the Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the ...
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To clarify this correspondence, the following example shows the conversion from an FC-2 Valid Data Byte to a Transmission Character (using 8B/10B Transmission Code notation) FC-2 45 Bits: Converted to 8B/10B notation (note carefully that the order of bits is ...
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Otherwise, running disparity at the end of the ...
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Valid Data Characters (SC/D = LOW) Bits Current RD Data Byte EDC- Name HGF BA abcdei fghj D0.0 000 00000 100111 0100 D1.0 000 00001 011101 0100 D2.0 000 00010 101101 0100 D3.0 000 00011 110001 1011 D4.0 000 00100 ...
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Valid Data Characters (SC/D = LOW) Bits Current RD Data Byte EDC- Name HGF BA abcdei fghj D4.2 010 00100 110101 0101 D5.2 010 00101 101001 0101 D6.2 010 00110 011001 0101 D7.2 010 00111 111000 0101 D8.2 010 01000 ...
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Valid Data Characters (SC/D = LOW) Bits Current RD Data Byte EDC- Name HGF BA abcdei fghj D10.4 100 01010 010101 1101 D11.4 100 01011 110100 1101 D12.4 100 01100 001101 1101 D13.4 100 01101 101100 1101 D14.4 100 01110 ...
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Valid Data Characters (SC/D = LOW) Bits Current RD Data Byte EDC- Name HGF BA abcdei fghj D16.6 110 10000 011011 0110 D17.6 110 10001 100011 0110 D18.6 110 10010 010011 0110 D19.6 110 10011 110010 0110 D20.6 110 10100 ...
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Valid Special Character Codes and Sequences (SC/D = HIGH) S.C. Byte Name S.C. Code Name K28.0 C0.0 (C00) K28.1 C1.0 (C01) K28.2 C2.0 (C02) K28.3 C3.0 (C03) K28.4 C4.0 (C04) K28.5 C5.0 (C05) K28.6 C6.0 (C06) K28.7 C7.0 (C07) K23.7 ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ..................................–65°C to +150°C Ambient Temperature with Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage............................................ ...
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CY7B923/CY7B933 Electrical Characteristics Parameter Description Miscellaneous [11] I Transmitter Power Supply CCT Current [12] I Receiver Power Supply CCR Current [13] Capacitance Parameter Description C Input Capacitance IN AC Test Loads and Waveforms OUTPUT R 1= 910 ...
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Transmitter Switching Characteristics Parameter t Write Clock Cycle CKW [15] t Bit Time B t CKW Pulse Width HIGH CPWH t CKW Pulse Width LOW CPWL [16] t Data Set-Up Time SD [16] t Data Hold Time HD t Enable ...
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Receiver Switching Characteristics Parameter Description t REFCLK Clock Pulse HIGH CPXH t REFCLK Clock Pulse LOW CPXL t Propagation Delay (note PECL and TTL DS [26] thresholds) [13, 27] t Static Alignment SA [13, 28] t Error ...
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Switching W0aveforms for the CY7B933 HOTLink Receiver CKR RDY SC/D,RVS, REFCLK NOTE SO Static Alignment INA , INB SAMPLE WINDOW Document #: 38-02017 Rev. *C ...
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DATA LATCHED IN CKW ENA D0 7, SC/D, DATA SVS RP OUTX Ordering Information Speed Ordering Code Standard CY7B923-JC CY7B923-JI CY7B923-SC 400 CY7B923-400JC CY7B923-400JI 155 CY7B923-155JC CY7B923-155JI Standard CY7B933-JC CY7B933-JI CY7B933-SC 400 CY7B933-400JC CY7B933-400JI 155 CY7B933-155JC CY7B933-155JI Notes: 29. C1.7 ...
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Package Diagrams ESCON is a registered trademark of IBM. HOTLink is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-02017 Rev. *C © ...
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Document History Page Document Title: CY7B923/CY7B933 HOTLink Transmitter/Receiver Document Number: 38-02017 Issue REV ECN NO. Date ** 105855 03/28/01 *A 112164 03/25/02 *B 114562 03/27/02 *C 125525 04/01/03 Document #: 38-02017 Rev. *C Orig. of Change SZV Changed from Spec ...