5962-88637023A Cypress Semiconductor Corporation., 5962-88637023A Datasheet

5962-88637023A

Manufacturer Part Number

5962-88637023A

Description

SPLD, PLDC20G10 Family, ECMOS Process, 400 Gates, 10 Macro Cells, 10 Reg., 10 User I/Os, 5V Supply, 30 Speed Grade, 28LLCC

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.5962-88637023A.pdf (13 pages)

Current page: 1 of 13
Download datasheet (450Kb)

Cypress Semiconductor Corporation

Document #: 38-03010 Rev. **

Features

• Fast

• Low power

• Commercial and military temperature range

• User-programmable output cells

• Generic architecture to replace standard logic func-

• Eight product terms and one OE product term per out-

Note:

tions including: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10,

14L8, 16L6, 18L4, 20L2, and 20V8

put

— Commercial: t

— Military: t

— I

— Selectable for registered or combinatorial operation

— Output polarity control

— Output enable source selectable from pin 13 or prod-

The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts.

The difference is in the location of the “no connect” or NC pins.

uct term

Logic Block Diagram

Pin Configurations

I/OE

max.: 70 mA, commercial

max.: 100 mA, military

OUTPUT

I/O

12131415161718

= 20 ns, t

4 3 2

CELL

PLDC20G10B

PLDC20G10

Top View

LCC

= 15 ns, t

282726

OUTPUT

I/O

CELL

= 15 ns, t

20G10–2

I/O

= 10 ns, t

OUTPUT

I/O

CELL

•

= 15 ns

3901 North First Street

OUTPUT

I/O

CELL

= 12 ns

121314 1516 1718

4 3 2

OUTPUT

I/O

PLDC20G10B

PLDC20G10

CELL

STD PLCC

PROGRAMMABLE

Top View

ANDARRAY

2827 26

Reprogrammable Logic Device

Functional Description

Cypress PLD devices are high-speed electrically programma-

ble logic devices. These devices utilize the sum-of-products

(AND-OR) structure providing users the ability to program cus-

tom logic functions for unique requirements.

In an unprogrammed state the AND gates are connected via

EPROM cells to both the true and complement of every input.

By selectively programming the EPROM cells, AND gates may

be connected to either the true or complement or disconnected

from both true and complement inputs.

OUTPUT

• CMOS EPROM technology for reprogrammability

• Highly reliable

I/O

CELL

— Uses proven EPROM technology

— Fully AC and DC tested

— Security feature prevents logic pattern duplication

— 10% power supply voltage and higher noise immu-

nity

•

I/O

OUTPUT

20G10–4

I/O

San Jose

PLDC20G10B/PLDC20G10

CELL

CMOS Generic 24-Pin

OUTPUT

I/O

CELL

•

121314 1516 1718

4 3 2

JEDEC PLCC

CA 95134

CG7C323B–A

CG7C323–A

OUTPUT

I/O

Top View

CELL

2827 26

Revised March 26, 1997

OUTPUT

I/O

CELL

[1]

•

I/O

408-943-2600

20G10–1

20G10–3

CP/I

Related parts for 5962-88637023A

5962-88637023A Summary of contents

Page 1

Features • Fast — Commercial ns — Military ns ns • Low power — I max.: 70 mA, commercial CC — I max.: 100 mA, ...

Selection Guide I (mA) CC Generic Part Number Com/Ind 20G10B–15 70 20G10B–20 70 20G10B–25 20G10–25 55 20G10–30 20G10–35 55 20G10–40 Functional Description (continued) Cypress PLDC20G10 uses an advanced 0.8-micron CMOS technology and a proven EPROM cell as the programmable element. ...

Page 3

Programmable Output Cell Configuration Table Figure ...

Page 4

Registered Output Configurations 20G10–6 Figure 1. Product Term OE/Active LOW 20G10–8 Figure 3. Pin 13 OE/Active LOW Combinatorial Output Configurations 20G10–10 Figure 5. Product Term OE/Active LOW 20G10–12 PIN 13 Figure 7. ...

Page 5

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. – +150 C Ambient Temperature with Power Applied............................................. – +125 C Supply Voltage to Ground Potential ............... ...

Page 6

AC Test Loads and Waveforms (Commercial) R1 238 (319 MIL) 5V OUTPUT 50pF INCLUDING JIG AND SCOPE (a) Equivalent to: THÉVENIN EQUIVALENT (Commercial) 99 OUTPUT 2.08V=V Switching Characteristics Over Operating Range Parameter Description t Input or Feedback to Non-Registered Output ...

Page 7

Switching Characteristics Over Operating Range Parameter Description t Input or Feedback to Non-Registered Output PD t Input to Output Enable EA t Input to Output Disable ER t Pin 11 to Output Enable PZX t Pin 11 to Output PXZ ...

Page 8

Functional Logic Diagram • • • • • • • • • • • • • • • ...

Page 9

Ordering Information (ns) (ns) (ns) (mA) Ordering Code PLDC20G10B–15PC PLDC20G10B–15WC 100 PLDC20G10B–20DMB PLDC20G10–25JC PLDC20G10–25PC/PI PLDC20G10–25WC PLDC20G10–30DMB PLDC20G10–30LMB ...

Page 10

Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL–STD–1835 D– 9Config.A 28-Square Leadless Chip Carrier L64 MIL–STD–1835 C–4 Document #: 38-03010 Rev. ** PLDC20G10B/PLDC20G10 28-Lead Plastic Leaded Chip Carrier J64 Page ...

Page 11

Package Diagrams (continued) Document #: 38-03010 Rev. ** 28-Pin Windowed Leaded Chip Carrier H64 PLDC20G10B/PLDC20G10 Page ...

Page 12

Package Diagrams (continued) Document #: 38-03010 Rev. ** 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead (300-Mil) Windowed CerDIP W14 MIL–STD–1835 D– 9Config.A PLDC20G10B/PLDC20G10 Page ...

Page 13

Document Title: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Document Number: 38-03010 REV. ECN NO. Issue Date ** 106292 04/25/01 Document #: 38-03010 Rev. ** © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. ...

Related keywords

5962-88637023A datasheet
5962-88637023A data sheet
5962-88637023A pdf datasheet
5962-88637023A component
5962-88637023A part
5962-88637023A distributor
5962-88637023A RoHS
5962-88637023A datasheet download