AD830ANZ Analog Devices Inc, AD830ANZ Datasheet - Page 13

• Manufacturer Part Number: AD830ANZ
• Description: IC VIDEO DIFF AMP HS 8-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD830ANZ

• Slew Rate: 360 V/µs
• Applications: Differential
• Number Of Circuits: 1
• -3db Bandwidth: 85MHz
• Current - Supply: 14.5mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): 8 V ~ 33 V, ±4 V ~ 16.5 V
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Gain Bandwidth: 85MHz
• Supply Voltage Range: ± 4V To ± 16.5V
• No. Of Amplifiers: 1
• Output Current: 40mA
• Amplifier Output: Single Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Choice of Polarity
The sign of the gain is easily selected by choosing the polarity
of the connections to the + and − inputs of the X G
Swapping between inverting and noninverting gain is possible
simply by reversing the input connections. The response of the
amplifier is identical in either connection, except for the sign
change.
The bandwidth, high impedance, and transient behavior of the
AD830 is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
The relatively high input impedance of the AD830, for a
differential receiver amplifier, permits connections to modest
impedance sources without much loading or loss of common-
mode rejection. The nominal input resistance is 300 kΩ. The
real limit to the upper value of the source resistance is in its
effect on common-mode rejection and bandwidth. If the source
resistance is in only one input, then the low frequency
common-mode rejection is lowered to ≈ R
resistance/input capacitance pole limits the bandwidth. Refer to
the following equation:
Furthermore, the high frequency common-mode rejection is
additionally lowered by the difference in the frequency response
caused by the R
and high frequency common-mode rejection, it is recommended
that the source resistances of the + and − inputs be matched and
of modest value (≤10 kΩ).
Handling Bias Currents
The bias currents are typically 4 μA flowing into each pin of the
G
finite source resistance, the bias current through this resistor
creates a voltage drop (I
impedance of the AD830 permits modest values of R
≤10 kΩ. If the source resistance is in only one terminal, then an
objectionable offset voltage may result, for example, 4 μA × 5
kΩ = 20 mV. Placement of an equal value resistor in series with
the other input cancels the offset to first order. However, due to
M
stages of the AD830. Because all applications possess some
⎛
⎜
⎝
100
0%
f
90
10
=
2
1
π
×
R
S
1V
× C
S
×
C
Figure 30. Clipping Behavior
IN
IN
pole. Therefore, to maintain good low
⎞
⎟
⎠
BIAS
× R
S
). The relatively high input
1V
IN
/R
S
. The source
M
stage.
S
, typically
Rev. C | Page 13 of 20
mismatches in the resistances, a residual offset remains and is
likely to be greater than the bias current (offset current)
mismatches.
Applying Fee
The AD830 is intended
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 40) with gain >1.
The value of the bottom resistor, R
1 kΩ to ensure that the pole formed by C
connection of R
it does not introduce excessive phase shift around the loop and
destabilize the amplifier. A compensating resistor, equal to the
parallel combination of R
with the other Y G
common-mode rejection and to lower the offset voltage
induced by the input bias current.
Output Common Mode
The output swing of the AD
input voltage, the gain, and the output common. Depending o
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output volta
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus the supply is
shown in Figure 31. A prediction of the common-mode rang
versus the peak output differential voltage can be easily derived
from the maximum output swing as V
Output Cur
The absolute peak
current limiting, typically greater than 60 mA. The maximum
drive capability is rated at 50 mA but without a guarantee of
distortion performance. Best distortion performance is obtained
by keeping the output current ≤20 mA. Attempting to drive
large voltages into low valued resistances, for example, 10 V i
150 Ω causes an apparent lowering of the limit for output signal
swing but is just the current limiting behavior.
15
12
9
6
3
0
0
rent
Figure 31. Maximum Output Swing vs. Supply
dback
1
and R
4
M
output current is set by the short-circuit
stage input to preserve the high frequenc
2
for use with gains from 1 to 100. Gains
is sufficiently high in frequency so t
SUPPLY VOLTAGE (V)
1
and R
8
830 is defined by the differential
V
P
2
, should be placed in series
2
, should be kept less than
12
OCM
IN
V
= V
N
and the parallel
MAX
16
− V
PEAK
AD830
20
.
hat
e
nto
y
ge
n