HDMP-1685A Agilent Technologies, Inc., HDMP-1685A Datasheet
HDMP-1685A
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HDMP-1685A Summary of contents
Page 1
... TC to latch TX [0:3] [0:4] data into the input register of the transmitter section. This timing scheme assumes that the driving ASIC and HDMP-1685A operate in the same clock domain. 8B/10B encoded data comes in 10-bit characters. This data is latched onto the 5 TX pins of each channel in 5-bit groups ...
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... Other encoding schemes will also work as long as they provide dc bal- ance and sufficient number of transitions. In order to accom- plish this task, the HDMP-1685A incorporates the following: • SSTL_2 Parallel Data I/O • High-Speed Phase Locked Loops • Parallel-to-Serial Converters • ...
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... SSTL_2 COMPATIBILITY HDMP-1685A works with proto- col devices whose VDDQ voltage is nominally set at 2.5 Volts. RX [0:3][0:4], RC [0:3][0:1] pins generate output voltages that are compatible with the SSTL_2 standard (EIA/JESD8-9) ...
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... Figure 1. Typical application of the four channel SERDES. FRAME TX(0:3)[0:4] TX PLL CLOCK TC GENERATOR CAP0 CAP1 RFCT RC(0:3)[0:1] SYNC SYN(0:3) FRAME DEMUX RX(0:3)[0:4] BYTE SYNC Figure 2. Block diagram of HDMP-1685A. 4 4-CHANNEL ASIC HDMP-1685A OUTPUT MUX SELECT TX CLOCKS INPUT SELECT RX PLL CLOCK RECOVERY RX CLOCKS AND INPUT SAMPLER SO[0:3]± ...
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... Agilent‘s HDMP-1685A internally generates another clock which is 90 degrees out of phase with the TC clock supplied. This clock, which will have its edges at the center of the data valid eye, is used to clock in the TX[0:4] data. Setup and hold times are taken care of by the HDMP-1685A provided the specifications indicated are met ...
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... HDMP-1685A Timing Characteristics – Receiver Sections – Rising Edge Clocking 3. 3. Symbol Parameter f_lock Frequency Lock at Powerup [1,2] B_sync Bit Sync Time t RX [0:3][0:4] Setup Time (Data Valid Before Clock) RXS t RX [0:3][0:4] Hold Time (Data Valid After Clock) ...
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... HDMP-1685A Timing Characteristics – Receiver Sections – Rising and Falling Edge Clocking 3. 3. Symbol Parameter f_lock Frequency Lock at Powerup [1,2] B_sync Bit Sync Time t RX [0:3][0:4] Setup Time (Data Valid Before Clock) RXS t RX [0:3][0:4] Hold Time (Data Valid After Clock) ...
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... 3. 3. Parallel Clock Rate (MHz) Serial Baud Rate (MBaud) Min. Max. Min. 124.0 126.0 1240 HDMP-1685A Reference Clock and Transmit Byte Clock Requirements 3. 3. Symbol Parameter f Nominal Frequency F Frequency Tolerance ...
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... HDMP-1685A SSTL_2 I/O DC Electrical Parameters 3. 3.45 V, VDDQ = 2. 2.70 V. VDDQ is the FC-1/MAC device I/O supply voltage SSTL-2 inputs can receive LVTTL signals successfully. SSTL-2 outputs do not output LVTTL compliant levels. Symbol Parameter VREFT SSTL_2 Input Reference Voltage V Input High Voltage ...
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... D 10 DIVIDE BY 10 CIRCUIT CH2 SOi– VARIABLE DELAY PLUP B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD = –1 PRBS Pattern for these devices is 36 C/W for the HDMP-1685A. ja Units Typ 70841B A 70311A PATTERN CLOCK SOURCE GENERATOR +K28.5, -K28.5 + DATA - DATA 1 ...
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... O-SSTL2 Output SSTL_2 HS_OUT 50 matched Output Driver. Will drive AC coupled 50 HS_IN PECL level compatible. Must be AC coupled (Figure 10). C External Circuit Node S Power Supply or Ground HDMP-1685A Pin Input Capacitance (TRx) Symbol Parameter C Input Capacitance on SSTL input pins INPUT I_TTL ...
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... THE CONFIGURATION ABOVE. VREFR SHOULD BE BYPASSED WITH 0.1 µF IN THIS CASE. IF USED, R SHOULD BE 500-1000 . 1% RESISTORS SHOULD BE USED FOR R ABOVE, VREFT TO THE MAC SHOULD BE SET TO 1.25 V NOMINAL. USING THIS VALUE CENTERS VREFR RELATIVE TO THE RX[0:3][0:4] OUTPUT SWINGS PROVIDED BY THE HDMP-1685A. Figure 11. O-SSTL_2 and I-SSTL_2 simplified circuit schematic. 01 ...
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... F* 0.1 F VCR V GND CC VCR GND VCR GND VCR GND GND 0 PLACEMENT NOT CRITICAL – INDICATES NEED FOR LOW-FREQUENCY BYPASS CAPACITANCE HDMP-1685A 0.1 F GND GND GND GND GND GND VCP GND VCP GND V A GND VCP CC V GND GND CC 0.1 F ...
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... HDMP-1685A TRx I/O Definition Name Pin Type Signal CAP0 P09 C Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected across the CAP0 and CAP1 pins. (typical value = 0.1 F) CAP1 R09 PLUP N14 I-SSTL2 Parallel Loopback Enable Input: When set high, a high-speed serial signal from the transmitter section’ ...
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... L16 TX32 L15 TX33 L14 TX34 M17 VREFT P01 I-S TX Parallel Interface SSTL_2 Reference Voltage: Voltage reference derived from 2 resistor network with V VREFR D07 O-S RX Parallel Interface SSTL_2 Reference Voltage: Provided by HDMP-1685A. Drives the VREF input of the ASIC. 15 (ASIC) as supply, as recommended in Figure 11. DDQ ...
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... HDMP-1685A TRx I/O Definition, continued Name Pin Type Signal V A02 S Power Supply: Normally 3.3 volts. Used for logic, SSTL inputs, and LVTTL I/O. CC A10 C14 G04 J14 K16 L04 N15 R04 R14 R16 T03 T04 T14 U05 VCCA T09 S Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the PLLs and high-speed analog cells ...
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... HDMP-1685A TRx I/O Definition, continued Name Pin Type Signal GND A01 S Logic Ground: Normally 0 volts. All GND pads on the chip are connected to one A03 ground slug in the package, which then distributes these to GND balls. A11 A15 A17 B04 B09 C07 C16 D04 ...
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... HDMP-1685A TRx I/O Definition, continued Name Pin Type Signal NC A08 These pins are connected to an isolated pad and have no functionality. A14 They may be left open, or LVTTL levels may be applied. B01 B02 B03 B08 B13 B14 C02 C03 C08 C09 C13 D08 D09 ...
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Package Drawing Nx0b eee CORNER [–Y–] E TOLERANCE OF FORM AND POSITION SYMBOL ddd eee 19 O (4x (CAVITY DOWN) (BACKFILL) ...
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... Data subject to change. Copyright © 2001 Agilent Technologies, Inc. May 7, 2001 Obsoletes 5988-1304EN 5988-2143EN ...