K8D1716UBC-PI07 Samsung, K8D1716UBC-PI07 Datasheet
K8D1716UBC-PI07
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K8D1716UBC-PI07 Summary of contents
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... K8D1716UTC / K8D1716UBC Document Title 16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory Revision History Revision No. History 0.0 Initial Draft 0.1 Support 48TSOP1 Lead Free Package 0.2 Support 48FBGA Leaded/Lead Free Package 1.0 Specification finalized FLASH MEMORY Draft Date July 25, 2004 Sep 16, 2004 Nov 29, 2004 Dec 16, 2004 ...
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... K8D1716UTC / K8D1716UBC 16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory FEATURES • Single Voltage, 2.7V to 3.6V for Read and Write operations • Organization 1,048,576 x 16 bit (Word mode) • Fast Read Access Time : 70ns • Read While Program/Erase Operation • Dual Bank architectures Bank 1 / Bank 2 : 8Mb / 8Mb • ...
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... K8D1716UTC / K8D1716UBC 48 Ball FBGA TOP VIEW (BALL DOWN FUNCTIONAL BLOCK DIAGRAM Bank1 Vcc Address Vss CE OE I/O WE Interface & BYTE Bank RESET Control RY/BY Bank2 WP/ACC Address A0~A19 DQ15/A-1 DQ0~DQ14 RY/ A13 WP/ A4 A17 A8 A12 ...
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... K8D1716UTC / K8D1716UBC ORDERING INFORMATION Samsung NOR Flash Memory Device Type Dual Bank Boot Block Bank Division 17 = 8Mbits + 8Mbits Organization x16 Operating Voltage Range 2.7V to 3.6V Table 1. PRODUCT LINE-UP Part No. Vcc Max. Address Access Time (ns) Max. CE Access Time (ns) Max ...
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... K8D1716UTC / K8D1716UBC Table 3. Top Boot Block Address (K8D1716UT K8D1716UT A19 A18 A17 Block BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 Bank1 BA27 BA26 BA25 ...
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... K8D1716UTC / K8D1716UBC Table 5. Bottom Boot Block Address (K8D1716UB K8D1716UT A19 A18 A17 Block BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 Bank2 BA30 BA29 BA28 BA27 BA26 BA25 ...
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... K8D1716UTC / K8D1716UBC PRODUCT INTRODUCTION The K8D1716U is a 16Mbit (16,777,216 bits) NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flex- ible erase and program capability, the device adapts a block memory architecture that divides its memory array into 39 blocks (64- Kbyte 8-Kbyte x 8) ...
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... K8D1716UTC / K8D1716UBC COMMAND DEFINITIONS The K8D1716U operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg- ister. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode ...
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... K8D1716UTC / K8D1716UBC Notes : Read Address Program Address Read Data Program Data DA : Dual Bank Address Block Address (A12 - A19 Don’t care . 2. To terminate the Autoselect Mode necessary to write Reset command to the register. 3. The 4th cycle data of Autoselect mode is output data. ...
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... K8D1716UTC / K8D1716UBC DEVICE OPERATION Byte/Word Mode If the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" , the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB (A-1) address pin ...
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... K8D1716UTC / K8D1716UBC A9 A6,A1,A0* DQ15-DQ0 Note : The addresses other than and A6 are Don′t care. Please refer to Table 9 for device code. Figure 2. Autoselect Operation ( by high voltage method ) WE ∼ A19 A0(x16)/* 555H/ 2AAH/ ∼ 555H A19 A-1(x8) AAAH ∼ DQ15 DQ0 AAH Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 9 for device code. ...
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... K8D1716UTC / K8D1716UBC Unlock Bypass The K8D1716U provides the unlock bypass mode to save its program time for program operation. The mode is invoked by the unlock bypass command sequence. Then, the unlock bypass program command sequence is required to program the device. Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles ...
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... K8D1716UTC / K8D1716UBC WE ∼ A19 A0(x16)/ 555H/ 2AAH/ AAAH 555H ∼ A19 A-1(x8) DQ15-DQ0 AAH RY/BY Figure 6. Block Erase Command Sequence Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Sus- pend command is only valid during the Block Erase operation including the time window of 50µ ...
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... K8D1716UTC / K8D1716UBC Read While Write The K8D1716U provides dual bank memory architecture that divides the memory array into two banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with dual bank architecture ...
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... K8D1716UTC / K8D1716UBC Block Protect Algorithm Set up Block Group address Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 150µs Verify Block Group Protect:Write 40H to Block Group address with A6=0, Increment A1=1,A0=0 COUNT Read from Block Group address with A6=0, A1=1,A0 COUNT Data=01h? ...
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... K8D1716UTC / K8D1716UBC Table 10. Block Group Address (Top Boot Block) Block Group A19 A18 BGA0 0 0 BGA1 0 0 BGA2 0 0 BGA3 0 1 BGA4 0 1 BGA5 1 0 BGA6 1 0 BGA7 BGA8 BGA9 1 1 BGA10 1 1 BGA11 1 1 BGA12 1 1 BGA13 ...
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... K8D1716UTC / K8D1716UBC Table 11. Block Group Address (Bottom Boot Block) Block Group A19 A18 BGA0 0 0 BGA1 0 0 BGA2 0 0 BGA3 0 0 BGA4 0 0 BGA5 0 0 BGA6 0 0 BGA7 0 0 BGA8 0 0 BGA9 0 0 BGA10 0 1 BGA11 0 1 BGA12 1 0 BGA13 1 0 BGA14 ...
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... K8D1716UTC / K8D1716UBC Temporary Block Group Unprotect The protected blocks of the K8D1716U can be temporarily unprotected by applying high voltage (V pin. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When the RESET pin goes high (RESET = V ), all the previously protected blocks will be protected again. If the WP/ACC pin is asserted the two outermost boot blocks remain protected ...
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... K8D1716UTC / K8D1716UBC Accelerated Program Operation Accelerated program operation reduces the program time. This is one of two functions provided by the WP/ACC pin. When the WP/ ACC pin is asserted the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any HH protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode ...
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... K8D1716UTC / K8D1716UBC Table 12. Common Flash Memory Interface Code Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max ...
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... K8D1716UTC / K8D1716UBC Table 12. Common Flash Memory Interface Code Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1- Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported Read Only Read & Write ...
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... K8D1716UTC / K8D1716UBC DEVICE STATUS FLAGS The K8D1716U has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as follows : Table 13 ...
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... K8D1716UTC / K8D1716UBC DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time win- dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed ...
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... K8D1716UTC / K8D1716UBC Start Read(DQ0~DQ7) Valid Address DQ7 = Data ? No No DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address DQ7 = Data ? No Fail Figure 11. Data Polling Algorithms Notes : 1. All protected block groups are unprotected WP/ACC = V 2. All previously protected block groups are protected once again. Start Read(DQ0~DQ7) ...
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... K8D1716UTC / K8D1716UBC ABSOLUTE MAXIMUM RATINGS Parameter Vcc A9 RESET Voltage on any pin relative WP/ACC All Other Pins Commercial Temperature Under Bias Industrial Storage Temperature Short Circuit Output Current Operating Temperature Notes : 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods < ...
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... K8D1716UTC / K8D1716UBC Parameter Symbol Voltage for Autoselect and V ID Block Protect (4) Output Low Level V OL Output High Level V OH Low Vcc Lock-out Voltage (5) V LKO Notes : 1. The I current listed includes both the DC operating current and the frequency dependent component(at 5 MHz). CC The read current is typically VCC=3. VIH.) 2 ...
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... K8D1716UTC / K8D1716UBC AC CHARACTERISTICS Write(Erase/Program)Operations Alternate WE Controlled Write Parameter Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Read (1) Enable Toggle and Data Polling (1) Hold Time CE Setup Time CE Hold Time Write Pulse Width ...
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... K8D1716UTC / K8D1716UBC AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CE Controlled Writes Parameter Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Read (1) Enable Toggle and Data Polling (1) Hold Time WE Setup Time WE Hold Time CE Pulse Width ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Read Operations Address HIGH-Z Outputs HIGH RY/BY Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time CE & OE Disable Time (1) Output Hold Time from Address Hold Time Note : 1. Not 100% tested. ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Hardware Reset/Read Operations Address RESET High-Z Outputs Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold Time from Address RESET Pulse Width RESET High Time Before Read t RC Address Stable ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Alternate WE Controlled Program Operations 555H Address CE t OES WPH A0H DATA t DS RY/BY Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Alternate CE Controlled Program Operations 555H Address WE t OES A0H DATA t DS RY/BY Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device Program Address Program Data 4 ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Word to Byte Timing Diagram for Read Operation CE OE BYTE t ELFL DQ0-DQ7 DQ8-DQ14 DQ15/A-1 Byte to Word Timing Diagram for Read Operation CE OE BYTE t ELFH DQ0-DQ7 DQ8-DQ14 DQ15/A-1 BYTE Timing Diagram for Write Operation CE WE BYTE Parameter Chip Enable Access Time ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Chip/Block Erase Operations t AS 555H 2AAH Address CE t OES WPH AAH DATA t DS RY/BY Vcc t VCS Note : BA : Block Address Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Read While Write Operations Read Command DA2 Address DA1 (555H OES Valid Valid DQ Output Input (A0H) Note : This is an example in the program-case of the Read While Write function. DA1 : Address of Bank1, DA2 : Address of Bank 2 ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Data Polling During Internal Routine Operation OEH2 WE Data In DQ7 DQ0-DQ6 Data In Note : *DQ7=Vaild Data (The device has completed the internal operation). RY/BY Timing Diagram During Program/Erase Operation CE WE RY/BY Parameter Program/Erase Valid to RY/BY Delay Chip Enable Access Time Output Enable Time CE & ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation Address OEH2 Data In DQ6/DQ2 RY/BY Note : Address for the write operation must include a bank address (A19) where the data is written. Enter Embedded Erase Erasing Suspend Erase Toggle ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS RESET Timing Diagram High RY/ RESET RY/ RESET Power-up and RESET Timing Diagram RESET Vcc Address DATA Parameter RESET Pulse Width RESET Low to Valid Data (During Internal Routine) RESET Low to Valid Data (Not during Internal Routine) RESET High Time Before Read ...
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... K8D1716UTC / K8D1716UBC SWITCHING WAVEFORMS Block Group Protect & Unprotect Operations RESET BGA,A6 A1,A0 Block Group Protect / Unprotect DATA 60H 1µ RY/BY Notes : Block Group Protect (A6= Block Group Unprotect (A6= BGA = Block Group Address (A12 ~ A19) Temporary Block Group Unprotect RESET ...
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... K8D1716UTC / K8D1716UBC PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8’C 0.45~0.75 0.018~0.030 20.00 ±0.20 0.787 ±0.008 #48 #25 18.40 ±0.10 0.724 ±0.004 0.50 ( 0.020 40 FLASH MEMORY Unit :mm/Inch 1.00 0.05 ±0.05 MIN 0.039 0.002 ±0.002 1.20 MAX 0.047 ) Revision 1.0 ...
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... K8D1716UTC / K8D1716UBC PACKAGE DIMENSIONS 48-Ball Fine Ball Grid Array Package (measured in millimeters) Top View 6.00 ±0.10 #A1 0.08MAX FLASH MEMORY Bottom View 6.00 ±0.10 0.80 x 5=4. (Datum A) 0.80 A (Datum 48- ∅ 0.45 ±0.05 ∅ 0. 2.00 Side View 0.45 ±0.05 8.50 ±0. Revision 1.0 ...