SAB88C166-5M Siemens Semiconductor Group, SAB88C166-5M Datasheet
SAB88C166-5M
Related parts for SAB88C166-5M
SAB88C166-5M Summary of contents
Page 1
Microcomputer Components 16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM SAB 88C166/88C166W Data Sheet 05.94 ...
Page 2
C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary SAB 88C166(W) 16-Bit Microcontrollers with 32 KByte Flash EPROM High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 Enhanced Boolean Bit ...
Page 3
Introduction The SAB 88C166 and the SAB 88C166W are members of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. They combine high CPU performance ( million instructions per second) with high peripheral functionality, enhanced IO-capabilities ...
Page 4
Pin Configuration Rectangular P-MQFP-100 (top view Figure 2 Semiconductor Group SAB 88C166(W) 3 SAB 88C166(W) ...
Page 5
Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) P4.0 – I/O P4 XTAL1 20 I XTAL2 19 O BUSACT EBC1 EBC0 ...
Page 6
Pin Definitions and Functions (cont’d) Symbol Pin Input (I) Number Output (O) NMI 29 I ALE P1.0 – I/O P1. P5.0 – 48 – P5.9 56 – ...
Page 7
Pin Definitions and Functions (cont’d) Symbol Pin Input (I) Number Output (O) P3.0 – 80 – 92, I/O P3.15 95 – ...
Page 8
Pin Definitions and Functions (cont’d) Symbol Pin Input (I) Number Output ( 18 38, 61 39, 60, 78, 94 Functional Description This document only describes specific properties of the ...
Page 9
Memory Organization The memory space of the SAB 88C166(W) is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 256 KBytes. Address ...
Page 10
H 3 3’0000 H 2 2’0000 H 1 1’0000 H 0 0’0000 H Memory Segments Figure 3 Flash Memory Overview The Flash Control Register (FCR) In standard operation mode the Flash memory can be accessed like the normal mask- ...
Page 11
FCR (FFA0 / FWM - - - - SET Bit Function FWE Flash Write Enable Bit (see description below Flash write operations (program / ...
Page 12
The selection of Flash Operation and Read Mode is done via the three bits FWE, FEE and FWMSET. The table below shows the combinations for these bits to select a specific function: FWMSET FEE FWE ...
Page 13
In order not to exceed the limit values listed above, a specific CKCTL setting requires a minimum CPU clock frequency, as listed below. Setting of Length of CKCTL TPRG 1/f CPU ...
Page 14
Operation Modes of the Flash Memory There are two basic operation modes for Flash accesses: The standard and the writing mode. Sub- modes of the writing mode are the programming, the erase and the non-verify mode. Figure 4 Flash Operating ...
Page 15
After entering writing mode the first erase or programming operation must not be started for at least 10 s. This absolute (!) delay time is required to set up the internal high voltage. In general, Flash write operations need a ...
Page 16
In Flash Programming Mode (FEE=’0’, FWE=’1’) the SAB 88C166(W) is prepared to program Flash locations in the way specified by the Word or Double Word Write (WDWW) bit in the FCR. The width of the programming pulses generated internally is ...
Page 17
Flash Protection If active, Flash protection prevents data operand accesses and program branches into the on-chip Flash area from any location outside the Flash memory itself. Data operand accesses and branches to Flash locations are exclusively allowed for instructions executed ...
Page 18
Flash Programming Algorithm The figure below shows the recommended Flash programming algorithm. The following example describes this algorithm in detail. Figure 5 Flash Programming Algorithm Semiconductor Group 17 SAB 88C166(W) ...
Page 19
Flash Programming Example This example describes the Flash programming algorithm. A source block of code and/or data within the first 32 Kbytes of segment 0 is copied (programmed target block within the Flash memory, which is mapped to ...
Page 20
Enter writing mode via unlock sequence (prerequisite for any programming or erase operation). MOV FCR MOV [ CALL cc_UC, WAIT_10 Program the FCR register with a value that selects the desired operating mode. Note ...
Page 21
Load source values and initialize loop counter (PCOUNT) with the maximum number of programming trials (PNmax performed before exiting the routine with a failure. Each trial means applying a pulse of 100 s to the selected words in ...
Page 22
Perform Program-Verify operation and compare with source data in order to check whether a programming operation was performed correctly. PVM reading consists of two identical Flash read instructions with 4 s delay in between. This example uses CMP instructions to ...
Page 23
Flash Erase Algorithm The figure below shows the recommended Flash erase algorithm. The following example describes this algorithm in detail. Figure 7 Flash Erase Algorithm Semiconductor Group 22 SAB 88C166(W) ...
Page 24
Flash Erase Example This example describes the Flash erase algorithm. The four banks of the Flash memory can be erased separately. The algorithm erases the Flash memory bank, which is selected by bitfield BE in the FCR. Start address and ...
Page 25
Enter writing mode via unlock sequence (prerequisite for any programming or erase operation). MOV FCR MOV [ CALL cc_UC, WAIT_10 Program the FCR register with a value that selects erase mode. Note that this ...
Page 26
WAIT_ERASE: MOV R15, DPP1: pof FCR JB R15.2, WAIT_ERASE … Verify V validity during erasing to make sure V PP erase operation. Otherwise erasing may have not been performed properly. The FCVPP flag is set to ‘1’ in case of ...
Page 27
Fundamentals of Flash Technology The Flash memory included in the SAB 88C166(W) combines the EPROM programming mechanism with electrical erasability (like an EEPROM) to create a highly reliable and cost effective memory. A Flash memory cell consists of a single ...
Page 28
To avoid this possible malfunction, the user must equalize the amount of charge on each cell by programming all cells of one block to ‘0’ before performing a block erasure. Figure 10 Flash Memory Cell Erase Mechanism The introduced erase ...
Page 29
Absolute Maximum Ratings Ambient temperature under bias ( SAB 88C166(W)-5M ....................................................................................................... ˚C T Storage temperature ( ) ....................................................................................... – 125 ˚ Voltage on pins with respect to ground ( CC Voltage ...
Page 30
DC Characteristics ˚C for SAB 88C166(W)-5M A Parameter Input low voltage EBC1/V PP Input low voltage (all except EBC1 Input ...
Page 31
Parameter Power-down mode supply current V read current PP V writing current PP V during write/read PP Notes 1) This specification does not apply to the analog input (Port 5.x) which is currently converted. 2) The maximum current may be ...
Page 32
Figure 12 Supply/Idle Current as a Function of Operating Frequency Semiconductor Group SAB 88C166(W) I CCmax I IDmax 20 f [MHz] CPU ...
Page 33
A/D Converter Characteristics ˚C for SAB 88C166(W)- 4 0.1 V; AREF CC Parameter Analog input voltage range ...
Page 34
Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at Figure 13 Input Output Waveforms For timing purposes a port pin is no ...
Page 35
AC Characteristics The specification of the timings depends on the CPU clock signal that is used in the respective device. In this regard the specification for the SAB 88C166 and the SAB 88C166W are different. While the SAB 88C166W directly ...
Page 36
AC Characteristics (cont’d) External Clock Drive XTAL1 for the SAB 88C166W ˚C for SAB 88C166W-M A Parameter Symbol Oscillator period CLPSR High ...
Page 37
AC Characteristics (cont’d) Multiplexed Bus for the SAB 88C166 ˚C for SAB 88C166- (for Port 0, Port 1, Port 4, ...
Page 38
Parameter ALE rising edge after RD, WR Address hold after RD, WR Semiconductor Group Symbol Max. CPU Clock = 20 MHz min. max – – ...
Page 39
AC Characteristics (cont’d) Multiplexed Bus for the SAB 88C166W ˚C for SAB 88C166W (for Port 0, Port 1, Port 4, ...
Page 40
Parameter Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR Semiconductor Group Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max 47 ...
Page 41
ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS RD Write Cycle BUS WR Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group Address t 7 Address t 10 ...
Page 42
ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS RD Write Cycle BUS WR Figure 18 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group Address t 7 Address t 10 ...
Page 43
ALE A17-A16 (A15-A8) BHE t Read Cycle BUS RD Write Cycle BUS WR Figure 19 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group Address Address t 9 ...
Page 44
ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS RD Write Cycle BUS WR Figure 20 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group Address t 7 Address t t ...
Page 45
AC Characteristics (cont’d) Demultiplexed Bus for the SAB 88C166 ˚C for SAB 88C166- (for Port 0, Port 1, Port 4, ...
Page 46
AC Characteristics (cont’d) Demultiplexed Bus for the SAB 88C166W ˚C for SAB 88C166W (for Port 0, Port 1, Port 4, ...
Page 47
Parameter ALE rising edge after RD, WR Address hold after RD, WR Semiconductor Group Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max – – ...
Page 48
ALE A17-A16 A15-A0 BHE t Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 21 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group Address 6 t ...
Page 49
ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 22 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group Address t ...
Page 50
ALE A17-A16 A15-A0 BHE t Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 23 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group Address 6 t ...
Page 51
ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 24 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group Address t ...
Page 52
AC Characteristics (cont’d) CLKOUT and READY for SAB 88C166 ˚C for SAB 88C166- (for Port 0, Port 1, Port 4, ...
Page 53
AC Characteristics (cont’d) CLKOUT and READY for SAB 88C166W ˚C for SAB 88C166W (for Port 0, Port 1, Port 4, ...
Page 54
Running cycle t 32 CLKOUT ALE Command RD, WR Sync READY Async 3) READY Figure 25 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). ...
Page 55
AC Characteristics (cont’d) External Bus Arbitration ˚C for SAB 88C166(W)- (for Port 0, Port 1, Port 4, ALE, RD, WR, ...
Page 56
CLKOUT t 61 HOLD HLDA 1) BREQ Other Signals Figure 26 External Bus Arbitration, Releasing the Bus Notes 1) The SAB 88C166(W) will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for ...
Page 57
CLKOUT HOLD HLDA t 62 BREQ Other Signals Figure 27 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated ...
Page 58
Figure 28 Package Outline Rectangular P-MQFP100 Semiconductor Group Min Typ Max A 3.30 A2 2.55 2.80 3.05 0.100 0.110 0.120 D 23.65 23.90 24.15 0.931 0.941 0.951 D1 19.90 20.00 20.10 0.783 0.787 0.791 D3 18.85 E ...