MPC99J93 Motorola, MPC99J93 Datasheet

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MPC99J93

Manufacturer Part Number
MPC99J93
Description
Manufacturer
Motorola
Datasheet

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MOTOROLA TIMING SOLUTIONS
SEMICONDUCTOR TECHNICAL DATA
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Intelligent Dynamic Clock
Switch (IDCS) PLL Clock
Driver
dant clock tree designs. The device receives two differential LVPECL
clock signals from which it generates 5 new differential LVPECL clock
outputs. Two of the output pairs regenerate the input signals frequency
and phase while the other three pairs generate 2x, phase aligned clock
outputs.
Features:
Functional Description
of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary
clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase
disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E Motorola Inc. 2003
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3V Operation
32--Lead LQFP Packaging
The MPC99J93 is a PLL clock driver designed specifically for redun-
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection
Man_Override
Clk_Selected
Alarm_Reset
Inp1bad
Inp0bad
PLL_En
Sel_Clk
Ext_FB
Ext_FB
CLK0
CLK0
CLK1
CLK1
Dynamic Switch
MR
Logic
Freescale Semiconductor, Inc.
OR
For More Information On This Product,
Go to: www.freescale.com
Figure 1. Block Diagram
200 -- 360 MHz
PLL
÷2
÷4
MPC99J93
32--LEAD LQFP PACKAGE
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
CASE 873A
FA SUFFIX
Order Number: MPC99J93/D
Rev 1, 08/2003
1

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MPC99J93 Summary of contents

Page 1

... LQFP Packaging Functional Description The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance ...

Page 2

... Digital power supply GNDA Power Supply PLL ground GND Power Supply Digital ground MPC99J93 Figure 2. 32- -Lead Pinout (Top View) Pin Definition For More Information On This Product, Go to: www.freescale.com 17 16 VCC ...

Page 3

... AN1545 for more information). The device AC and DC parameters are speci- fied up to 110°C junction temperature allowing the MPC99J93 to be used in applications requiring industrial temperature range recom- mended that users of the MPC99J93 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application ...

Page 4

... Freescale Semiconductor, Inc. MPC99J93 Table 4. DC CHARACTERISTICS (V Symbol Characteristics LVCMOS control inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset) V Input High Voltage IH V Input Low Voltage Input Current IN LVCMOS control outputs (Clk_selected, Inp0bad, Inp1bad) V Output High Voltage OH V Output Low Voltage OL LVPECL clock inputs (CLK0, CLK1, Ext_FB) ...

Page 5

... V -1.7 CC within QA[2:0] or QB[1:0] within device f QA[1:0] f QB[2:0] g QA[1:0] g QB[2:0] 45 RMS (1 σ) 0. (AC) specification. Violation CMR For More Information On This Product, Go to: www.freescale.com MPC99J93 Typ Max Unit Condition 90 MHz PLL locked 360 MHz 90 MHz PLL locked 180 MHz 75 % +0.17 ns PLL_EN=1 1.8 ns PLL_EN=0 1 -0.3 ...

Page 6

... The resistor will have minimal impact on the rise and fall times of the input signals. Acquiring Frequency Lock 1. While the MPC99J93 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. ...

Page 7

... C A-- SECTION 0.25 GAUGE PLANE L θ _ For More Information On This Product, Go to: www.freescale.com MPC99J93 e DETAIL G NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND DETERMINED AT SEATING PLANE C ...

Page 8

... Minami--Azabu, Minato--ku, Tokyo 106--8573, Japan 81--3--3440--3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852--26668334 HOME PAGE: http://motorola.com/semiconductors ◊ For More Information On This Product, Go to: www.freescale.com MOTOROLA TIMING SOLUTIONS MPC99J93/D ...

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