MCM63P631TQ4.5 Motorola, MCM63P631TQ4.5 Datasheet

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MCM63P631TQ4.5

Manufacturer Part Number
MCM63P631TQ4.5
Description
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
64K x 32 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
a burstable, high performance, secondary cache for the 68K Family, PowerPC ,
and Pentium
This device integrates input registers, an output register, a 2–bit address counter,
and high speed SRAM onto a single monolithic circuit for reduced parts count in
cache data RAM applications. Synchronous design allows precise cycle control
with the use of an external clock (K). CMOS circuitry reduces the overall power
consumption of the integrated functions for greater reliability.
enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-
trolled through positive–edge–triggered noninverting registers.
addresses can be generated internally by the MCM63P631 (burst sequence op-
erates in linear or interleaved mode dependent upon state of LBO) and controlled
by the burst address advance (ADV) input pin.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
nous write enable SW are provided to allow writes to either individual bytes or to
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
are LVTTL compatible.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA FAST SRAM
REV 3
8/4/97
The MCM63P631 is a 2M bit synchronous fast static RAM designed to provide
Addresses (SA), data inputs (DQx), and all control signals except output
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
Write cycles are internally self–timed and are initiated by the rising edge of the
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
For read cycles, pipelined SRAMs output data is temporarily stored by an
The MCM63P631 operates from a 3.3 V power supply, all inputs and outputs
Motorola, Inc. 1997
MCM63P631–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
MCM63P631–4.5 = 4.5 ns access / 10 ns cycle (100 MHz)
MCM63P631–7 = 7 ns access / 13.3 ns cycle (75 MHz)
MCM63P631–8 = 8 ns access / 15 ns cycle (66 MHz)
Single 3.3 V + 10%, – 5% Power Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
Sleep Mode (ZZ)
PB1 Version 2.0 Compatible
Single–Cycle Deselect Timing
JEDEC Standard 100–Pin TQFP Package
microprocessors. It is organized as 64K words of 32 bits each.
MCM63P631
Order this document
CASE 983A–01
TQ PACKAGE
by MCM63P631/D
MCM63P631
TQFP
1

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MCM63P631TQ4.5 Summary of contents

Page 1

... The PowerPC name is a trademark of IBM Corp., used under license therefrom. Pentium is a trademark of Intel Corp. This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 3 8/4/97 MOTOROLA FAST SRAM Motorola, Inc. 1997 Order this document by MCM63P631/D MCM63P631 TQ PACKAGE TQFP CASE 983A– ...

Page 2

... MCM63P631 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 16 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c WRITE REGISTER ENABLE ENABLE REGISTER REGISTER 2 16 64K x 32 ARRAY DATA–IN DATA–OUT REGISTER REGISTER K DQa – DQd MOTOROLA FAST SRAM ...

Page 3

... DQd DQd 22 DQd 23 DQd 24 DQd DQd 28 29 DQd MOTOROLA FAST SRAM PIN ASSIGNMENT DQb 78 DQb ...

Page 4

... When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation Supply Power Supply: 3 10%, – 5 Supply Ground. NC — No Connection: There is no connection to the chip. Description MOTOROLA FAST SRAM ...

Page 5

... On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. This READ assumes the RAM was previously deselected. MOTOROLA FAST SRAM SE2 SE3 ...

Page 6

... SBa 4th Address (Internal X11 X00 X01 X10 4th Address (Internal X11 X10 X01 X00 SBb SBc SBd MOTOROLA FAST SRAM ...

Page 7

... Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MOTOROLA FAST SRAM Value Unit Notes – ...

Page 8

... TBD — — 145 — — 115 — — 105 — — TBD — — 65 — — 50 — — 50 — — 0.4 V 2.4 — — V Min Typ Max Unit — — MOTOROLA FAST SRAM ...

Page 9

... All read and write cycle timings are referenced from don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 5. This parameter is sampled and is not 100% tested. 6. Measured at 200 mV from steady state. MOTOROLA FAST SRAM 1.5 V Output Timing Reference Level 0 to 3.0 V Output Load ...

Page 10

... MCM63P631 10 MOTOROLA FAST SRAM ...

Page 11

... MOTOROLA FAST SRAM É É É É É É É É É É É É É É ...

Page 12

... CONTROL PIN TIE VALUES Non–Burst Sync Non–Burst, Pipelined SRAM NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low ADSP ADSC ADV SE1 LBO MOTOROLA FAST SRAM ...

Page 13

... K ADDR DQx Q(A) READS Figure 2. Configured as Non–Burst Pipelined Synchronous SRAM MOTOROLA FAST SRAM D Q(B) Q(C) Q( D(E) D(F) D(G) D(H) WRITES MCM63P631 13 ...

Page 14

... Part Number Full Part Numbers — MCM63P631TQ117 MCM63P631 14 ORDERING INFORMATION (Order by Full Part Number) MCM 63P631 Blank = Trays Tape and Reel Speed (117 = 117 MHz, 4.5 = 4 ns) Package (TQ = TQFP) MCM63P631TQ4.5 MCM63P631TQ117R MCM63P631TQ4.5R MCM63P631TQ7 MCM63P631TQ8 MCM63P631TQ7R MCM63P631TQ8R MOTOROLA FAST SRAM ...

Page 15

... D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQ PACKAGE TQFP CASE 983A– TIPS 0.20 (0.008) C A–B D –D– E/2 –B– E1 D/2 ...

Page 16

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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