AM5X86 Advanced Micro Devices, AM5X86 Datasheet
AM5X86
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... SMM. Table 1 shows available processors in the Am5 86 microprocessor family. X This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Complete 32-Bit Architecture — ...
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AMD BLOCK DIAGRAM 2 PRELIMINARY Am5 86 Microprocessor X ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. – 133 A D AMD-X5 Valid Combinations OPN Package Type AMD-X5-133ADW ...
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AMD Table of Contents 1 Connection Diagrams and Pin Designations ......................................................................................... 8 1.1 168-Pin PGA (Pin Grid Array) Package .......................................................................................... 8 1.2 168-Pin PGA Designations (Functional Grouping) ......................................................................... 9 1.3 208-Pin SQFP (Shrink Quad Flat Pack) Package ........................................................................ 10 1.4 ...
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BOFF During Write-Back ..................................................................................................... 32 4.8.10 Snooping Characteristics During a Cache Line Fill ........................................................... 32 4.8.11 Snooping Characteristics During a Copy-Back ................................................................. 32 4.9 Cache Invalidation and Flushing in Write-Back mode .................................................................. 33 4.9.1 Cache Invalidation through Software .................................................................................. ...
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AMD 8 Test Registers 4 and 5 Modifications .................................................................................................. 53 8.1 TR4 Definition ................................................................................................................................ 53 8.2 TR5 Definition ................................................................................................................................ 54 8.3 Using TR4 and TR5 for Cache Testing.......................................................................................... 55 8.3.1 Example 1: Reading the Cache (Write-back mode only) ..................................................... 55 ...
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Figure 30 SMM Base Slot Offset ............................................................................................................. 48 Figure 31 SRAM Usage .......................................................................................................................... 48 Figure 32 SMRAM Location .................................................................................................................... 49 Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM.......................................................................................... 50 Figure ...
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AMD 1 CONNECTION DIAGRAMS AND PIN DESIGNATIONS 1.1 168-pin PGA (Pin Grid Array) Package D20 D19 D11 D22 D21 D18 D13 TCK V CLK D17 D10 SS 3 ...
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PGA Designations (Functional Grouping) Address Data Pin Pin Pin Pin Name No. Name No. A2 Q-14 D0 P-1 A3 R-15 D1 N-2 A4 S-16 D2 N-1 A5 Q-12 D3 H-2 A6 S-15 D4 M-3 A7 Q-13 D5 J-2 ...
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AMD 1.3 208-pin SQFP (Shrink Quad Flat Pack) Package 10 PRELIMINARY TOP VIEW Am5 86 Microprocessor X ...
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SQFP Designations (Functional Grouping) Address Data Pin Name Pin Pin Name No. A2 202 D0 144 A3 197 D1 143 A4 196 D2 142 A5 195 D3 141 A6 193 D4 140 A7 192 D5 130 A8 190 ...
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AMD 2 LOGIC SYMBOL CLK Clock STPCLK Stop Clock CLKMUL Clock Multiplier A20M Address Mask Upgrade UP Present VOLDET Voltage Detect A31–A4 28 A3–A2 2 Address Bus BE3–BE0 4 BS8 BS16 Bus Cycle ADS Control RDY M/IO D/C Bus Cycle ...
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PIN DESCRIPTIONS The Am5 86 microprocessor provides the complete in- X terface support offered by the Enhanced Am486 micro- processor family products. The CLKMUL pin settings have changed to accommodate the higher operating speed selection. A20M Address Bit 20 ...
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AMD BS8/BS16 Bus Size 8 (Active Low; Input)/ Bus Size 16 (Active Low; Input) The BS8 and BS16 signals allow the processor to op- erate with 8-bit and 16-bit I/O devices by running multiple bus cycles to respond to data ...
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FERR Floating-Point Error (Active Low; Output) Driven active when a floating-point error occurs, FERR is similar to the ERROR pin on a 387 math coprocessor. FERR is included for compatibility with systems using DOS-type floating-point error reporting. FERR is active ...
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AMD LOCK Bus Lock (Active Low; Output) A Low output on this pin indicates that the current bus cycle is locked. The microprocessor ignores HOLD when LOCK is asserted (although it does acknowledge AHOLD and BOFF). LOCK goes active in ...
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When the CPU recognizes SMI, it enters SMM before execut- ing the next instruction and saves internal registers in SMM space. SMIACT SMM Interrupt Active (Active Low; Output) SMIACT goes Low in ...
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AMD 4 FUNCTIONAL DESCRIPTION 4.1 Overview Am5 86 microprocessors use a 32-bit architecture with X on-chip memory management and cache memory units. The instruction set includes the complete 486 micropro- cessor instruction set along with extensions to serve the new ...
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Write-Back Cache Protocol The Am5 86 microprocessor family write-back cache X coherency protocol reduces bus activity ...
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AMD Table 5. MESI Cache Line Status Situation Modified Exclusive Shared Line valid? Yes Yes Yes External out-of- memory valid valid date is... goes to A write to does not does not go the bus this cache go to the ...
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If the PWT signal is 0, the external WB/WT signal de- termines the new state of the line. If the WB/WT signal was asserted to 1 during reload, the line transits to the exclusive state. If the WB/WT signal was ...
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AMD 4.8.2.2 HOLD Bus Arbitration Implementation The HOLD/HLDA bus arbitration scheme is used prima- rily in systems where all memory transfers are seen by the microprocessor. The HOLD/HLDA bus arbitration scheme permits simple write-back cache design while maintaining a relatively ...
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CLK ADR M/IO W/R 1 ADS BLAST BRDY Data KEN WB/WT BOFF Note: The circled numbers in this figure represent the steps in section 4.8.2.2.2. CLK ADR M/IO W/R 1 ADS BLAST BRDY Data WB/WT BOFF Note: The circled numbers ...
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AMD CLK ADR INV EADS HITM HOLD HLDA Note: The circled numbers in this figure represent the steps in section 4.8.3.1. Figure 6. Snoop of On-Chip Cache That Does Not Hit a Line CLK ADR INV EADS HITM HOLD HLDA ...
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External Bus Master Snooping Actions The following scenarios describe the snooping actions of an external bus master. 4.8.3.1 Snoop Miss Scenario : A snoop of the on-chip cache does not hit a line, as shown in Figure 6. Step ...
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AMD Step 3 Two clock cycles after EADS is asserted, HITM becomes valid, and is 0 because the line is mod- ified. Step 4 In the next clock, the core system logic deas- serts the HOLD signal in response to ...
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Step 1 HOLD places the microprocessor in Snooping mode. HLDA must be High for a minimum of one clock cycle before EADS assertion. In the fastest case, this means that HOLD asserts one clock cycle before the HLDA response. Step ...
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AMD Step 1 During a snoop to the on-chip cache that hits a modified cache line, the HOLD signal cannot be deasserted to the microprocessor until the next clock cycle after HITM transitions active. Step 2 After the write-back has ...
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CLK ADR from CPU M/IO CACHE W/R 1 ADS BLAST BRDY AHOLD 2 INV EADS HITM Data Note: The circled numbers in this figure represent the steps in section 4.8.5.3. Figure 12. Snoop Hit Cycle with Write-Back Step 8 As ...
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AMD CLK ADR R1 from CPU W1 to CPU M/IO CACHE W/R ADS BLAST BRDY BOFF AHOLD INV EADS HITM Data Note: The circled numbers in this figure represent the steps in section 4.8.6. Figure 13. Cycle Reordering with BOFF ...
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CLK 2 XXX A Write Buffer B original Cached Data AHOLD 1 EADS HITM ADS BLAST BRDY Data Note: The circled numbers in this figure represent the steps in section 4.8.7.1. Figure 14. Write Cycle Reordering Due to Buffering Step ...
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AMD 4.8.7.2 BOFF Write-Back Arbitration Implementation The use of BOFF to perform snooping of the on-chip cache is used in systems where more than one cache- able bus master resides on the microprocessor bus. The BOFF signal forces the microprocessor ...
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CLK ADR n AHOLD EADS CACHE HITM ADS BRDY BLAST 4.9 Cache Invalidation and Flushing in Write-Back Mode The Am5 86 microprocessor family supports cache in- X validation and flushing, much like the Am486 micropro- cessor Write-through mode. However, the ...
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AMD Table 8. FLUSH Special Bus Cycles A32–A2 M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle 0000 0001h 0000 0001h 4.9.3 Snooping During Cache Flushing As with snooping during ...
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CLK ADR XX0 M/IO W/R CACHE ADS BLAST BRDY BOFF Data XX0 XX4 from CPU Figure 18. Burst Write with BOFF Assertion CACHE is asserted for cacheable reads, cacheable code fetches, and write-backs/copy-backs. CACHE is deasserted for non-cacheable reads, translation ...
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AMD 4.10.3 PLOCK Operation in Write-Through Mode As described in Section 3, PLOCK is only used in Write- through mode; the signal is driven inactive in Write-back mode. In Write-through mode, the processor drives PLOCK Low to indicate that the ...
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CLK STPCLK ADDR RDY 5.4 Pin State During Stop Grant Table 9 shows the pin states during Stop Grant Bus states. During the Stop Grant state, most output and input/output signals of the microprocessor maintain ...
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AMD (valid for Write-back mode only) CLK STPCLK Sampled STPCLK NMI SMI Note Earliest time at which NMI or SMI is recognized. Figure 21. Recognition of Inputs when Exiting Stop Grant State A RESET or SRESET brings the ...
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The Am5 86 CPU product family requires INTR held active until the CPU issues an interrupt acknowl- edge cycle to guarantee recognition. This condition also applies to the existing Am486 CPUs. In the Stop Grant state, the ...
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AMD Dedicated and secure memory space (SMRAM) for SMI handler code and CPU state (context) data with a status signal for the system to decode access to that memory space, SMIACT Resume (RSM) instruction, for exiting SMM Special features, such ...
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SMIACT } CPU SMI Figure 23. Basic SMI Hardware Interface For uses such as fast enabling of external I/O devices, the SMSAVE mode permits the restarting of the I/O in- structions and the HALT instruction. This is accom- plished through ...
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AMD T1 T2 CLK CLK2 SMI ADS RDY SMIACT A: Last RDY from non-SMM transfer to SMIACT assertion B: SMIACT assertion to first ADS for SMM state save C: SMM state save (dependent on memory performance) D: SMI handler E: ...
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SMRAM State Save Map When SMI is recognized on an instruction boundary, the CPU core first sets the SMIACT signal Low, indicating to the system logic that accesses are now being made to the system-defined SMRAM areas. The CPU ...
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AMD 7.4 Entering System Management Mode SMM is one of the major operating modes, along with Protected mode, Real mode, and Virtual mode. Figure 27 shows how the processor can enter SMM from any of the three modes and then ...
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Table 11. SMM Initial CPU Core Register Settings Register SMM Initial State General Purpose Unmodified Registers EFLAGS 0000 0002h CR0 Bits and 31 cleared (PE, EM, TS, and PG); rest unmodified DR6 Unpredictable state DR7 0000 0400h ...
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AMD 7.7.1 Exceptions and Interrupts with System Management Mode When the CPU enters SMM, it disables INTR interrupts, debug, and single step traps by clearing the EFLAGS, DR6, and DR7 registers. This prevents a debug appli- cation from accidentally breaking ...
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Auto HALT Restart The Auto HALT Restart slot at register offset (word lo- cation) 7F02h in SMRAM indicates to the SMI handler that the SMI interrupted the CPU during a HALT state; bit 0 of slot 7F02h is set ...
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AMD If an SMI occurs and it does not trap an I/O instruction, the contents of the I/O address and R/W bit are unpre- dictable and should not be used. 7.7.6 SMM Base Relocation The Am5 86 CPU family provides ...
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Normal SMRAM memory Normal memory Normal memory Non-overlaid Overlaid (no need to flush (caches must caches) be flushed) Figure 32. SMRAM Location The recommended configuration is to use a separate (non-overlaid) physical address for SMRAM. This non- overlaid scheme prevents ...
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AMD State Save SMI SMIACT Figure 33. SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM State Save SMI SMIACT WB/WT Note: For proper operation of systems configured in Write-back mode when caching ...
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SMI State Save Instruction x SMI SMIACT FLUSH Cache contents invalidated Figure 36. SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM SMI State Save Instruction x SMI SMIACT FLUSH Cache contents invalidated ...
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AMD 7.8.4 CPU Reset During SMM The system designer should take into account the fol- lowing restrictions while implementing the CPU Reset logic: 1. When running software written for the 80286 CPU, a CPU RESET switches the CPU from Protected ...
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If the offset of the interrupted procedure is greater than 64 Kbytes not possi- ble for the interrupt/exception handler to return con- trol to that procedure. (One work-around is to perform software adjustment of ...
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AMD STn (bits 30–29): Read Only, available only in Write- back mode when Ext=1 in TR5. STn returns the sta- tus of the set (ST3, ST2, ST1, or ST0) specified by the TR5 Set State field (bits 18–17) during cache ...
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Control (bits 1–0): Read/Write, independent of Write- through or Write-back mode. The control bits deter- mine which operation to perform. The following is a definition of the control operations: — Write to cache fill buffer, or read from ...
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AMD 10 Am5 86 CPU IDENTIFICATION X The Am5 86 microprocessor supports two standard X methods for identifying the CPU in a system. The re- ported values are assigned based on the RESET status of the WB/WT pin input (Low ...
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Electrical Data The following sections describe recommended electri- cal connections for the Am5 86 microprocessors and X electrical specifications. 11.1 Power and Grounding 11.1.1 Power Connections Am5 86 microprocessors with 16 Kbytes of cache have X modest power requirements. ...
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AMD ABSOLUTE MAXIMUM RATINGS Case Temperature under Bias . . . – 65°C to +110°C Storage Temperature . . . . . . . . . . – 65°C to +150°C Voltage on any pin with respect to ground . ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges The AC specifications, provided in the AC characteris- tics table, consist of output delays, input setup require- ments, and input hold requirements. All AC specifica- tions are relative to the rising edge of the ...
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AMD Am5 86 Microprocessor AC Characteristics for X Boundary Scan Test Signals at 25 MHz V = 3.3 V ±0 0°C to +85° CASE Symbol Parameter t TCK Frequency 24 t TCK Period 25 t ...
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PRELIMINARY Key to Switching Waveforms Waveform Inputs Must be steady May change from May change from Don’t care; any change permitted Does not apply Figure 39. CLK Waveforms Figure 40. Output Valid Delay Timing ...
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AMD 62 PRELIMINARY Figure 41. Maximum Float Delay Timing Figure 42. PCHK Valid Delay Timing Am5 86 Microprocessor X ...
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PRELIMINARY Figure 43. Input Setup and Hold Timing Figure 44. RDY and BRDY Input Setup and Hold Timing Am5 86 Microprocessor X AMD 63 ...
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AMD 64 PRELIMINARY Figure 45. TCK Waveforms Figure 46. Test Signal Timing Diagram Am5 86 Microprocessor X ...
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PACKAGE THERMAL SPECIFICATIONS The Am5 86 microprocessor is specified for operation X when T (the case temperature) is within the range CASE + + can be measured in CASE any environment ...
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AMD 13 PHYSICAL DIMENSIONS Index Corner 1.595 1.605 1.735 1.765 Bottom View (Pins Facing Up) Notes: 1. All measurements are in inches. 2. Not to scale. For reference only. 3. BSC is an ANSI standard for Basic Space Centering. 66 ...
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... Trademarks AMD, Am386, and Am486 are registered trademarks and Am5 FusionPC is a service mark of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...