82541 Intel Corporation, 82541 Datasheet
82541
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82541 Summary of contents
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... Family of Gigabit Ethernet Controllers Networking Silicon - 82541(PI/GI/EI) Product Features PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — CLK_RUN# signal — 3 tolerant PCI signaling) MAC Specific — Low-latency transmit and receive queues — ...
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... The 82541 Family of Gigabit Ethernet Controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Voltage, Temperature, and Timing Specifications............................................................19 4.1 Absolute Maximum Ratings.................................................................................19 4.2 Targeted Recommended Operating Conditions..................................................19 4.2.1 General Operating Conditions................................................................19 4.2.2 Voltage Ramp and Sequencing Recommendations...............................20 4.3 DC Specifications ................................................................................................22 4.4 AC Characteristics...............................................................................................25 4.5 Timing Specifications ..........................................................................................27 5.0 Package and Pinout Information ......................................................................................33 5.1 Package Information ...........................................................................................33 5.2 Thermal Specifications ........................................................................................35 5.3 Pinout Information ...............................................................................................36 Networking Silicon — 82541(PI/GI/EI) iii ...
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... Networking Silicon 5.4 Visual Pin Assignments....................................................................................... 46 Figures 1 82541(PI/GI/EI) External Architecture Block Diagram ........................................ 11 2 Internal Architecture Block Diagram.................................................................... Test Loads for General Output Pins.............................................................. Test Loads for General Output Pins.............................................................. Test Loads for General Output Pins.............................................................. Test Loads for General Output Pins.............................................................. 29 7 TVAL (max) Rising Edge Test Load ...
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... LED Signals.........................................................................................................37 24 Other Signals.......................................................................................................38 25 IEEE Test Signals ...............................................................................................38 26 PHY Signals ........................................................................................................38 27 Test Interface Signals..........................................................................................38 28 Digital Power Signals ..........................................................................................38 29 Analog Power Signals .........................................................................................39 30 Grounds and No Connect Signals.......................................................................39 31 Voltage Regulation Control Signals.....................................................................39 32 Signal Names in Pin Order..................................................................................40 Networking Silicon — 82541(PI/GI/EI) v ...
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... Networking Silicon Note: This page is intentionally blank. vi ...
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... TCP/UDP/IP checksum calculations and TCP segmentation. The 82541(PI/GI/EI) is packaged 196-ball grid array and is pin compatible with the 82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller, 82562EZ(EX) Platform LAN Connect devices, and the 82540EP(EM) Gigabit Ethernet Controller. ...
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... PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group (SIG). Software driver developers should contact their local Intel representatives for programming information. 1.3 Product Codes The product ordering codes for the 82541 Family of Gigabit Ethernet Controllers: • GD82541PI • GD82541GI • ...
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... Architectural Overview 2.1 External Architecture Block Diagram The 82541(PI/GI/EI) architecture is a derivative of the 82542, 82543, and 82544 designs that provided Media Access Controller (MAC) functionality as well as an integrated 10/100/1000Mbps copper PHY. The 82541(PI/GI/EI) family architecture now adds SMBus-based manageability and an integrated ASF controller functionality to the MAC. ...
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... MAC control registers, is used to configure and monitor the PHY operation. 2.4 System Interface 82541(PI/GI/EI) provides a 32-bit PCI 2.2 bus interface which is capable MHz operation in conventional PCI mode. In conventional PCI systems with a dedicated I/O bus per connector, this interface should provide sufficient bandwidth to support a sustained 1000 Mb/sec transfer rate ...
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... Power. Power connection, voltage reference, or other reference connection. 3.2 PCI Bus Interface Signals (56) When the Reset signal (RST#) is asserted, the 82541(PI/GI/EI) will not drive any PCI output or bi- directional pins. The Power Management Event signal (PME#) can be active by configuring manageability functions. Networking Silicon — 82541(PI/GI/EI) ...
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... TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. When the 82541(PI/GI/EI) controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases. ...
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... Grant Bus. The Grant Bus signal notifies the 82541(PI/GI/EI) that bus access has been granted. This is a point-to-point signal. Name and Function Interrupt A. Interrupt A is used to request an interrupt of the 82541(PI/GI/EI active low, level-triggered interrupt signal. Name and Function PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and is an input to the 82541(PI/GI/EI) device ...
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... Name and Function Power Good (Power-on Reset). The LAN_PWR_GOOD signal is used to indicate that stable power is available for the 82541(PI/GI/EI). When the signal is low, the 82541(PI/GI/EI) holds itself in reset state and floats all PCI signals. Power Management Event. The 82541(PI/GI/EI) device drives this signal low when ...
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... EEPROM used to initialize the device. For a MIcrowire* EEPROM on the standard EEPROM pins, tie this pin to ground with a 1 KΩ pull-down resistor (for the 82541PI, use a 100 Ω pull-down resistor instead). For an Serial Peripheral Interface (SPI*) EEPROM attached to the Flash memory pins, leave this pin unconnected ...
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... I XTAL2 O Note: The 82541 clock input circuit is optimized for use with an external crystal. However, an oscillator may also be used in place of the crystal with the proper design considerations. The 82540EP/ 82541(PI/GI/EI) & 825462EZ(EX) Dual Footprint Design Guide (AP-444) should be consulted for further details. ...
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... JTAG Test Access Port Reset. This is an active low reset signal for JTAG. To disable the JTAG interface, this signal should be terminated using pull- I down resistor (1 KΩ for the 82541GI(EI) and 100 Ω for the 82541PI) to ground. It must not be left unconnected. Name and Function 3 ...
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... Networking Silicon 3.7.2 Grounds, Reserved Pins and No Connects Symbol Type VSS P AVSS P RSVD_VSS P RSVD_NC 3.7.3 Voltage Regulation Control Signals (2) Symbol Type CTRL12 A CTRL18 A 18 Name and Function Ground. Shared analog Ground. Reserved Ground. This pin is reserved by Intel and may have factory test functions. ...
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... Table 2. Recommended Operating Conditions (Sheet Symbol VDD (3.3) DC supply voltage on 3.3 V pins VDD (1.8) DC supply voltage on 1.8 V pins VDD (1.2) DC supply voltage on 1.2 V pins VIO PCI bus reference voltage Input rise/fall time (normal input) Networking Silicon — 82541(PI/GI/EI) a Parameter Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -40 a Parameter Min 3 ...
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... Networking Silicon Table 2. Recommended Operating Conditions (Sheet Symbol tr/tf input rise/fall time (Schmitt input) Operating temperature range T A (ambient) T Junction temperature J a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage. ...
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... Capacitance range when using PNP circuit Capacitance Input Capacitance range when using PNP circuit Capacitance Capacitance Equivalent series resistance of output ESR capacitance Ictrl_12 Maximum output current rating to CTRL12 a. Tantalum capacitors must not be used. Networking Silicon — 82541(PI/GI/EI) a Parameter Min 0.025 1.14 a 4.7 20 µF 4.7 20 µ ...
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... Networking Silicon 4.3 DC Specifications Table 6. DC Characteristics Symbol Parameter DC supply voltage on 3.3 V VDD (3.3) pins DC supply voltage on 1.8 V VDD (1.8) pins DC supply voltage on 1.2 V VDD (1.2) pins a. The value listed in this table is for external voltage regulation. If the internal voltage regulator is used, the minimum value is 1 ...
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... Typical conditions: operating temperature (T MHz system interface. c. Maximum conditions: minimum operating temperature (T duplex, and PCI 33 MHz system interface. Table 9. Power Specifications D(r) Uninitialized 3.3 V 1.8 V 1.2 V Total Device Power Networking Silicon — 82541(PI/GI/EI) a D3cold - wake-up enabled @10 Mbps @100 Mbps Typ Icc Max Icc Typ Icc ...
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... Networking Silicon Table 10. Power Specifications - Complete Subsystem Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold - wake disabled Typ Max Icc Icc a (mA) (mA Sub-system 40 60 Power Typical conditions: operating temperature (T system interface. ...
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... IOS circuit current Input CIN capacitance a. This is only applicable to the 82541PI. The maximum VIL is 0.6 V for the following pins: A13, C5, C8, J4, L7, L13, L12, M8, M12, M13, N10, N11, N13, N14, P9, and P13. b. This is only applicable to the 82541PI (3. Mhz ...
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... IEEE specifications) • ±50 ppm at 0° 70° C • ±30 ppm at 0° 70° C (required for the 82541GI/EI) Parallel • • (required for the 82541GI/EI maximum • ...
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... The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range. Networking Silicon — 82541(PI/GI/EI) Signal Name CL ...
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... Networking Silicon Figure 4. AC Test Loads for General Output Pins 3.3 V Clock 0.5 Vcc 0.4 Vcc 0.3 Vcc Table 18. PCI Bus Interface Timing Parameters Symbol CLK to signal valid delay: bussed TVAL signals CLK to signal valid delay: point- TVAL(ptp) to-point signals TON Float to active delay ...
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... Table 19. PCI Bus Interface Timing Measurement Conditions Symbol VTH Input measurement test voltage (high) VTL Input measurement test voltage (low) VTEST Output measurement test voltage Input signal slew rate Networking Silicon — 82541(PI/GI/EI) V TEST V TEST V (3.3 V Signalling) STEP < _ output current ...
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... Networking Silicon Figure 7. TVAL (max) Rising Edge Test Load Figure 8. TVAL (max) Falling Edge Test Load Figure 9. TVAL (min) Test Load 30 Pin 1/2 inch max. 25Ω Pin 1/2 inch max. 25Ω Pin 1/2 inch max 1kΩ Test Point Test ...
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... Table 20. Link Interface Rise and Fall Times Symbol Parameter TR Clock rise time TF Clock fall time TR Data rise time TF Data fall time Figure 11. Link Interface Rise/Fall Timing 2.0 V 0.8 V Networking Silicon — 82541(PI/GI/EI) Test Point 1/2 inch max Condition Min 0 2.0 V 0.7 2 0.8 V 0.7 0 2.0 V 0.7 2 0.8 V ...
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... Networking Silicon Table 21. EEPROM Link Interface Clock Requirements Symbol Microwire EESK pulse width TPW SPI EESK pulse width a. The EEPROM clock is derived from a 125 MHz internal clock. Table 22. EEPROM Link Interface Clock Requirements Symbol TDOS EEDO setup time TDOH EEDO hold time a ...
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... This section describes the 82541(PI/GI/EI) device physical characteristics. The pin number-to- signal mapping is indicated beginning with 5.1 Package Information The 82541(PI/GI/EI) device is a 196-lead plastic ball grid array (BGA) measuring mm. The package dimensions are detailed below. The nominal ball pitch is 1 mm. 0.32 +/-0.04 Figure 11. 82541(PI/GI/EI) Mechanical Specifications Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Networking Silicon — ...
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... Networking Silicon Figure 12. 196 PBGA Package Pad Detail As illustrated in Figure copper area is 0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter is 0.50 mm. 34 Detail Area 0.45 Solder Resist Opening 0.60 Metal Diameter 12, the Ethernet controller package uses solder mask defined pads. The ...
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... Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82541(PI/GI/EI) device is operating under recommended conditions. Networking Silicon — 82541(PI/GI/EI) ° ...
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... Networking Silicon 5.3 Pinout Information Table 14. PCI Address, Data and Control Signals Signal AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] Table 15. PCI Arbitration Signals Signal REQ# GNT# Table 16. Interrupt Signals Signal INTA# Table 17. System Signals Signal CLK M66EN 36 Pin Signal Pin N7 AD[16 AD[17 AD[18 AD[19 AD[20 AD[21] C1 ...
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... Signal Pin EESK M10 EEDO N10 Table 22. Serial FLASH Interface Signals Signal FLSH_SCK FLSH_SO/LAN_DISABLE# Table 23. LED Signals Signal Pin LED0 / LINK_UP# A12 LED1 / ACTIVITY# C11 Networking Silicon — 82541(PI/GI/EI) Signal Pin PERR# J2 Pin Signal Pin A6 AUX_PWR J12 A9 Signal Pin SMBDATA C9 Signal ...
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... Networking Silicon Table 24. Other Signals Signal SDP[0] N14 SDP[1] P13 Table 25. IEEE Test Signals Signal IEEE_TEST- Table 26. PHY Signals Signal MDI[0]- C14 MDI[0]+ C13 MDI[1]- E14 MDI[1]+ E13 Table 27. Test Interface Signals Signal JTAG_TCK JTAG_TDI Table 28. Digital Power Signals (Sheet Signal 3 ...
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... E10 VSS VSS E2 VSS VSS E5 VSS VSS E6 VSS VSS E7 VSS VSS E8 VSS VSS E9 VSS Table 31. Voltage Regulation Control Signals Signal CTRL18 Networking Silicon — 82541(PI/GI/EI) Signal Pin 1.2V J6 1.2V J7 1.2V J8 Signal Pin ANALOG_1.8V D11 ANALOG_1.8V G12 PLL_1.2V G4 PLL_1.2V H4 Signal Pin Signal F10 VSS ...
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... Networking Silicon Table 32. Signal Names in Pin Order (Sheet Signal Name NC SERR# 3.3V IDSEL AD[25] PME# 3.3V AD[30] LAN_PWR_GOOD SMBCLK 3.3V LED0 / LINK_UP# TEST NC AD[22] AD[23] VSS AD[24] AD[26] AD[27] VSS AD[31] RST# SMB_ALERT# LED2 / LINK100# LED3 / LINK1000# CTRL18 IEEE_TEST+ AD[21] M66EN REQ# C/BE#[3] RSVD_NC 40 Pin A10 A11 ...
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... AD[20] RSVD_VSS VSS VSS VSS VSS NC NC ANALOG_1.8V CLKR_1.8V AVSS IEEE_TEST- 3.3V VSS AD[17] RSVD_VSS VSS VSS VSS VSS VSS VSS ANALOG_1.2V ANALOG_1.2V Networking Silicon — 82541(PI/GI/EI) Pin C10 C11 C12 C13 C14 D10 D11 D12 D13 D14 ...
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... Networking Silicon Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name MDI[1]+ MDI[1]- IRDY# FRAME# C/BE#[2] VSS VSS VSS VSS VSS VSS VSS AVSS RSVD_NC MDI[2]+ MDI[2]- CLK VIO TRDY# PLL_1.2V 1.2V 1.2V VSS VSS VSS VSS AVSS ANALOG_1.8V ANALOG_1.2V AVSS ...
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... VSS VSS ANALOG_1.2V NC MDI[3]+ MDI[3]- PAR PERR# GNT# EEMODE 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AUX_PWR XTAL_1.8V XTAL2 AD[16] VSS 3.3V 3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AVSS Networking Silicon — 82541(PI/GI/EI) Pin H10 H11 H12 H13 H14 J10 J11 J12 J13 J14 K10 K11 ...
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... Networking Silicon Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name 3.3V XTAL1 AD[14] AD[15] C/BE#[1] 1.2V 1.2V VSS RSVD_NC NC 1.2V 1.2V VSS JTAG_TMS JTAG_TRST# JTAG_TCK AD[11] AD[12] AD[13] C/BE#[0] AD[5] VSS AD[1] RSVD_NC FLSH_CE# EESK FLSH_SI SDP[3] JTAG_TDI JTAG_TDO VSS AD[10] AD[9] AD[7] AD[4] 44 Pin K13 K14 L10 L11 L12 L13 ...
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... Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name 3.3V AD[0] 3.3V FLSH_SCK EEDO RSVD_NC VSS SDP[2] SDP[0] NC 3.3V AD[8] AD[6] AD[3] AD[2] EECS VSS FLSH_SO EEDI CTRL12 3.3V SDP[1] NC Networking Silicon — 82541(PI/GI/EI) Pin N10 N11 N12 N13 N14 P10 P11 P12 P13 P14 ...
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... Networking Silicon 5.4 Visual Pin Assignments AD[22] AD[21] AD[18] 2 SERR# AD[23] M66EN AD[19] 3 3.3V VSS REQ# AD[20] RSVD_ C/BE#[3] 4 IDSEL AD[24] VSS RSVD_ 5 AD[25] AD[26] VSS NC 6 PME# AD[27] AD[28] VSS 3.3V VSS AD[29] VSS 7 CLK_ 8 AD[30] AD[31] VSS RUN# LAN_ 9 PWR_ RST# SMBDATA NC GOOD SMB_ 10 SMBCLK VSS NC ALERT LED2/ LED1/ ANALOG_ 11 3.3V LINK ACTIVITY# 1 ...