CS5336-KS Cirrus Logic, Inc., CS5336-KS Datasheet
CS5336-KS
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CS5336-KS Summary of contents
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... The CS5336 & CS5338 have an SCLK which clocks out data on rising edges. The CS5339 has an SCLK which clocks out data on falling edges. The CS5336 has a filter passband 22kHz. The CS5338 & CS5339 have a filter passband kHz. The filters have linear phase, 0.01 dB passband ripple, and > ...
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... VIN 3.5 3.68 - ZIN - 65 IA VA- IA- - -25 -35 VD VA- IA- - -10 -50 VD+ ID 400 PDN - 400 575 PDS - 0.15 2 PSRR - 100 CS5336, CS5338, CS5339 = and T A CS5336-B CS5336-T -40 to +85 -55 to +125 - 93 .005 .001 - .013 .005 - - .0001 - - .0001 - ...
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... Notes: 3. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 3.072MHz 22kHz for the CS5338 & CS5339 3.072MHz 20.0kHz for the CS5336, where n = 0,1,2,3...). DIGITAL CHARACTERISTICS ( ...
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... DPD pulse width DPD rising to DCAL rising DPD falling to DCAL falling (OWR = Output Word Rate) Notes: 4. ICLKD rising or falling depends on DPD to L/R timing (see Figure 2). 5. SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339. 6. Specifies minimum output word rate (OWR kHz. 3-42 5%; VA- = -5V 5% ...
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... SCLK output (MASTER mode) ICLKD to Outputs Propagation Delays (CMODE high) t sdo t msfs t t sclkh sclkl t sclkw t dss MSB-1 MSB-2 MSB-1 MSB-2 CS5336, CS5338, CS5339 t t clkh2 clkl2 t clkw2 t io2 pdw pcf DPD t pcr DCAL Power Down & Calibration Timing ...
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... VD+ 28 VREF F 2 CS5336 AINL CS5338 27 CS5339 AINR A/D CONVERTER 3 ZEROL 26 ZEROR 1 AGND VA- LGND DGND 0.1 F Figure 1. Typical Connection Diagram CS5336, CS5338, CS5339 Typ Max 5.0 VA+ 5.0 VA+ 5.0 5. 5.0 5.25 - 3.68 +5V Digital + 0 Power Down APD & Calibrate 10 DPD Control 7 ACAL 9 DCAL ...
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... GENERAL DESCRIPTION The CS5336, CS5338, and CS5339 are 16-bit, 2- channel A/D converters designed specifically for stereo digital audio applications. The devices use two one-bit delta-sigma modulators which simul- taneously sample the analog input signals sampling rate. The resulting serial bit streams are digitally filtered, yielding pairs of 16-bit val- ues ...
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... L/ R Output SCLK Output FSYNC Output SDATA 15 14 Output * SCLK for CS5336/8. SCLK inverted for Left Audio Data CS5339 L/ R Input SCLK Input FSYNC Input (high) SDATA 15 14 Output * SCLK for CS5336/8. SCLK inverted for Left Audio Data CS5339 Figure 4 ...
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... LSB would result very small dc offset all modes, SCLK is shown for the CS5336 and CS5338, where data bits are clocked out on rising edges. SCLK is inverted for the CS5339. CS5336, CS5338, CS5339 *** ...
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... The ADC samples the analog inputs at 3.072 MHz for a 12.288 MHz ICLKD (CMODE low). For the CS5336, the digital filter rejects all noise between 26 kHz and (3.072 MHz-26 kHz). For the CS5338 and CS5339, the digital filter re- jects all noise between 28 kHz and (3 ...
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... A short delay of approximately 40 output words will occur following calibration for the digital filter to begin accurately tracking audio band signals. DS23F1 CS5336, CS5338, CS5339 Power-up Considerations Upon initial application of power to the supply pins, the data in the calibration registers will be indeterminate. A calibration cycle should always ...
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... ADC, and an FFT analysis is performed on the output data. The resulting spec- trum is a measure of the performance of the ADC. Figure 7 shows the spectral purity of the CS5336 with a 1 kHz, -10 dB input. Notice the low noise floor, the absence of any harmonic distortion, and the Dynamic Range value of 95 ...
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... Non-Linearity of the CS5336. This plot DS23F1 Signal ( kHz) Amplitude Relative to Full Scale (dB Figure 8. CS5336 FFT Plot with -10 dB, 9 kHz Input Signal ( kHz) Amplitude Relative to Full Scale (dB Figure 10. CS5336 FFT Plot with -80 dB, 9 kHz Input displays the worst case positive and negative er- rors in each of 512 groups of 128 codes ...
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... Stopband rejection is greater than 80 dB. Figures 12,14 &16 show the CS5338 and CS5339 filter characteristics. Figure expanded view of the transition band. Figures 13,15 & 17 show the CS5336 filter char- acteristics. Figure expanded view of the transition band. 3-52 CS5336, CS5338, CS5339 32,768 ...
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... Figure 15. CS5336 Digital Filter Passband Ripple -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 Figure 17. CS5336 Digital Filter Transition Band CS5336, CS5338, CS5339 10 0 -10 -20 -30 -40 -50 -60 -70 -80 - Input Frequency (kHz ...
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... TEST TST L CS5336, CS5338, CS5339 VREF VOLTAGE REFERENCE OUTPUT AINR RIGHT CHANNEL ANALOG INPUT ZEROR RIGHT CHANNEL ZERO INPUT VL+ ANALOG SECTION LOGIC POWER LGND ANALOG SECTION LOGIC GROUND ICLKA ANALOG SECTION CLOCK INPUT NC NO CONNECT OCLKD DIGITAL SECTION OUTPUT CLOCK ...
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... A calibration cycle should always be initiated after applying power to the supply pins. ACAL - Analog Calibrate, PIN 7. Analog section calibration command. When high, causes the left and right channel modulator inputs to be internally connected to ZEROL and ZEROR inputs respectively. May be connected to DCAL. DS23F1 CS5336, CS5338, CS5339 3-55 ...
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... Digital Inputs or Outputs SCLK - Serial Data Clock, PIN 15. Data is clocked out on the rising edge of SCLK for the CS5336 and CS5338. Data is clocked out on the falling edge of SCLK for the CS5339. In master mode (SMODE high), SCLK is a continuous output clock the output word rate ...
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... These two pins are bonded out to test outputs. They must not be connected to any external component or any length of PC trace. TST -Test Input, PIN 11. Allows access to the ADC test modes, which are reserved for factory use. Must be tied to DGND. DS23F1 CS5336, CS5338, CS5339 3-57 ...
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... Gain Error - The deviation of the measured full scale amplitude from the ideal full scale amplitude value. Gain Drift - The change in gain value with temperature. Units in ppm/ C. Bipolar Offset Error - The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below AGND). Units in LSBs. 3-58 CS5336, CS5338, CS5339 N, where N = the number of bits DS23F1 ...
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... Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. Ordering Guide Model Resolution CS5336-KP 16-bits CS5336-BP 16-bits CS5338-KP 16-bits CS5339-KP 16-bits CS5336-KS 16-bits CS5336-BS 16-bits CS5338-KS 16-bits CS5339-KS 16-bits CS5336-TC 16-bits CDB5336 CS5336 Evaluation Board CDB5338 ...
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... CDB5336 CDB5338 CDB5339 General Description The CDB5336, CDB5338 & CDB5339 evaluation boards allow fast evaluation of the CS5336, CS5338 and CS5339 16-bit, stereo A/D converters. The boards generate all converter timing signals and provide both parallel and serial output interfaces. Evaluation re- quires a digital signal processor, a low-distortion signal source, and a power supply ...
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... C25 47 uF 0.22 uF C31 C26 + 47 uF 0.22 uF COM IN 79L05 OUT U11 VD 1N4148 47 uF 0.1 uF SW1 CAL Figure 1. Power Supply and Reset Circuitry CDB5336,8,9 VA+ C27 0. C28 AGND DGND 0. RST CS8402 U7E VD+ R26 10k 11 10 Cal (DPD CS5336) 0.1uF U7D C15 3-61 ...
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... C1 From NPO Buffers Fig NPO R3 Optional 3-62 0 C16 C17 28 22 VREF NC 18 VD VA+ CS5336 1 CS5338 AGND CS5339 5 VA- 24 LGND 19 DGND 27 AINR 2 AINL ZEROL ZEROR OCLKD C3* C4* R4 U8A MCK ...
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... Analog Inputs As shown in Figure 2, the analog input signals are connected to the CS5336 via an RC network. R1 and C1 provide antialiasing and optimum source impedance for the right analog input channel while R2 and for the left chan- nel. The ZEROR and ZEROL inputs are tied to ...
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... Q2 Jumper P4 allows the board to be configured for either the CS5336/38, or the CS5339, which have opposite polarities of SCLK. Parallel Output Interface Figure 6 depicts the parallel output interface on the evaluation board. 16-bit words are assembled from the serial data output of the converter. Each ...
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SMODE 15 SCLK 17 FSYNC 14 L/R 16 SDATA U8B 5 U8C on the rising edge of SCLK and shifted into the 16-bit shift register formed by U4 and U5 on SCLK’s falling edge. After all ...
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PIN14 VD CLR FSYNC 2 D PIN17 Q U1 U12A Q ICLKD 3 CLK 14 PIN20 VCC U1 PRE GND 4 7 R11 47 k VD+ C19 CLR 3 6 ...
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... P1 left then right channel data alternately presented on P1 DRDY selected to signal the arrival of new data for the selected channel L/R selected Buffer amplifier in circuit Buffer amplifier bypassed Correct SCLK for CS5337 & CS5339 Correct SCLK for CS5336 & CS5338 3-67 ...
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Switch# 0=Closed, 1=Open 3 PRO=0 1 CRE default C6 default default default EM1, EM0 default 1 1 ...
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Switch# 0=Closed, 1=Open 3 PRO FC1, FC0 C15 C8 ...
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Figure 7. Top Ground Plane Layer (NOT TO SCALE) 3-70 CDB5336,8,9 DS23DB5 ...
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DS23DB5 Figure 8. Bottom Trace Layer (NOT TO SCALE) CDB5336,8,9 3-71 ...
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Figure 9. Component Layout (NOT TO SCALE) CDB5336,8,9 DS23DB5 ...