82562V Intel Corporation, 82562V Datasheet
82562V
Specifications of 82562V
Available stocks
Related parts for 82562V
82562V Summary of contents
Page 1
... PHY detects polarity, MDI-X, and cable n lengths. Auto MDI, MDIX crossover at all speeds Additional Features The 82562V PLC supports strapping options that enable the following operating modes: n — LED support for three logic configurations. — LAN disable function using one pin. — Increased transmit strength. ...
Page 2
... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82562V PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
Page 3
... The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562V complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82562V also includes a PHY interface compliant to the current platform LAN connect interface. 1.2 References • ...
Page 4
... Networking Silicon 2.0 82562V Architectural Overview The 82562V PLC is a 3.3 V device in a 81-pin Mold Cap package. In normal operating mode, the 82562V incorporates all active circuitry required to interface with the Intel integrated 10/100 Mbps LAN controller. The 82562V supports a direct interface to all Media Access Control (MAC) components that meet the Platform LAN connect interface specification ...
Page 5
... Reset Considerations When the 82562V Reset signal (JRSTSYNC) is asserted for at least 500 µs, all internal circuits are reset. The 82562V can also be reset by setting the MII register Reset bit equal to 1 (Register 0, bit 15). The 82562V filters out JRSTSYNC pulses with a width of less than 200 ns to distinguish between a reset and synchronize pulse. Again, the Reset signal should be longer than 500 µ ...
Page 6
... When the 82562V is in 100BASE-TX mode it drives JCLK at 50 MHz. When the 82562V is in 10BASE-T mode it drives JCLK at 5 MHz. The LAN Connect clock does not stop during normal operation under any conditions. In reduced power mode, the 82562V drives JCLK at 5 MHz, which is required for proper filtering of incoming packets for applications such as Wake on LAN (WoL) ...
Page 7
... Networking Silicon — 82562V Table 1. 82562V Hardware Configuration ISOL ISOL TESTEN _TCK NOTE: Combinations not shown in Table 2. LED Logic Functionality Mode/Configuration Configuration A: 82562ET- compatible Configuration B: Intel GbE mode Configuration C: Alternative mode Datasheet ISOL_ Mode _TI EXEC 0 1 Reserved ...
Page 8
... BOM cost compared to the 82562ET PLC device. To implement these new features, a board design must include the proper pull-up and/or pull-down strapping resistor options. Refer to the 82562V/ 82562GZ/82562GX/82562G LAN on Motherboard Design Guide for more information. ...
Page 9
... MDI/MDI-X provides the ability to automatically detect the required cable connection type and configure the controller-side MAU to the cable type. MDI/MDI-X effectively allows all properly wired Ethernet cables usable with any Ethernet device to be connected to the 82562V without any additional external logic. ...
Page 10
... Networking Silicon Note: This page intentionally left blank. 8 Datasheet ...
Page 11
... Description Input pin to the 82562V. Output pin from the 82562V. Multiplexed input and output pin to and from the 82562V. Multi-level analog pin used for input and output. Bias pin used for ground connection through a resistor or an external voltage reference. Digital power or ground pin for the 82562V. ...
Page 12
... I LAN Connect Transmit Data. The LAN Connect transmit pins are used to transfer data from the MAC device to the 82562V. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. The pins should be fully synchronous to JCLK ...
Page 13
... Datasheet Type Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and the 82562V advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562V advertises all of its technologies. Note: ADV10 has an internal 10 K Ω pull-down resistor. LAN Disable in 82562G Mode. In the 82562G operating mode, this pin is used as a LAN disable signal ...
Page 14
... Mode 5.1.1 100BASE-TX Transmit Blocks The transmit subsection of the 82562V accepts 3 bit wide data from the LAN Connect unit. Another subsection passes data unconditionally to the 4B/5B encoder. The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5- bit-wide parallel symbols. These symbols are scrambled and serialized into a 125 Mbps bit stream, converted by the analog transmit driver into a MLT-3 waveform format, and transmitted onto the Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire ...
Page 15
... The 82562V scrambles and serializes the data into a 125 Mbps stream, encodes it as MLT-3, and drives it onto the wire. ...
Page 16
... The 82562V first decodes the MLT-3 data, and then the descrambler reproduces the 5B symbols originated in the transmitter. The descrambling is based on synchronization to the transmission of the 11-bit Linear Feedback Shift Register (LFSR) during an idle phase. The data is decoded at the 4B/5B decoder. After the 4B symbols are obtained, the 82562V outputs the receive data to the CSMA unit. 14 Figure 3 ...
Page 17
... Networking Silicon — 82562V In 100BASE-TX mode, the 82562V can detect errors in receive data in a number of ways. Any of the following conditions is considered an error: • Link integrity fails in the middle of frame reception. • The start of stream delimiter “JK” symbol is not fully detected after idle. ...
Page 18
... LAN activity is not present. The reduced power mode decreases power consumption from 300 mW to about 50 mW and is based on automatic detection of cable plugging. If the 82562V is configured to support dynamic power reduction, it enters the reduced power mode whenever a cable is not connected to the device. In reduced power mode, the 82562V shuts off the link circuits, except the circuit used for the automatic plugging detection ...
Page 19
... Auto Plugging Detection The 82562V senses the link all the time detects loss of any link activity for more than 6.6 seconds, it indicates to the Media Access Controller (MAC) an “unplugged state” by resetting the SQL LAN Connect control bit. If the 82562V is in reduced power mode and link activity is detected, the 82562V notifies the MAC (in less than 1 second) that “ ...
Page 20
... Networking Silicon 6.0 Platform LAN Connect Registers The following sections describe PHY registers that are accessible through the LAN Connect management frame protocol. Acronyms mentioned in the registers are defined as follows: SC: Self cleared. RO: Read only. RW: Read/Write. E: EEPROM setting affects content. LL: Latch low ...
Page 21
... PHY shall not be affected by the status of this bit Half Duplex 1 = Full Duplex This bit is not used in the 82562V and has a default value of 1b. ( used in other devices, it forces a collision in response to the assertion of the transmit enable signal.) These bits are reserved and should be set to 0b. ...
Page 22
... This bit enables the extended register capabilities Extended register capabilities disabled 1 = Extended register capabilities enabled Description Description Value: 0330 hexadecimal for 82562V PLC (and 82562GZ) Value: 0310 hexadecimal for 82562G Description This bit is a constant 0, transmit primary capability data page. This bit is reserved and should be set to 0b. ...
Page 23
... Datasheet Description This bit reflects the PHY’s link partner’s Next Page ability. This bit is used to indicate that the 82562V has successfully received its link partner’s Auto-Negotiation advertising ability. This bit reflects the PHY’s link partner’s Remote Fault condition. This bit reflects the PHY’ ...
Page 24
... Networking Silicon 6.3 MDI Registers 16 through 31 6.3.1 Register 16: PHY Status and Control Register Bit Definitions Bit(s) Name 15:14 Reserved 13 Reduced Power Down Disable 12 Reserved 11 Receive De- Serializer In-Sync Indication 10 100BASE-TX Power-Down 9 10BASE-T Power- Down 8 Polarity 7 Reserved 6:2 PHY Address 1 Speed 0 Duplex Mode 6.3.2 Register 17: PHY Unit Special Control Bit Definitions ...
Page 25
... Networking Silicon — 82562V Bit(s) Name 11 Valid Link 10 Symbol Error Enable 9 Carrier Sense Disable 8 Disable Dynamic Power-Down 7 Auto-Negotiation Loopback 6 MDI Tri-State 5 Force Polarity 4 Auto Polarity Disable 3 Squelch Disable 2 Extended Squelch 1 Link Integrity Disable 0 Jabber Function Disable 6.3.3 Register 18: Reserved Bit(s) Name 15:0 Reserved 6 ...
Page 26
... Networking Silicon 6.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions Bit(s) Name 15:0 Disconnect Event 6.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions Bit(s) Name 15:0 Receive Error Frame 6.3.7 Register 22: Receive Symbol Error Counter Bit Definitions Bit(s) Name 15:0 Symbol Error Counter 6.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter ...
Page 27
... Control. This bit should always be set to 0b. If this bit equals 0, the device is in 82562EZ (or 82562ET) mode. If this bit equals 1, the device is in 82562V (or 82562GZ) mode. This bit enables the carrier sense disconnection while the PHY is in jabber mode at 100 Mbps speed. ...
Page 28
... Networking Silicon Note: This page intentionally left blank. 26 Datasheet ...
Page 29
... Networking Silicon — 82562V 7.0 82562V Test Port Functionality The 82562V’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 7.1 Asynchronous Test Mode An asynchronous test mode is supported for system level design use. The modes are selected through the use of the Test Port input pins (TESTEN, ISOL_TCK, ISOL_TI and ISOL_EXEC) in static combinations ...
Page 30
... Networking Silicon Table 8. XOR Tree Chain Order XOR Tree Output The following pins are not included in the XOR Tree chain: X1, ISOL_TCK, ISOL_EXEC, ISOL_TI and TESTEN. 28 Chain Order Chain 11 SPDLED# 12 LILED# TOUT Datasheet ...
Page 31
... Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 3.45 V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562V device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
Page 32
... Networking Silicon Table 10. Current and Power Values (measured)* System Maximum * Averaging of three typical units at typical and maximum conditions with nominal VCC. ** LED power deducted from overall power consumption. 8.2.1 X1 Clock DC Specifications Table 11. X1 Clock DC Specifications Symbol Parameter V Input Low Voltage ...
Page 33
... Networking Silicon — 82562V 8.2.2 LAN Connect Interface DC Specifications Table 12. LAN Connect Interface DC Specifications Symbol Parameter V Input/Output CCJ Supply Voltage V Input Low Voltage IL V Input High Voltage IH I Input Leakage IL Current V Output Low OL Voltage V Output High OH Voltage C Input Pin IN Capacitance NOTES: 1. This characteristic is only characterized, not tested valid for digital pins only. ...
Page 34
... Networking Silicon Table 15. 10BASE-T Receiver V Input Differential IDA10 Accept Peak Voltage V Input Differential IDR10 Reject Peak Voltage V Input Common ICM10 Mode Voltage NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN. 8.2.5 100BASE-TX Voltage and Current DC Specifications Table 16 ...
Page 35
... Networking Silicon — 82562V 8.3 AC Characteristics Figure 5 defines the conditions for timing measurements. The design must guarantee proper operation for voltage swings and slew rates that exceed the specified test conditions. Figure 5. AC Test Level Conditions 8.3.1 10BASE-T Normal Link Pulse (NLP) Timing Parameters Table 18 ...
Page 36
... Networking Silicon 8.3.2 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Table 19. Fast Link Pulse Timing Parameters Symbol T8 T LP_WID FLP_CLK_CLK T10 T FLP_CLK_DATA T11 T FLP_BUR_NUM T12 T FLP_BUR_WID T13 T FLP_BUR_PER Figure 7. Fast Link Pulse Timings Fast Link Pulse FLP Bursts 34 Parameter ...
Page 37
... Networking Silicon — 82562V 8.3.3 100BASE-TX Transmitter AC Specifications Table 20. 100BASE-TX Transmitter Timing Parameters Symbol T14 T JIT 8.3.4 Reset (JRSTSYNC) AC Specifications Table 21. Reset Timing Parameters Symbol T58 T RST_WID T59 T POP_RST Figure 8. Reset Timing Parameters Datasheet Parameter Condition Min TDP/TDN HLS Data Differential Output Peak Jitter ...
Page 38
... Package and Pinout Information 9.1 Package Information The 82562V is a 81-pin Mold Cap package. The Package dimensions are shown in information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local sales office. Figure 9. Dimension Diagram for the 82562V PLC 9 ...
Page 39
... Networking Silicon — 82562V Table 22. 82562V Pin Assignments Pin Pin Name Number B3 VCC B4 ACT_LED TEST_EN TDP B9 TDN C1 JRXD2 VSS VSSR Datasheet Pin Pin Pin Name Number Number D9 RDP G6 E1 VSSP G7 RBIAS100 E2 JCLK G8 E3 JRST_SYNC G9 E4 VCC ...
Page 40
... Networking Silicon 9.2.2 82562V Package Diagram Figure 10. 82562V Pin Out Diagram--Top View VSSA VSS NC NC VSS VCCT RDP RDN VSS VSS TDN TDP NC VSS VSSA2 NC RBIAS10 RBIAS100 VSS NC VCCA2 VCCA VSS NC VSS NC NC VCC ...
Page 41
... Networking Silicon — 82562V Note: This page intentionally left blank. Datasheet 39 ...
Page 42
... Networking Silicon 40 Datasheet ...