MX29F001TQC-12 Macronix International Co., MX29F001TQC-12 Datasheet
MX29F001TQC-12
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MX29F001TQC-12 Summary of contents
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FEATURES • 5.0V 10% for read, erase and write operation • 131072x8 only organization • Fast access time: 90/120ns • Low power consumption - 30mA maximum active current(5MHz typical standby current A • Command register architecture - Byte ...
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PIN CONFIGURATIONS 32 PDIP A16 2 31 A15 3 30 A12 ...
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BLOCK DIAGRAM CONTROL CE INPUT OE LOGIC WE ADDRESS LATCH A0-A16 AND BUFFER Q0-Q7 P/N: PM0515 MX29F001T/B PROGRAM/ERASE HIGH VOLTAGE MX29F001T/B FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 3 WRITE ...
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AUTOMATIC PROGRAMMING The MX29F001T/B is byte programmable using the Au- tomatic Programming algorithm. The Automatic Program- ming algorithm does not require the system to time out or verify the data programmed. The typical chip pro- gramming time of the MX29F001T/B ...
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TABLE 1. SOFTWARE COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH Read 1 RD Read Silicon ID 4 555H Chip Protect Verify 4 555H Program 4 555H Chip Erase 6 555H Sector Erase 6 555H Sector ...
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TABLE 2. MX29F001T/B BUS OPERATION Pins Mode Read Silicon ID Manufacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Chip Protect with 12V system(6) Chip Unprotect with 12V system(6) Verify Chip Protect with 12V system Chip Protect ...
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READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The de- vice remains enabled for reads until the command regis- ter contents are ...
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SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Au- tomatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device ...
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Table 4. Write Operation Status Status Byte Program in Auto Program Algorithm In Progress Auto Erase Algorithm Erase Suspended Mode Byte Program in Auto Program Algorithm Exceeded Erase in Auto Erase Algorithm Time Limits Erase Suspended Mode Note: 1. Performing ...
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ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all ...
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Q5 Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not ...
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WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one VIL VIH VIH. ...
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ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & OE CAPACITANCE 1.0 MHz SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin ...
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AC CHARACTERISTICS VCC = 5V SYMBOL PARAMETER tACC Address to Output Delay tCE CE to Output Delay tOE OE to Output Delay tDF OE High to Output Float (Note1) tOH Address to Output hold TEST CONDITIONS: • Input pulse levels: ...
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READ TIMING WAVEFORMS VIH A0~16 VIL VIH CE VIL VIH WE VIL VIH OE VIL HIGH Z VOH DATA Q0~7 VOL COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS VCC = 5V SYMBOL PARAMETER ICC1 (Read) Operating VCC Current ICC2 ICC3 (Program) ...
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AC CHARACTERISTICS VCC = 5V SYMBOL PARAMETER tOES OE setup time tCWC Command programming cycle tCEP WE programming pulse width tCEPH1 WE programming pulse width High tCEPH2 WE programming pulse width High tAS Address setup time tAH Address hold time ...
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SWITCHING TEST CIRCUITS DEVICE UNDER TEST SWITCHING TEST WAVEFORMS 2 TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns. P/N: ...
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COMMAND WRITE TIMING WAVEFORM VCC 5V VIH ADD A0~16 VIL tAS VIH WE VIL tOES CE VIH VIL tCS OE VIH VIL VIH DATA Q0-7 VIL P/N: PM0515 ADD Valid tAH tCEP tCWC tCH tDS tDH DIN 18 MX29F001T/B tCEPH1 ...
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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verification in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA polling ...
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AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address NO Invalid Command Auto Program Completed P/N: PM0515 START NO Toggle Bit Checking Q6 not Toggled YES Verify ...
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TOGGLE BIT ALGORITHM NO Notes: 1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text. 2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text. P/N: PM0515 START Read ...
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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be veri- fied by DATA polling and toggle bit checking after ...
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AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H NO Invalid Command Auto Chip ...
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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector data indicated by A13 to A16 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle ...
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AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Toggle Bit Checking Q6 ...
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ERASE SUSPEND/ERASE RESUME FLOWCHART P/N: PM0515 MX29F001T/B START Write Data B0H NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H Continue Erase Another . NO Erase Suspend ? ...
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TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V A1 A6 12V 5V A9 tVLHT 12V 5V OE tVLHT WE CE Data P/N: PM0515 tWPP 1 tOESP 27 MX29F001T/B Verify tVLHT 01H F0H tOE REV. 2.6, DEC. 29, 2003 ...
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TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V A1 12V 5V A9 tVLHT A6 12V 5V OE tVLHT WE CE Data P/N: PM0515 tWPP 2 tOESP 28 MX29F001T/B Verify tVLHT 00H F0H tOE REV. 2.6, DEC. 29, 2003 ...
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CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V P/N: PM0515 START PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Device Failed Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector No Addr=SA, A1=1 No Data=01H? PLSCNT=32? Yes Remove VID ...
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CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V P/N: PM0515 START PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 12ms Set OE=CE=VIL A9=VID,A1=1 Read Data from Device No Data=00H? PLSCNT=1000? Yes Remove VID from A9 Device Failed Write Reset Command ...
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TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V Don't care Data Note: 1. Must issue "unlock for sector protect/unprotect" command before chip protection for a system without 12V provided. 2. Except F0H P/N: ...
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TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V tCEP WE CE Data Don't care (Note 2) Note: 1. Must issue "unlock for sector protect/unprotect" command P/N: PM0515 Toggle bit polling * See the following Note! ...
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CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Increment PLSCNT PLSCNT=32? Device Failed P/N: PM0515 START PLSCNT=1 Write "unlock for chip protect/unprotect" Command(Table1) OE=VIH,A9=VIH CE=VIL,A6=VIL Activate WE Pulse to start Data don't care Toggle bit checking DQ6 not Toggled Yes Set ...
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CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Write "unlock for chip protect/unprotect" No P/N: PM0515 START PLSCNT=1 Command (Table 1) Set OE=A9=VIH CE=VIL,A6=1 Activate WE Pulse to start Data don't care Toggle bit checking DQ6 not Toggled Yes Set OE=CE=VIL ...
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ID CODE READ TIMING WAVEFORM VCC 5V VID ADD VIH A9 VIL tACC A1 VIH VIL ADD VIH A2-A8 A10-A16 VIL CE VIH VIL VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q7 P/N: PM0515 tACC tCE tOE tOH ...
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ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured 5V. 3.Maximum values measured ...
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... ORDERING INFORMATION PLASTIC PACKAGE (Top Boot Sector as an sample For Bottom Boot Sector ones,MX29F001Txx will change to MX29F001Bxx) PART NO. ACCESS TIME (ns) MX29F001TQC-90 90 MX29F001TQC-12 120 MX29F001TTC-90 90 MX29F001TTC-12 120 MX29F001TPC-90 90 MX29F001TPC-12 120 P/N: PM0515 MX29F001T/B OPERATING CURRENT STANDBY CURRENT MAX.(mA) MAX.(uA ...
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PACKAGE INFORMATION P/N: PM0515 MX29F001T/B 38 REV. 2.6, DEC. 29, 2003 ...
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P/N: PM0515 MX29F001T/B 39 REV. 2.6, DEC. 29, 2003 ...
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P/N: PM0515 MX29F001T/B 40 REV. 2.6, DEC. 29, 2003 ...
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REVISION HISTORY Revision Description 2 remove "Advanced Information" data sheet marking and contain information on products in full production 2.The modification summary from Revision 0.0 to Revision 1.0: 2-1.Program/erase cycle times:10K cycles-->100K cycles 2-2.To add data retention 20 ...
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... MX29F001T/B MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...