SY88793VKG Micrel Inc, SY88793VKG Datasheet - Page 5

• Manufacturer Part Number: SY88793VKG
• Description: IC POST AMP PECL LP LIMIT 10MSOP
• Manufacturer: Micrel Inc
• Type: Limiting Postamplifierr

Specifications of SY88793VKG

• Applications: Optical Networks
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2547; SY88793VKG

Micrel, Inc.
from a single +3.3V or +5V power supply, over temperatures
from –40 C to +85 C. Signals with data rates up to 622Mbps
and as small as 5mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88793V generates
an SD output. SD
amplitude detection.
Input Amplifier/Buffer
input stage. The high-sensitivity of the input amplifier allows
signals as small as 5mV
The input amplifier allows input signals as large as
1800mV
38dB differential voltage gain. Since it is a limiting amplifier,
the SY88793V outputs typically 1500mV
waveforms for input signals that are greater than 18mV
Applications requiring the SY88793V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88793V’s input pins to ensure the best
performance of the device.
Output Buffer
50 lines. The output buffer requires appropriate termination
for proper operation. An external 50
for each output pin provides this. Figure 3 shows a simplified
schematic of the output stage and includes an appropriate
termination method.
Signal-Detect
TTL output with internal 6.75k
Figure 4. SD is used to determine that the input amplitude
is large enough to be considered a valid input. SD asserts
high if the input amplitude rises above the threshold set by
M9999-072505
[e-mail] or [phone]
DETAILED DESCRIPTION
The SY88793V low-power limiting post amplifier operates
Figure 2 shows a simplified schematic of the SY88793V's
The SY88793V’s PECL output buffer is designed to drive
The SY88793V generates a chatter-free SD open-collector
PP
. Input signals are linearly amplified with a typically
LVL
sets the sensitivity of the input
PP
to be detected and amplified.
pullup resistor as shown in
resistor to V
PP
voltage-limited
CC
–2V
PP
.
5
SD
the enable (EN) input to maintain output stability under a
loss of signal condition. EN deasserts the true output signal
without removing the input signals. Typically 6dB SD
hysteresis is provided to prevent chattering.
Signal-Detect Level Set
threshold of the input amplitude detection. Connecting an
external resistor between V
at SD
external resistor creates a voltage divider between V
V
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SD
Hysteresis
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88793V provides typically 3dB SD
optical hysteresis. As the SY88793V is an electrical device,
this datasheet refers to hysteresis in electrical terms. With
6dB SD hysteresis, a voltage factor of two is required to
assert or deassert SD.
REF
A programmable SD level set pin (SD
The SY88793V provides typically 6dB SD electrical
LVL
LVL
LVL
as shown in Figure 5. If desired, an appropriate
and deasserts low otherwise. SD can be fed back to
voltage.
. This voltages ranges from V
LVL
to V
CC
CC
, the smaller the SD sensitivity.
and SD
LVL
CC
sets the voltage
LVL
to V
2
IN
) sets the
SY88793V
/R for an
REF
CC
. The
and