UPD485506G5-35-7JF NEC, UPD485506G5-35-7JF Datasheet
UPD485506G5-35-7JF
Related parts for UPD485506G5-35-7JF
UPD485506G5-35-7JF Summary of contents
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... BY 16-BIT/10K-WORD BY 8-BIT Description The PD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either 5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power consumption ...
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Pin Configuration (Marking side) 44-pin plastic TSOP (II) (10.16 mm (400 OUT0 D 2 OUT1 D 3 OUT2 D 4 OUT3 D 5 OUT4 D 6 OUT5 D 7 OUT6 D 8 OUT7 GND ...
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Block Diagram RSTW Write Address Pointer WCK WE D IN0 D IN1 D IN2 D IN3 D IN4 D IN5 D IN6 D IN7 D IN8 D IN9 D IN10 D IN11 D IN12 D IN13 D IN14 D IN15 ...
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Input/Output Pin Function Pin I/O Pin Pin Symbol Number Name In 44 – 37, D Data IN0 | Input 30 – IN15 Out 1 – Data OUT0 | Output 15 – OUT15 In ...
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Operation Mode PD485506 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK). For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK). ...
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... After power up, the PD485506 requires the initialization of internal circuits because the read and write address pointers are not defined at that time necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and RCK, and then input the RSTW and RSTR signals to initialize the circuit. ...
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Operation-related Restriction Following restriction exists to read data written in a write cycle. Read the written data after an elapse of 1/2 write cycle + not satisfied, the output data may undefined. WAR Figure 2.1 Delay ...
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Electrical Specifications All voltages are referenced to GND. Absolute Maximum Ratings Parameter Voltage on any pin relative to GND Supply voltage Output current Operating ambient temperature Storage temperature Note –3.0 V MIN. (Pulse width = 10 ns) Caution Exposing ...
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AC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Write clock cycle time Write clock pulse width Write clock precharge time Read clock cycle time Read clock pulse width Read clock precharge time Access time Write data-read delay time Output ...
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Notes 1. AC measurements assume Characteristics test condition Input Timing Specification 3 Output Timing Specification High impedance Output Loads for Timing 1 OUT 1 Input timing reference levels = 1.5 ...
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Write Cycle Timing Chart Cycle n Cycle n+1 t WCK t WCP WCK (Input) t WCW WE (Input (Input) (n) IN Remark RSTW = “H” level Read Cycle Timing Chart (RE Control) Cycle n Cycle ...
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Write Reset Cycle Timing Chart (WE = Active) Cycle n WCK (Input RN1 RS RSTW (Input) WE (Input) “L” Level t DS (n–1) D (Input) IN Note In write reset cycle, reset operation is executed even without a ...
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Read Reset Cycle Timing Chart (RE = Active) Cycle n RCK (Input RN1 RS RSTR (Input) RE (Input) “L” Level (Output) (n – 1) (n) OUT Note In read reset cycle, reset operation is executed ...
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Application 4 Delay Line PD485506 easily allows (5,048 bits/10,096 bits) delay line (see Figure 4.1). Figure 4 Delay Line Circuit 40 MHz Clock Data Input 8/16 Figure 4 Delay Line ...
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Bit Delay It is possible to make delay read from the write data with the PD485506. (1) Perform a reset operation in the cycle proportionate to the delay length (see Figure 4.3). (2) Shift the input timing of ...
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Figure 4.4 n-Bit Delay Line Timing Chart (2) t WCK t RCK Cycle 0 Cycle 1 Cycle 2 Write Read t t WCW WCP t t RCW RCP WCK/RCK (Input RSTW (Input) RSTR t DS (Input) ...
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Figure 4.6 Mode Set Cycle Timing Chart (Write) (1) Cycle (Input) RSTW (Input RN1 WCK (Input IN0 IN7 (n–1) (Input ...
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Figure 4.8 Mode Set Cycle Timing Chart (Read) (1) Cycle (Input) RSTR (Input RN1 RS RCK (Input OUT0 OUT7 (n–1) (n) (Output ...
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Double-speed Conversion Figure 4.10 shows an example timing chart of double-speed and twice reading operation (f Note 2 cycles or 10,096 by 2 cycles ) for a write operation (f Caution The read operation collide with the write operation ...
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Data Sheet M10060EJ7V0DS00 PD485506 ...
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Package Drawing 44-PIN PLASTIC TSOP(II) (10.16 mm (400 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD485506. Type of Surface Mount Device PD485506G5-7JF: 44-pin plastic TSOP (II) (10.16 mm (400)) 7. Example of Stamping Letter E in the fifth character position ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...