MC9328MXLDVH20 Freescale Semiconductor, Inc, MC9328MXLDVH20 Datasheet
MC9328MXLDVH20
Related parts for MC9328MXLDVH20
MC9328MXLDVH20 Summary of contents
Page 1
... Mold Array Process-Ball Grid Array (MAPBGA) or 225-pin PBGA package. Figure 1 shows the functional block diagram of the MC9328MXL. © Freescale Semiconductor, Inc., 2004. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice. ...
Page 2
Introduction JTAG/ICE Connectivity MMC/SD Memory Stick® Host Controller SPI 1 and SPI 2 UART 1 UART 2 SSI USB Device Figure 1. MC9328MXL Functional Block Diagram 1.1 Conventions This document uses the following conventions: • ...
Page 3
Features To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the following: • ARM920T™ Microprocessor Core • AHB to IP Bus Interfaces (AIPIs) • External Interface Module (EIM) • SDRAM Controller (SDRAMC) ...
Page 4
Introduction 1.4 Revision History Table 1 provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes. Table 1. MC9328MXL Data Sheet Revision History Rev. 5 Revision Location Throughout Section 3.3, “Power ...
Page 5
... Standard Pb-free Standard - Pb-free O O Standard - Pb-free O O Standard Pb-free - Standard Pb-free MC9328MXL Advance Information, Rev. 5 Introduction Order Number MC9328MXLCVH15(R2) MC9328MXLCVM15(R2) MC9328MXLVH20(R2) MC9328MXLVM20(R2) MC9328MXLDVH20(R2) MC9328MXLDVM20(R2) MC9328MXLCVF15(R2) MC9328MXLCVP15(R2) MC9328MXLVF20(R2) MC9328MXLVP20(R2) MC9328MXLDVF20(R2) MC9328MXLDVP20(R2) 5 ...
Page 6
Signals and Connections 2 Signals and Connections Table 3 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to. Signal Name A[24:0] Address bus signals ...
Page 7
Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name CSD1 SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected can be used as ...
Page 8
Signals and Connections Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are ...
Page 9
Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name SPI2_SS SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and ...
Page 10
Signals and Connections Table 3. MC9328MXL Signal Descriptions (Continued) Signal Name UART1_RTS Request to Send UART1_CTS Clear to Send UART2_RXD Receive Data UART2_TXD Transmit Data UART2_RTS Request to Send UART2_CTS Clear to Send UART2_DSR Data Set Ready UART2_RI Ring Indicator ...
Page 11
... This section contains the electrical specifications and timing diagrams for the MC9328MXL processor. 3.1 Maximum Ratings Table 4 provides information on maximum ratings. Rating Supply voltage Maximum operating temperature range MC9328MXLVH20/MC9328MXLVM20/ MC9328MXLVF20/MC9328MXLVP20 Maximum operating temperature range MC9328MXLDVH20/MC9328MXLDVM20/ MC9328MXLDVF20/MC9328MXLDVP20 Maximum operating temperature range MC9328MXLCVH15/MC9328MXLCVM15/ MC9328MXLCVF15/MC9328MXLCVP15 ESD at human body model (HBM) ESD at machine model (MM) Latch-up current Storage temperature Power Consumption 1 ...
Page 12
Specifications 3.2 Recommended Operating Range Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MXL has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All ...
Page 13
Table 6. Maximum and Minimum DC Characteristics (Continued) Number or Symbol Sidd Standby current 4 (Core = 150 MHz, QVDD = 2.0V, temp = 55 V Input high voltage IH V Input low voltage IL V Output high voltage (I ...
Page 14
Specifications Table 8. 32k/16M Oscillator Signal Timing (Continued) Parameter EXTAL32k startup time EXTAL16M input jitter (peak to peak) EXTAL16M startup time 3.6 Embedded Trace Macrocell All registers in the ETM9 are programmed through a JTAG interface. The interface is an ...
Page 15
Table 9. Trace Port Timing Diagram Parameter Table (Continued) Ref Parameter No. 3a Clock rise time 3b Clock fall time 4a Output hold time 4b Output setup time Freescale Semiconductor 1.8V ± 0.10V Minimum Maximum – 4 – 3 2.28 ...
Page 16
Specifications 3.7 DPLL Timing Specifications Parameters of the DPLL are given in Table 10. In this table, T pre-divider and T is the output double clock period. dck Parameter Reference clock freq range Pre-divider output clock freq range Double clock ...
Page 17
Reset Module The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4. Be aware that NVDD must ramp least 1.8V before QVDD is powered up to ...
Page 18
Specifications RESET_IN HRESET RESET_OUT 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN Table 11. Reset Module Timing Parameter Table Ref Parameter No. 1 Width of input POWER_ON_RESET 2 Width of internal POWER_ON_RESET (CLK32 at 32 kHz ...
Page 19
External Interface Module The External Interface Module (EIM) handles the interface to devices external to the MC9328MXL, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and ...
Page 20
Specifications Ref No. Parameter 1a Clock fall to address valid 1b Clock fall to address invalid 2a Clock fall to chip-select valid 2b Clock fall to chip-select invalid 3a Clock fall to Read (Write) Valid 3b Clock fall to Read ...
Page 21
DTACK Signal Description The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated ...
Page 22
Specifications HCLK CS5 RW OE EXT_DTACK (WAIT) INT_DTACK Figure 7. DTACK Timing, WSC=111111, DTACK_sel=1 Table 14. Access Cycle Timing Parameters Ref Characteristic No. 1 External DTACK input setup from CS5 asserted Note the number of wait states ...
Page 23
EIM External Bus Timing The timing diagrams in this section show the timing of accesses to memory or a peripheral. hclk hsel_weim_cs[0] htrans Seq/Nonseq hwrite haddr hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Address weim_cs weim_r/w weim_lba weim_oe weim_eb ...
Page 24
Specifications hclk hsel_weim_cs[0] htrans Nonseq hwrite Write haddr hready hwdata Last Valid Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Address weim_cs[0] weim_r/w weim_lba weim_oe weim_eb weim_data_out Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF 24 V1 ...
Page 25
Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[0] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address ...
Page 26
Specifications hclk hsel_weim_cs[0] htrans Nonseq hwrite Write haddr V1 hready hwdata Last Valid Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[0] weim_r/w weim_lba weim_oe weim_eb weim_data_out Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 26 ...
Page 27
Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[3] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address ...
Page 28
Specifications hclk hsel_weim_cs[3] htrans Nonseq hwrite Write haddr V1 hready hwdata Last Valid Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[3] weim_r/w weim_lba weim_oe weim_eb weim_data_out] Last Valid Data Figure 13. WSC = 3, WEA = 1, WEN = ...
Page 29
Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address ...
Page 30
Specifications hclk hsel_weim_cs[2] htrans Nonseq hwrite Write haddr V1 hready Last Valid hwdata Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 15. WSC = 3, WEA = 2, WEN = ...
Page 31
Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address ...
Page 32
Specifications hclk hsel_weim_cs[2] htrans Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF 32 Last ...
Page 33
Nonseq hwrite Write haddr V1 hready Last Valid hwdata Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 18. WSC = 2, WWS = 1, WEA = 1, ...
Page 34
Specifications hclk hsel_weim_cs[2] htrans Nonseq hwrite Write haddr V1 hready Last Valid hwdata Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 19. WSC = 1, WWS = 2, WEA = ...
Page 35
Nonseq Read hwrite haddr V1 hready hwdata weim_hrdata Last Valid Data weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in weim_data_out Figure 20. WSC = 2, WWS = 2, WEA = ...
Page 36
Specifications hclk hsel_weim_cs[2] htrans Nonseq hwrite Read haddr V1 hready hwdata weim_hrdata Last Valid Data weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in weim_data_out Figure 21. WSC = 2, WWS = 1, WEA ...
Page 37
Nonseq hwrite Write haddr V1 hready hwdata Last Valid Data weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs weim_r/w weim_lba weim_oe weim_eb weim_data_out Last Valid Data Figure 22. WSC = 2, CSA = 1, WWS = 1, ...
Page 38
Specifications hclk hsel_weim_cs[4] htrans Nonseq hwrite Read haddr V1 hready hwdata weim_hrdata weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[4] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in weim_data_out Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF 38 Nonseq Write ...
Page 39
Nonseq hwrite Read haddr V1 hready weim_hrdata Last Valid Data weim_hready weim_bclk weim_addr Last Valid weim_cs[4] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = ...
Page 40
Specifications hclk hsel_weim_cs[4] htrans Nonseq hwrite Read haddr V1 hready hwdata weim_hrdata Last Valid Data weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[4] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_data_in weim_data_out Figure 25. WSC = 2, OEA = 2, WEA ...
Page 41
Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk weim_addr] Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 26. WSC = 3, SYNC = 1, A.HALF/E.HALF Freescale Semiconductor Nonse Read V5 ...
Page 42
Specifications hclk hsel_weim_cs[2] htrans Nonseq hwrite Read haddr V1 hready weim_hrdata Last Valid Data weim_hready weim_bclk weim_addr Last Valid Addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 27. WSC = 2, SYNC = 1, DOL = ...
Page 43
Nonseq hwrite Read haddr V1 hready weim_hrdata Last Valid Data weim_hready weim_bclk weim_addr Last Valid weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 28. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF ...
Page 44
Specifications hclk hsel_weim_cs[2] Non htrans seq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk weim_addr Last weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 29. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, ...
Page 45
Non htrans seq hwrite Read haddr V1 hready weim_hrdata weim_hready weim_bclk Last weim_addr weim_cs[2] weim_r/w weim_lba weim_oe weim_eb (EBC=0) weim_eb (EBC=1) weim_ecb weim_data_in Figure 30. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD ...
Page 46
Specifications 3.10 SPI Timing Diagrams To utilize the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) ...
Page 47
SS (input) 6 SCLK, MOSI, MISO Figure 35. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Table 15. Timing Parameter Table for Figure 31 through Figure 35 Ref Parameter No. 1 SPI_RDY to SS output low 2 SS ...
Page 48
Specifications Table 16. LCDC SCLK Timing Parameter Table Ref No. Parameter 1 SCLK to LD valid T1 VSYN T2 HSYN OE LD[15:0] Line Y T5 HSYN SCLK OE LD[15:0] VSYN Figure 37. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table ...
Page 49
Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued) Symbol Description T7 End beginning of HSYN T8 SCLK to valid LD data T9 End of HSYN idle2 to VSYN edge (for non-display region) T9 End of ...
Page 50
Specifications 3.12 Multimedia Card/Secure Digital Host Controller The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the ...
Page 51
Command Response Timing on MMC/SD Bus The card identification and card operation conditions timing are processed in open-drain mode. The card response to the host command starts after exactly N SET_RCA is also processed in the open-drain mode. The ...
Page 52
Specifications Host Command CMD S T Content CMD S T Content Host Command CMD S T Content Figure 40. Timing Diagrams at Data Transfer Mode Figure 41 on page 53 shows basic read operation timing read operation, the ...
Page 53
CMD S T DAT Host Command CMD Content S T CRC DAT Z****Z CMD S T DAT Figure 42 shows the basic write operation timing. As with the read operation, after the card response, the data ...
Page 54
Specifications 54 Figure 42. Timing Diagrams at Data Write MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor ...
Page 55
The stop transmission command may occur when the card is in different states. Figure 43 shows the different scenarios on the bus. Figure 43. Stop Transmission During Different Scenarios Freescale Semiconductor MC9328MXL Advance Information, Rev. 5 Specifications 55 ...
Page 56
Specifications Table 20. Timing Values for Figure 39 through Figure 43 Parameter MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Command read cycle Command-command ...
Page 57
CMD Content S T CRC DAT[1] Interrupt Period For 4-bit DAT[1] For 1-bit ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this mode, the block temporarily pauses the data transfer ...
Page 58
Specifications MS_SCLKI MS_SCLKO MS_BS MS_SDIO(output) MS_SDIO (input) (RED bit = 0) MS_SDIO (input) (RED bit = 1) Table 21. MSHC Signal Timing Parameter Table Ref No. 1 MS_SCLKI frequency 2 MS_SCLKI high pulse width 3 MS_SCLKI low pulse width 4 ...
Page 59
Table 21. MSHC Signal Timing Parameter Table (Continued) Ref No MS_BS delay time 12 MS_SDIO output delay time 13 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0) 14 MS_SDIO input hold time for MS_SCLKO ...
Page 60
Specifications 3.14 Pulse-Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output ...
Page 61
Active which sets up the status register read. The bank and row addresses are driven during this command. The third command of the triplet is Read. Bank and column addresses are driven on the address bus during this command. Data ...
Page 62
Specifications Table 23. SDRAM Timing Parameter Table (Continued) Ref Parameter No. 3H CS, RAS, CAS, WE, DQM hold time 4S Address setup time 4H Address hold time 5 SDRAM access time ( SDRAM access time (CL = ...
Page 63
SDCLK 1 CS RAS CAS WE 4 ADDR / BA DQ DQM Figure 49. SDRAM/SyncFlash Write Cycle Timing Diagram Table 24. SDRAM Write Timing Parameter Table Ref Parameter No. 1 SDRAM clock high-level width 2 SDRAM clock low-level width 3 ...
Page 64
Specifications Table 24. SDRAM Write Timing Parameter Table (Continued) Ref Parameter No. 8 Data setup time 9 Data hold time 1. Precharge cycle timing is included in the write timing diagram and t = SDRAM clock cycle time. ...
Page 65
Table 25. SDRAM Refresh Timing Parameter Table (Continued) Ref Parameter No. 3 SDRAM clock cycle time 4 Address setup time 5 Address hold time 6 Precharge cycle period 7 Auto precharge command period 1. t and t = SDRAM clock ...
Page 66
Specifications 3.16 USB Device Port Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the ...
Page 67
Table 26. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX) Ref No. Parameter USBD_VMO low to VMO_ROE USBD_ROE deactivated (includes SE0 SE0 interval of EOP FEOPT Data ...
Page 68
Specifications 2 3. Module 2 The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA SCL Ref No. Parameter 1 Hold time (repeated) START condition 2 ...
Page 69
STCK Output STFS (bl) Output STFS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 55. SSI Transmitter Internal Clock Timing Diagram SRCK Output SRFS (bl) Output SRFS (wl) Output SRXD Input Figure 56. SSI ...
Page 70
Specifications STCK Input STFS (bl) Input STFS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 57. SSI Transmitter External Clock Timing Diagram SRCK Input SRFS (bl) Input SRFS (wl) Input SRXD Input Figure 58. ...
Page 71
Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued) Ref No. Parameter 4 STCK high to STFS (bl) low 5 SRCK high to SRFS (bl) low 6 STCK high to STFS (wl) high 7 SRCK high to SRFS ...
Page 72
Specifications Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued) Ref No. Parameter 28 STCK high to STXD high impedance 29 SRXD setup time before SRCK low 30 SRXD hole time after SRCK low Synchronous Internal Clock Operation ...
Page 73
Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref Parameter No. 9 SRCK high to SRFS (wl) low 10 STCK high to STXD valid from high impedance 11a STCK high to STXD high 11b STCK high to ...
Page 74
Specifications Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref Parameter No. Synchronous Internal Clock Operation (Port B Alternate Function 31 SRXD setup before STCK falling 32 SRXD hold after STCK falling Synchronous External Clock Operation (Port ...
Page 75
CMOS Sensor Interface The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing, a control register for statistic data generation, a status register, interface logic × statistic data FIFO. ...
Page 76
Specifications 1 VSYNC HSYNC PIXCLK DATA[7:0] Figure 60. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 31. Gated Clock Mode Timing Parameters Ref No. 1 csi_vsync to csi_hsync 2 csi_hsync to ...
Page 77
Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive ...
Page 78
Specifications VSYNC PIXCLK DATA[7:0] Figure 62. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 32. Non-Gated Clock Mode Parameters Ref No. 1 csi_vsync to csi_pixclk 2 csi_d setup time 3 csi_d ...
Page 79
Freescale Semiconductor MC9328MXL Advance Information, Rev. 5 Pin-Out and Package Information 79 ...
Page 80
Pin-Out and Package Information 80 MC9328MXL Advance Information, Rev. 5 Freescale Semiconductor ...
Page 81
MAPBGA 256 Package Dimensions Figure 63 illustrates the 256 MAPBGA 14 mm × × 1.30 mm package, which has 0.8 mm spacing between the pads. The device designator for the MAPBGA package is VH. TOP VIEW BOTTOM ...
Page 82
Pin-Out and Package Information 4.2 PBGA 225 Package Dimensions Figure 64 illustrates the 225 PBGA 13 mm × × 0.8 mm package. TOP VIEW BOTTOM VIEW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS AND TOLERANCES PER ...
Page 83
Freescale Semiconductor NOTES MC9328MXL Advance Information, Rev ...
Page 84
... Learn More: For more information about Freescale products, please visit www.freescale.com. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The ARM POWERED logo is the registered trademark of ARM Limited ...