K4N26323AE-GC20 Samsung, K4N26323AE-GC20 Datasheet

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... K4N26323AE-GC 128Mbit GDDR2 SDRAM with Differential Data Strobe and DLL Samsung Electronics reserves the right to change products or specification without notice 32Bit x 4 Banks GDDR2 SDRAM Revision 1.7 January 2003 - 1 - 128M GDDR2 SDRAM Rev. 1.7 (Jan. 2003) ...

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... K4N26323AE-GC Revision History Revision 1.7 (January 23, 2003) - Changed the device name from GDDR-II to GDDR2 Revision 1.6 (December 18, 2002) - Typo corrected Revision 1.5 (December 4, 2002) - Typo corrected Revision 1.4 (November 12, 2002) - Changed the device name from DDR-II to GDDR-II - Typo corrected Revision 1.3 (November 8, 2002) - Typo corrected Revision 1.2 (November 5, 2002) ...

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... K4N26323AE-GC Revision 0.5 (January 2002) - Eliminated DLLEN pin - Power-up sequence Revision 0.4 (January 2002) - Changed EMRS Table - Changed Self-Refresh exit mode - Changed On-die Termination Control - Changed OCD Control method - Power-up sequence Revision 0.3 (December 2001) - Noted the ball names changed from DDR-1 and exchanged DQS and /DQS ball location. ...

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... Burst type : sequential only • Additive latency (AL): 0,1(clock) • Read latency(RL) : CL+AL • Write latency(WL) : AL+1 ORDERING INFORMATION Part NO. K4N26323AE-GC20 K4N26323AE-GC22 K4N26323AE-GC25 GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank GDDR2 SDRAM The 4Mx32 GDDR2 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 1,048,976 words by 32 bits, fabricated with SAMSUNG extremely high performance up to 4GB/s/chip ...

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... K4N26323AE-GC PIN CONFIGURATION Normal Package (Top View DQS0 /DQS0 VSSQ C DQ4 DM0 VDDQ D DQ6 DQ5 VSSQ E DQ7 VDDQ VDD F DQ17 DQ16 VDDQ G DQ19 DQ18 VDDQ H DQS2 /DQS2 NC J DQ20 DM2 VDDQ K DQ21 DQ22 VDDQ L DQ23 A3 VDD VREF A2 A10 M A0 ...

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... K4N26323AE-GC PIN CONFIGURATION Mirror Package (Top View DQS3 /DQS3 VSSQ C DQ27 DM3 VDDQ D DQ25 DQ26 VSSQ E DQ24 VDDQ VDD F DQ14 DQ15 VDDQ G DQ12 DQ13 VDDQ H DQS1 /DQS1 NC J DQ11 DM1 VDDQ K DQ10 DQ9 VDDQ L DQ8 A4 VDD M VREF A8/ Under consideration ...

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... K4N26323AE-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive CK, CK Input edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both direc- tions of crossing). ...

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... K4N26323AE-GC BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select iCK ADDR LCKE LRAS LCBR iCK CKE * iCK : internal clock DQS , DQS Input Buffer CK, CK Input DLL Data Input Register Serial to parallel Column Decoder Latency & Burst Length ...

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... K4N26323AE-GC FUNTIONAL DESCRIPTION Simplified State Diagram Power Applied Power DLL On Enable Precharge PREALL MRS EMRS Write A PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh REFS ...

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... K4N26323AE-GC Power-Up Sequence GDDR2 SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Power Up Sequence - Apply Power and Keep CKE at low state. (All other inputs may be undefined) - Apply VDD before VDDQ. - Apply VDDQ before VREF. - Start low frequency clock(100MHz) - The minimum of 200us after stable power and clock (CK, /CK), apply NOP and take CKE to be high ...

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... K4N26323AE-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR2 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR2 SDRAM useful for variety of dif- ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...

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... K4N26323AE-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis- ter) ...

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... K4N26323AE-GC DQS 500MHz Differential DQS * To support existing DDR-I user , single DQS is supported under 400MHz by EMRS option, When single DQS is selected, 4 /DQS pins should be connected to VREF. Differntial DQS Timing (CL5, BL4 CK, CK CMD READ DQS DQS DQ Single DQS Timing (CL5, BL4) ...

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... K4N26323AE-GC Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 and BA1 are used to select the desired bank. The row address A0 through A11 is used to deter- mine which row to activate in the selected bank ...

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... K4N26323AE-GC Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in GDDR2 SDRAM. In this operation, the GDDR2 SDRAM allows a CAS read or write command to be issued tRCDmin or 1 tCK ear- lier than tRCDmin after the RAS bank activate command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device ...

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... K4N26323AE-GC Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL) ...

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... K4N26323AE-GC Burst Read followed by Burst Write : (AL+ CK, CK Post CAS CMD NOP READ A DQS RL =8 DQ’s Seamless Burst Read Operation CK, CK Post CAS NOP CMD READ A0 DQS DQ’s The seamless burst read operation is supported by enabling a read command at every other clock. This operation is allowed regardless of same or different banks as long as the banks are activated ...

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... K4N26323AE-GC Burst Write Operation The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Latency(AL) plus one and is equal to (AL + 1). first rising edge of the clock and at the first falling edge of the clock. The tDQSS specification must be satisfied for write cycles ...

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... K4N26323AE-GC Seamless Burst Write Operation : CK, CK Post CAS CMD NOP WRITE A DQS DQ’s The seamless burst write operation is supported by enabling a write command every other clock. This operation is allowed regardless of same or different banks as long as the banks are activated ...

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... K4N26323AE-GC Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A8, BA0 and BA1 are used to define which bank to precharge when the command is issued ...

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... K4N26323AE-GC Burst Read Operation Followed by Precharge (AL=1, CL= CK, CK Posted CAS CMD Precharge A READ A DQS DQ’s Burst Write followed by Precharge For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (t precharge command ...

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... K4N26323AE-GC DM FUNCTION The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the Data Mask is activated (DM high) during write operation the write data is masked immediately (DM to Data-mask Latency is zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge. ...

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... K4N26323AE-GC Burst Read with Auto Precharge high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The GDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2)cycles later from the read with Auto Precharge command, when tRAS(min) is satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto Pre- charge operation will be delayed until tRAS(min) is satisfied ...

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... K4N26323AE-GC Burst Write with Auto-Precharge high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The GDDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). Interruption of the Write with Auto-Precharge function is prohibited. Active command of same bank can be issued WL+tWR+tRP+BL/2 cycles later from the Write with Auto-Precharge command ...

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... K4N26323AE-GC Automatic Refresh Command (CAS Before RAS Refresh) When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the GDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (t before the Auto Refresh Command (CBR) can be applied ...

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... K4N26323AE-GC Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE ...

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... K4N26323AE-GC On-Die Termination All pins except ZQ, CKE Pins adopt on-die termination to improve signal integrity of channel. The On-Die Termination should be controlled by EMRS command at low frequency clock (<100Mhz). The On-Die Termination control command should be issued before issuing DLLON command by EMRS or simultaneously to guarantee stable channel condition of /CK and CK pins ...

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... K4N26323AE-GC The On-die Termination on/off status on DRAM is in accompany with DRAM operation mode. Power consumption by On-die termination can be reduced by issuing power down mode. Mode Self_refresh Power Down Active All banks idle READ * A10 in EMRS code is used for On-Die Termination of DQ’s off when Read data comes out ...

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... K4N26323AE-GC The On-die Termination for external two bank system with self-calibration code (A3 The external resistor (Rref) is equal to 2X the number of shared DRAM’s on one channel X target termination value of DQ channel. The following figure is represented the typical two bank system having on-die termination. 4 DRAM’s share one channel for CMD and ADD pins and 2 DRAM’ ...

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... K4N26323AE-GC 4. Command Truth Table. Function Previous Cycle Mode Register Set H Extended Mode Register Set H Auto (CBR) Refresh H Entry Self Refresh H L Exit Self Refresh L Single Bank Precharge H Precharge all Banks H Bank Activate H Write H Write with Auto Precharge H Read H Read with Auto-Precharge ...

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... K4N26323AE-GC 5. Clock Enable (CKE) Truth Table CKE Current State Previous Current Cycle Cycle Self Refresh Power Down All Banks Idle Any State other H L than listed ...

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... K4N26323AE-GC ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...

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... K4N26323AE-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I CC2 in Power-down mode Precharge Standby Current I CC2 in Non Power-down mode Active Standby Current I CC3 power-down mode Active Standby Current in I CC3 in Non Power-down mode ...

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... K4N26323AE-GC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.5V Parameter Input capacitance ( CK ...

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... K4N26323AE-GC AC CHARACTERISTICS Parameter CL=7 CK cycle time CL=6 CL=5 CK high width CK low width DQS out access time from CK Data strobe edge to Dout edge Read preamble Read postamble DQS in/out high level DQS in/out low level Address and Control input setup Address and Control input hold ...

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... K4N26323AE-GC Note The JEDEC DDR-II specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...

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... K4N26323AE-GC AC CHARACTERISTICS (I) Parameter Row cycle time tRC Refresh row cycle time tRFC Row active time tRAS RAS to CAS delay for Read tRCDRD RAS to CAS delay for Write tRCDWR Row precharge time tRP Row active to Row active tRRD Last data in to Row precharge ...

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... K4N26323AE-GC PACKAGE DIMENSIONS (FBGA) 0.45 0.25 1.40 A1 INDEX MARK 13.0 <Top View> 0.8x11=8.8 0.10 Max 0 ± 0. ± 0.05 Max <Bottom View> 128M GDDR2 SDRAM 13.0 A1 INDEX MARK 0.8 0.40 0.40 Rev. 1.7 (Jan. 2003) Unit : mm ...

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... K4N26323AE-GC IBIS: I/V Characteristics for Input and Output Buffers The termination resistor of the controller must be set to a appropriate value to satisfy output voltage level if the ODT of DRAM is on. 30 ohm Driver @ ODT OFF 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. ...

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... K4N26323AE-GC Pulldown Current (mA) Typical Voltage (V) 0.0 0.0 0.1 4.4 0.2 8.1 0.3 11.2 0.4 13.8 0.5 15.9 0.6 17.4 0.7 18.4 0.8 19.0 0.9 19.4 1.0 19.7 1.1 19.8 1.2 20.0 1.3 20.1 1.4 20.2 1.5 20.2 1.6 20.3 1.7 20.4 1.8 20.4 1.9 20.5 Temperature (Tj) 50 °C Typical 100 °C Minimum 0 °C Maximum Vdd/Vddq Typical 2.5V Minimum 2.4V Maximum 2.6V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum 0.0 0.0 3.0 6.3 5.5 11.8 7.6 16.4 9.3 20.4 10.6 23.5 11.5 25.9 12.1 27.5 12.4 28.4 12.6 29.0 12.8 29.3 12.9 29.5 13.0 29.7 13.1 29.9 13.1 30.0 13.2 30.1 13.2 30.2 13.3 30.3 13.3 30.3 13.5 30 128M GDDR2 SDRAM Pullup Current (mA) Typical Minimum 0.0 0.0 -3.6 -2.5 -6.9 -4.6 -9.7 -6.6 -12.2 -8.2 -14.3 -9.6 -16.1 -10.7 -17.4 -11.6 -18.4 -12.3 -19.1 -12.8 -19.7 -13.2 -20.3 -13.6 -20.7 -13.9 -21.1 -14.2 -21.5 -14.5 -21.8 -14.7 -22.1 -14.9 -22.4 -15.1 -22.6 -15.3 -22.9 -15.5 Rev. 1.7 (Jan. 2003) Maximum 0 ...

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... K4N26323AE-GC 30 ohm Driver @ ODT 60 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT 60 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. ...

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... K4N26323AE-GC Pulldown Current (mA) Typical Voltage (V) 0.0 -14.4 0.1 -8.5 0.2 -3.2 0.3 1.6 0.4 5.8 0.5 9.5 0.6 12.7 0.7 15.3 0.8 17.5 0.9 19.6 1.0 21.5 1.1 23.3 1.2 25.1 1.3 26.8 1.4 28.6 1.5 30.3 1.6 32.0 1.7 33.7 1.8 35.4 1.9 37.1 Temperature (Tj) 50 °C Typical 100 °C Minimum 0 °C Maximum Vdd/Vddq Typical 2.5V Minimum 2.4V Maximum 2.6V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum -11.5 -17.1 -7.1 -9.0 -3.3 -1.8 0.2 4.7 3.3 10.4 5.9 15.4 8.2 19.7 10.2 23.1 11.9 25.9 13.5 28.3 15.1 30.5 16.6 32.6 18.1 34.7 19.6 36.7 21.0 38.7 22.4 40.7 23.9 42.7 25.3 44.6 26.7 46.6 28.1 48 128M GDDR2 SDRAM Pullup Current (mA) Typical Minimum 14.9 11.9 9.7 8.1 4.8 4.6 0.4 1.3 -3.7 -1.7 -7.4 -4.4 -10.8 -6.9 -13.7 -9.2 -16.4 -11.2 -18.8 -13.2 -21.0 -15.0 -23.2 -16.8 -25.3 -18.5 -27.3 -20.2 -29.4 -21.8 -31.3 -23.5 -33.3 -25.1 -35.2 -26.6 -37.1 -28.2 -39.0 -29.8 Rev. 1.7 (Jan. 2003) Maximum 18 ...

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... K4N26323AE-GC 30 ohm Driver @ODT 120 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT 120 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a ...

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... K4N26323AE-GC Pulldown Current (mA) Typical Voltage (V) 0.0 -7.2 0.1 -2.1 0.2 2.5 0.3 6.4 0.4 9.8 0.5 12.7 0.6 15.1 0.7 16.9 0.8 18.3 0.9 19.5 1.0 20.6 1.1 21.6 1.2 22.6 1.3 23.5 1.4 24.5 1.5 25.4 1.6 26.3 1.7 27.1 1.8 28.0 1.9 28.9 Temperature (Tj) 50 °C Typical 100 °C Minimum 0 °C Maximum Vdd/Vddq Typical 2.5V Minimum 2.4V Maximum 2.6V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum -5.8 -8.6 -2.1 -1.4 1.1 5.0 3.9 10.6 6.3 15.4 8.3 19.5 9.9 22.8 11.2 25.3 12.2 27.2 13.1 28.7 14.0 30.0 14.8 31.2 15.6 32.3 16.4 33.4 17.1 34.5 17.9 35.5 18.6 36.5 19.4 37.6 20.1 38.6 20.9 39 128M GDDR2 SDRAM Pullup Current (mA) Typical Minimum 7.6 6.1 3.1 2.9 -0.9 0.1 -4.6 -2.5 -7.9 -4.9 -10.8 -6.9 -13.4 -8.8 -15.5 -10.3 -17.3 -11.7 -18.9 -12.9 -20.4 -14.1 -21.7 -15.2 -23.0 -16.2 -24.2 -17.2 -25.4 -18.1 -26.6 -19.1 -27.7 -20.0 -28.8 -20.9 -29.9 -21.8 -31.0 -22.7 Rev. 1.7 (Jan. 2003) Maximum 9 ...

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... K4N26323AE-GC 45 ohm @ ODT OFF 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 45 ohm@ ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. ...

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... K4N26323AE-GC Pulldown Current (mA) Typical Voltage (V) 0.0 0.0 0.1 2.8 0.2 5.2 0.3 7.2 0.4 8.8 0.5 10.1 0.6 11.1 0.7 11.7 0.8 12.1 0.9 12.4 1.0 12.5 1.1 12.6 1.2 12.7 1.3 12.8 1.4 12.8 1.5 12.9 1.6 12.9 1.7 13.0 1.8 13.0 1.9 13.1 Temperature (Tj) 50 °C Typical 100 °C Minimum 0 °C Maximum Vdd/Vddq Typical 2.5V Minimum 2.4V Maximum 2.6V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum 0.0 0.0 1.9 4.0 3.5 7.5 4.9 10.5 5.9 13.0 6.8 15.0 7.3 16.5 7.7 17.5 7.9 18.1 8.0 18.4 8.1 18.7 8.2 18.8 8.3 18.9 8.3 19.0 8.4 19.1 8.4 19.2 8.4 19.2 8.5 19.3 8.5 19.3 8.6 19 128M GDDR2 SDRAM Pullup Current (mA) Typical Minimum 0.0 0.0 -2.2 -1.5 -4.2 -2.8 -6.0 -4.0 -7.5 -5.0 -8.8 -5.9 -9.8 -6.6 -10.6 -7.1 -11.2 -7.5 -11.7 -7.8 -12.1 -8.1 -12.4 -8.3 -12.7 -8.5 -12.9 -8.7 -13.1 -8.8 -13.3 -9.0 -13.5 -9.1 -13.7 -9.2 -13.8 -9.4 -14.0 -9.5 Rev. 1.7 (Jan. 2003) Maximum 0 ...

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... K4N26323AE-GC 45 ohm Driver @ODT 120 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 45 ohm@ODT 120 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a ...

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... K4N26323AE-GC Pulldown Current (mA) Typical Voltage (V) 0.0 -7.3 0.1 -3.7 0.2 -0.5 0.3 2.4 0.4 4.8 0.5 7.0 0.6 8.8 0.7 10.2 0.8 11.4 0.9 12.5 1.0 13.5 1.1 14.4 1.2 15.4 1.3 16.3 1.4 17.1 1.5 18.0 1.6 18.9 1.7 19.8 1.8 20.6 1.9 21.5 Temperature (Tj) 50 °C Typical 100 °C Minimum 0 °C Maximum Vdd/Vddq Typical 2.5V Minimum 2.4V Maximum 2.6V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum -5.8 -8.6 -3.2 -3.7 -0.9 0.7 1.2 4.6 2.9 8.0 4.4 11.0 5.7 13.5 6.8 15.4 7.7 16.9 8.6 18.2 9.4 19.3 10.7 20.5 10.9 21.5 11.6 22.6 12.4 23.6 13.1 24.6 13.8 25.6 14.6 26.6 15.3 27.6 16.0 28 128M GDDR2 SDRAM Pullup Current (mA) Typical Minimum 7.6 6.1 4.6 3.9 1.8 1.9 -0.8 0.0 -3.2 -1.7 -5.3 -3.2 -7.1 -4.6 -8.8 -5.8 -10.2 -7.0 -11.5 -8.0 -12.7 -9.0 -13.9 -9.9 -15.0 -10.8 -16.0 -11.7 -17.1 -12.5 -18.1 -13.4 -19.1 -14.2 -20.1 -15.0 -21.1 -15.8 -22.1 -16.7 Rev. 1.7 (Jan. 2003) Maximum 9 ...

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... K4N26323AE-GC 60 ohm @ODT OFF 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 60 ohm@ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a. ...

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... K4N26323AE-GC Pulldown Current (mA) Typical Voltage (V) 0.0 0.0 0.1 2.0 0.2 3.7 0.3 5.1 0.4 6.3 0.5 7.3 0.6 7.9 0.7 8.4 0.8 8.7 0.9 8.8 1.0 8.9 1.1 9.0 1.2 9.1 1.3 9.1 1.4 9.2 1.5 9.2 1.6 9.2 1.7 9.3 1.8 9.3 1.9 9.3 Temperature (Tj) 50 °C Typical 100 °C Minimum 0 °C Maximum Vdd/Vddq Typical 2.5V Minimum 2.4V Maximum 2.6V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum 0.0 0.0 1.4 2.9 2.5 5.4 3.5 7.5 4.2 9.3 4.8 10.7 5.2 11.8 5.5 12.5 5.7 12.9 5.8 13.2 5.8 13.3 5.9 13.4 5.9 13.5 5.9 13.6 6.0 13.6 6.0 13.7 6.0 13.7 6.0 13.8 6.1 13.8 6.2 13 128M GDDR2 SDRAM Pullup Current (mA) Typical Minimum 0.0 0.0 -1.6 -1.1 -3.1 -2.1 -4.4 -2.9 -5.5 -3.7 -6.4 -4.3 -7.2 -4.8 -7.7 -5.2 -8.2 -5.5 -8.5 -5.7 -8.8 -5.9 -9.0 -6.0 -9.2 -6.2 -9.4 -6.3 -9.5 -6.4 -9.7 -6.5 -9.8 -6.6 -9.9 -6.7 -10.1 -6.8 -10.2 -6.9 Rev. 1.7 (Jan. 2003) Maximum 0 ...

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... K4N26323AE-GC 60 ohm Driver @ODT 120 ohm Fix. 1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 60 ohm@ODT 120 ohm fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a ...

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... K4N26323AE-GC Pulldown Current (mA) Typical Voltage (V) 0.0 -7.3 0.1 -4.5 0.2 -2.0 0.3 0.3 0.4 2.3 0.5 4.1 0.6 5.6 0.7 6.9 0.8 8.0 0.9 9.0 1.0 9.9 1.1 10.8 1.2 11.7 1.3 12.6 1.4 13.5 1.5 14.2 1.6 15.2 1.7 16.1 1.8 16.9 1.9 17.8 Temperature (Tj) 50 °C Typical 100 °C Minimum 0 °C Maximum Vdd/Vddq Typical 2.5V Minimum 2.4V Maximum 2.6V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum -5.8 -8.7 -3.7 -4.9 -1.9 -1.4 -0.2 1.6 1.2 4.3 2.5 6.7 3.6 8.7 4.6 10.4 5.5 11.7 6.3 12.9 7.0 14.0 7.8 15.1 8.5 16.1 9.3 17.1 10.0 18.1 10.7 19.1 11.4 20.1 12.1 21.1 12.8 22.1 13.6 23 128M GDDR2 SDRAM Pullup Current (mA) Typical Minimum 7.6 6.1 5.2 4.3 2.9 2.7 0.8 1.1 -1.1 -0.3 -2.9 -1.6 -4.5 -2.8 -5.9 -3.9 -7.1 -4.9 -8.3 -5.9 -9.4 -6.8 -10.5 -7.6 -11.5 -8.5 -12.5 -9.3 -13.5 -10.1 -14.5 -10.9 -15.5 -11.7 -16.4 -12.5 -17.4 -13.3 -18.3 -14.1 Rev. 1.7 (Jan. 2003) Maximum 9 ...