AM79C987JC Advanced Micro Devices, AM79C987JC Datasheet
AM79C987JC
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AM79C987JC Summary of contents
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... The device is fabricated in CMOS technology and requires a single +5 V supply. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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BLOCK DIAGRAM CK Clock/ Reset RST D7–0 CS C/D Bus RD Interface WR RDY INT RELATED AMD PRODUCTS Part No. Description Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX+) Am79C90 CMOS Local Area Network Controller for Ethernet ...
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CONNECTION DIAGRAM PLCC SCLK CRS Am79C987 STR ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM79C987 DEVICE NUMBER/DESCRIPTION Am79C987 Hardware Implemented Management Information Base (HIMIB) Valid ...
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PIN DESCRIPTION CK Clock Input CK is the master 20 MHz clock. The IMR+ device X must also be clocked with the identical clock signal. RST Reset Input, Active LOW Driving this pin LOW resets the internal logic of the ...
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CS Chip Select Input, Active LOW The chip-select input, when asserted, enables a read from or a write to the 8-bit parallel port of the HIMIB device. RDY Ready Output, Open Drain Ready is driven LOW at the start of ...
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AMD FUNCTIONAL DESCRIPTION Overview The functional specification of the HIMIB device is a su- perset of that defined by the Layer Management for 10 Mbyte/s Baseband Repeaters (IEEE802.3k), commonly referred to as the “Repeater Management Standard.” The HIMIB chip contains ...
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Microprocessor Interface Access to the HIMIB device’s on-chip registers is made via its simple processor interface which is designed to be used by a variety of available microprocessors. The bus interface is designed to be asynchronous and can be easily ...
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AMD C Command (C) Port Data (D) Port C Figure 1. Overview of HIMIB Register Definition An exception to the normal Command/Data Port access scheme, is the Status Register which is read directly by reading only ...
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For (Repeater Registers), the following registers are accessible: R[4:0] Register 10 Source Address Match (6-byte) 12 Total Octets (4-byte) 13 Transmit Collisions (4-byte) 16 Configuration Register 28 Version/Device ID 30 IMR+ Management Port Set Register 31 IMR+ ...
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AMD Table 1. Summary of All the HIMIB Device Registers Register Status Register Port/Register Bank P[4:0] Repeater Registers 0 Port Status Registers 1 Port Control Registers 2 Attribute Registers 16–23, 31 Note that all register locations listed as reserved and ...
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DETAILED REGISTER FUNCTIONS Status Register The HIMIB Status Register can be accessed at any time by reading the C Port. The 8-bit quantity read has the following format: C Port Read MSB Interrupt. This bit ...
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AMD Transmit Collisions P[4: R[4: Port Read Byte 0 bit 7 Byte 1 Byte 2 bit 31 Byte 3 MSB Transmit Collisions is a 4-byte read-only attribute that counts the number of transmit collisions this ...
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If a Get command is written to this register accidentally, the IMR+ device output will be retained in the Get regis- ter, however, the management Interface Error bit will be set in the Status Register. Writing to this register prior ...
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AMD AUI SQE Test Error P[4: R[4: This register is not valid for the IMR device (Am79C980). When the HIMIB device is interfaced with the IMR+ chip (Am79C981), this bit is set the ...
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TP Link State Change Interrupt Enable P[4: R[4: Setting any of the bits in this register causes the INT pin to be driven when there is a change in the Link Test State of the corresponding ...
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AMD Note that the contents of all attribute registers are main- tained during an external reset. These attributes and their definitions comply with the IEEE 802.3k Layer Management for 10 Mbyte/s Baseband Repeaters Repeater Management Standard. A brief summary of ...
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Frames Too Long P[4:0] = 16–23, 31, R[4: Port Read Byte 0 bit 7 Byte 1 Byte 2 bit 31 Byte 3 MSB “Frames Too Long” read-only attribute that counts the number of frames that ...
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AMD Data Rate Mismatches P[4:0] = 16–23, 31, R[4: Port Read Byte 0 bit 7 Byte 1 Byte 2 bit 31 Byte 3 MSB “Data Rate Mismatches” read-only attribute that counts the number of occurrences ...
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SYSTEMS APPLICATIONS Typical System Interface The block diagram on this page shows a typical system interface. A fully managed multiport repeater can be easily built by interfacing the HIMIB chip with the IMR+ Host System Bus Address Decode Data Buffer ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . ...
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SWITCHING CHARACTERISTICS Clock and Reset Timing Symbol Description tCK Clock Period tCKH Clock High tCKL Clock Low tCKR Clock Rise Time tCKF Clock Fall Time tRST Reset Pulse Width tRSTS Reset Input Setup Time with Respect to CK tRSTH Reset ...
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AMD SWITCHING CHARACTERISTICS (continued) Microprocessor Interface (MPI) Symbol Description tCDS C/D Setup Time with Respect to RD/WR Falling Edge tCDH C/D Hold Time with Respect to RD/WR Rising Edge CS Setup Time with Respect to tCSS RD/WR Falling Edge CS ...
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SWITCHING TEST LOADS Sense Point Pin Name All Outputs and I/O Pins except RDY, INT RDY, INT Normal and Three-State Outputs VCC ...
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AMD SWITCHING TEST LOADS (continued VDD 500 Device Pin 500 17305B-8 C. For Data Out (D7–0) Hold Only Am79C987 25 ...
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KEY TO SWITCHING WAVEFORMS WAVEFORM SWITCHING WAVEFORMS tCKH 3 tCKR RST 0.8 CK tCASET ACK COL DAT JAM INPUTS OUTPUTS Must be Will be ...
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AMD SWITCHING WAVEFORMS CK tSCKD SCLK tCRSTS CRS tSCKF tSCKD tSCKR tSID tSID tSOS tSOH Management Port Timing tCRSTH Port Activity Timing Am79C987 17305B-11 17305B-12 27 ...
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SWITCHING WAVEFORMS C/D tCDS CS tCSS RD, WR RDY D7–0 D7–0 Note: Refer to AMD’s IEEE 802.3 Repeater Technical Manual (PID #17314A) for more detailed access timing tRDYD ...
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APPENDIX A IMR+/HIMIB Security Features The Am79C981 Integrated Multiport Repeater Plus (IMR+) and the Am79C987 Hardware Implemented Management Information Base (HIMIB) Ethernet re- peater chip-set is capable of providing physical network security features. AMD will only make these features available ...
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... Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI , QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc ...
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