TMP91C630F TOSHIBA Semiconductor CORPORATION, TMP91C630F Datasheet
TMP91C630F
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TMP91C630F Summary of contents
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TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C630 ...
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Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Preface ...
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... TMP91C630 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. 2 Kbytes of boot ROM is built-in. The standard name of this microcontroller is TMP91C630F-7770 with ROM code (7770). The package of TMP91C630 is 100-pin flat type. The features are shown below. (1) High-speed 16-bit CPU (900/L1 CPU) ...
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Chip Select/Wait controller: 4 blocks (11) Interrupts: 35 interrupts 9 CPU interrupts: Software interrupt instruction and illegal instruction 19 internal interrupts: 7 priority levels are selectable. 7 external interrupts: 7 priority levels are selectable. (Level mode, rising edge mode ...
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ADTRG AN0~AN7 (PA0~PA7) VREFH 10-bit 8-ch VREFL AD AVCC converter AVSS Port Port Z PZ2 ( ) HWR PZ3 TXD0 (P80) RXD0 (P81) Serial I/O (channel 0) SCLK0/ (P82) CTS0 (P83) STS 0 TXD1 (P84) RXD1 ...
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... Pin Assignment and Pin Functions The Pin Assignment and Pin Functions of the TMP91C630F are showed in Figure 2.1.1. 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C630F. Pin Name Pin No. P27/A23 64 P26/A22 65 P25/A21 66 P24/A20 67 P23/A19 68 P22/A18 69 P21/A17 70 P20/A16 71 A15 72 A14 73 A13 74 A12 75 ...
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Pin Names and Functions The names of the Input/Output pins and their functions are described below. Table 2.2.1 to Table 2.2.3 show Pin name and functions. Table 2.2.1 Pin Names and Functions (1/3) Number Pin Names I/O of Pins ...
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Table 2.2.2 Pin Names and Functions (2/3) Number Pin Names I/O of Pins P73 1 I/O TA4IN Input INT3 Input P74 1 I/O TA5OUT Output P75 1 I/O INT4 Input P80 1 I/O TXD0 Output P81 1 I/O RXD0 Input ...
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Table 2.2.3 Pin Names and Functions (3/3) Number Pin Names I/O of Pins 1 Input BOOT 1 Input NMI AM0 to AM1 2 Input 1 Input RESET VREFH 1 Input VREFL 1 Input AVCC 1 I/O AVSS 1 X1/X2 2 ...
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Operation This section describes the basic components, functions and operation of the TMP91C630. Notes and restrictions which apply to the various items described here are outlined in section 7. Precautions and restrictions at the end of this databook. 3.1 ...
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Figure 3.1.1 shows the timing of a reset for the TMP91C630. Figure 3.1.1 TMP91C630 Reset Timing Example 91C630-9 Read Write TMP91C630 2003-07-22 ...
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Outline of Operation Modes There are multi-chip and multi-boot modes. Which mode is selected depends on the device’s pin state after a reset. Multi-chip mode: The device normally operations in this mode. After a reset, the device starts executing ...
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Memory Map Figure 3.3 memory map of the TMP91C630. Multi-chip mode 000000H Internal I/O (4 Kbytes) 000100H 001000H Internal RAM (6 Kbytes) 002800H External memory 01F800H Internal boot ROM (2 Kbytes) 01FFFFH External memory FFFF00H Vector table ...
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Triple Clock Function and Standby Function The TMP91C630 system clock block contains (1) Clock gearing system (2) Standby controller (3) Noise reducing circuit It can be used for low-power, low-noise systems. The system clock operating mode (single clock mode) ...
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Block Diagram of System Clock SYSCR2<WUPTM1:0> Warming up timer (High-frequency oscillator) X1 High-frequency f X2 oscillator OSCH f SYS TMRA01 to TMRA45 T0 Prescaler TMRB0 Prescaler SIO0, SIO1 Prescaler Figure 3.4.2 Block Diagram of System Clock SYSCR0 <PRCK1:0> fc/16 ...
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SYSCR0 Bit symbol (00E0H) Read/Write After reset 1 Always Always Function write 1 write 0 7 SYSCR1 Bit symbol (00E1H) Read/Write After reset Function 7 SYSCR2 Bit symbol (00E2H) Read/Write R/W After reset Always Function write 0 SFRs 6 ...
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EMCCR0 Bit symbol PROTECT (00E3H) Read/Write R R/W After reset 0 Function Protect flag Always 0: OFF write EMCCR1 Bit symbol (00E4H) Read/Write After reset Function Figure 3.4.4 SFR for Noise-Reducing R/W ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<GEAR0:2> sets the high-frequency clock gear to either ...
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Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA45, TMRB0 and SIO0, SIO1) there is a prescaler which can divide the clock. The T clock input to the prescaler is either the clock f divided by 2. The ...
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Runaway provision with protection register (Purpose) Provision against runaway of program caused by noise mixing etc. If specified SFR (clock and memory control register) is changed in runaway state, memory access is impossibility. By setting protection register, write operation ...
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Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: ...
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How to clear a HALT mode The Halt state can be cleared by a reset interrupt request. The combination of the value in <IFF0:2> of the interrupt mask register and the current HALT mode determine in ...
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Table 3.4.3 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt (Interrupt Level) HALT Mode NMI INTWDT INT0 to INT4 (Note) INT5 INTTA0 to INTTA5 INTTB00, INTTB01, INTTBOF0 INTRX0, INTTX0 INTRX1, INTTX1 INTAD RESET : After ...
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Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.4.5 illustrates an example of the timing for clearance of ...
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STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. pin status in STOP mode depends on the settings in the SYSCR2<DRVE> register. Table 3.4.5 summarizes the state of these pins in STOP mode. ...
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Table 3.4.5 Pin States in STOP Mode Pin Names I/O Input/output mode Input mode P10 to P17 (D8 to D15) Output mode Input/output mode P20 to P27 (A16 to A23), Output pin A0 to A15 Output pin ...
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Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C630 has a total of 35 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources (Software interrupts, ...
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Interrupt processing Interrupt appointed by micro DMA start vector? No Interrupt vector calue “V” read Interrupt request F/F clear General-purpose interrupt PUSH PC processing PUSH SR SR<IFF2:0> Level of accepted interrupt INTNEST INTNEST PC (FFFF00H Interrupt processing program RETI instruction ...
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General-Purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the ...
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Table 3.5.1 TMP91C630 Interrupt Vectors and Micro DMA Start Vectors Default Interrupt Source or Source of Micro DMA Type Priority 1 Reset or [SWI0] instruction 2 [SWI1] instruction 3 Illegal instruction or [SWI2] instruction 4 [SWI3] instruction 5 Non-mask [SWI4] ...
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Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C630 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the ...
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This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see (4) Transfer Mode Register. As the transfer counter is a 16-bit counter, micro DMA ...
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Soft start function In addition to starting the micro DMA function by interrupts, TMP91C815 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to ...
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Detailed description of the transfer mode register 8 bits DMAM0 Mode DMAM3 Number of Transfer Bytes 000 000 Transfer destination address INC mode (fixed) 00 Byte transfer (DMADn ) DMACn 01 Word transfer If DMACn ...
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Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. ...
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Figure 3.5.3 Block Diagram of Interrupt Controller 91C630-34 TMP91C630 2003-07-22 ...
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Interrupt priority setting registers Name Symbol Address 7 6 INTE0 IADC IADM2 & 90H INTE0AD INTAD R enable 0 0 INT1 I2C I2M2 & 91H INTE12 INT2 R enable 0 0 INT3 I4C I4M2 & 92H INTE34 INT4 R ...
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Name Symbol Address 7 Interrupt ITB01C enable INTETB0 99H R TMRB0 0 Interrupt enable 9BH INTETBOV TMRB0V (over flow) Interrupt ITX0C enable INTES0 9CH R serial 0 0 Interrupt ITX1C enable INTES1 9DH R serial 1 0 INTTC0 ITC1C & ...
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External interrupt control Name Symbol Address 7 Interrupt 0 8CH input mode IIMC0 (no RMW) Write 0 control 0 INT2 level enable 0 Edge detect INT 1 Level INT INT1 level enable 0 Edge detect INT 1 Level INT ...
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Setting functions on external interrupt pins Interrupt Pin NMI INT0 INT1 INT2 INT3 INT4 INT5 (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.5.1, ...
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Micro DMA start vector registers These registers assign micro DMA processing to an sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated ...
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Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may ...
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Port Functions The TMP91C630 features 53-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.6.1 ...
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Table 3.6.2 (a) I/O Registers and Their Specifications Port Name Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 2 P20 to P27 Output port A16 to A23 output Port Z PZ2 Input port (without ...
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Table 3.6.2 (b) I/O Registers and Their Specifications Port Name Port 8 P80 Input port (without PU) Input port (with PU) Output port TXD0 output (Note1) P81 Input port/RXD0 input (without PU) Input port/RXD0 input (with PU) Output port P82 ...
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After a Reset the port pins listed below function as general-purpose I/O port pins. A Reset sets I/O pins which can be programmed for either input or output to be input port pins. Setting the port pins for internal function ...
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Figure 3.6.1 shows an example external interface circuit when the bus release function is used. When the bus is released, neither the internal memory nor the internal I/O can be accessed. However, the internal I/O continues to operate ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting, the control register P1CR to 0 and sets Port 1 ...
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Port 2 (P20 to P27) Port 8-bit output port. In addition to functioning as a output port, Port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for ...
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Port 5 (P53 to P56) Port 4-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch the control register P5CR and the ...
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Reset Direction control (on bit basis) P5CR write Function control (on bit basis) P5FC write Output latch B Output buffer P5 write BUSAK P5 read Figure 3.6.7 Port 54 Reset Direction control (on bit basis) P5CR write ...
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Reset Direction control (on bit basis) P5CR write Function control (on bit basis) P5FC write S Output latch P5 write S B Selector P5 write A Level or edge & INT0 rising edge or falling edge IIMC0<I0LE, I0EDGE> Figure 3.6.9 ...
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Bit symbol P56 P5 (000DH) Read/Write After reset Function 7 6 Bit symbol P56C P5CR (0010H) Read/Write After reset 0 Function 7 6 Bit symbol P56F P5FC (0011H) Read/Write W After reset 0 Function 0: Port 1: INT0 ...
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Port 6 (P60 to P63) Port 4-bit output port. When reset, the P62 output latch is cleared to 0 while the P60, P61 and P63 output latches are set addition to functioning as ...
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Bit symbol P6 Read/Write (0012H) After reset 7 6 Bit symbol P6FC (0015H) Read/Write After reset Function Note: Read-modify-write is prohibited for the registers P6FC. Port 6 Register P63 Output latch register is set to ...
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Port 7 (P70 to P75) Port 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port input port. In addition to functioning as a general-purpose ...
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Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Output latch Selector P7 write B Timer F/F out TA1OUT: 8-bit TMRA1 TA5OUT: 8-bit TMRA5 Selector P7 read S Figure 3.6.15 Ports ...
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P7 Bit symbol (0013H) Read/Write After reset 7 6 P7CR Bit symbol (0016H) Read/Write After reset 7 6 Bit symbol P72F2 P7FC (0017H) Read/Write W After reset 0 Function 0: Port 1: INT2 input Note: Read-modify-write are prohibited ...
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Port 8 (P80 to P87) Port pins Port pins constitute a 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets P80 to P87 ...
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Port pins 81 (RXD0) and 85 (RXD1) Port pins 81 and 85 are I/O port pins and can also be used as RXD input pin for the serial channels. Reset Direction control (Each bit can be set individually.) P8CR ...
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Port pins and 87 ( STS 0 STS Port pins 83 and 87 are I/O port pins and can also be used as received data request signal. Reset Direction control (on bit basis) P8CR write Function ...
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Bit symbol P87 P86 P8 Read/Write (0018H) After reset Function 7 6 Bit symbol P87C P86C P8CR (001AH) Read/Write After reset 0 0 Function 7 6 Bit symbol P87F P86F P8FC (001BH) Read/Write W W After reset 0 ...
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Port 9 (P90, P93 to P96) Port 5-bit general-purpose I/O port. Each bit can be set individually for input or output, Resetting sets port input port, It also sets all bits in ...
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P93 to P96 Reset Direction control (on bit basis) P9CR write S Output latch P9 write Selector P9 read TB0IN0 TB0IN1 Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch ...
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Bit symbol P96 Read/Write P9 (0019H) After reset 7 6 Bit symbol P96C P9CR (001CH) Read/Write After reset 0 Function 7 6 Bit symbol P96F P9FC (001DH) Read/Write W After reset 0 Function 0: Port 1: TB0OUT1 Note: ...
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Port A (PA0 to PA7) Port 8-bit input port and can also be used as the analog input pins for the internal AD converter. Port A read AD read ADTRG (for PA3 only Bit ...
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Port Z (PZ2, PZ3) Port 2-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting clears all bits of the output latch the control register PZCR and the function ...
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Bit symbol PZ (007DH) Read/Write After reset Function Note: Output latch register is set Bit symbol PZCR (007EH) Read/Write After reset Function 7 6 Bit symbol PZFC (007FH) Read/Write After reset Function Port Z ...
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Chip Select/Wait Controller On the TMP91C630, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). ...
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Memory start address registers Figure 3.7.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The eight most significant bits (A23 to ...
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Memory address mask registers Figure 3.7.3 shows the memory address mask registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). ...
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Setting memory start addresses and address areas Figure 3.7.4 shows an example in which CS0 is specified 64-Kbyte address area starting at 010000H. First, MSAR0<S23:16>, the eight most significant bits of the start address register and ...
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Address area size specification Table 3.7.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A size in question using the memory start address register and memory ...
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Chip Select/Wait Control Registers Figure 3.7.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 plus any other) are set ...
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Master enable bits Bit 7 (<B0E>, <B1E>, <B2E> or <B3E> chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables ...
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Wait control Bits (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2> or <BEXW0:2> chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of ...
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Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: a. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. b. ...
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Connecting External Memory Figure 3.7.6 shows an example of how to connect external memory to the TMP91C630. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C630 ...
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Timers (TMRA) The TMP91C630 features six built-in 8-bit timers. These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module consists of two channels and can operate in any of the following four operating modes. 8-bit ...
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Block Diagrams Figure 3.8.1 TMRA01 Block Diagram 91C630-78 TMP91C630 2003-07-22 ...
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Figure 3.8.2 TMRA23 Block Diagram 91C630-79 TMP91C630 2003-07-22 ...
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Figure 3.8.3 TMRA45 Block Diagram 91C630-80 TMP91C630 2003-07-22 ...
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Operation of Each Circuit (1) Prescalers The 9-bit prescaler in TMRA01 generates the clock source of TMRA01. The clock T0 is divided by 4 and input to this prescaler. T0 can be either f fc/16 and is selected using ...
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Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up-counter, the comparator match ...
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Comparator (CP0 and CP1) The comparator compares the value in an up-counter with the value set in a timer register. If they match, the up-counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFRs 7 Bit symbol TA0RDE TA01RUN (0100H) Read/Write R/W After reset 0 Function Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN are undefined ...
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Bit symbol TA4RDE TA45RUN (0110H) Read/Write R/W After reset 0 Function Double buffer 0: Disable 1: Enable TA4REG double buffer control 0 Disable 1 Enable Note: The values of bits TA45RUN are undefined when read. ...
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Bit symbol TA01M1 TA01M0 TA01MOD (0104H) Read/Write After reset 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA01 Mode Register PWM01 PWM00 TA1CLK1 ...
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TA23MOD Bit symbol TA23M1 TA23M0 (010CH) Read/Write After reset 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA23 Mode Register PWM21 PWM20 TA3CLK1 ...
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TA45MOD Bit symbol TA45M1 TA45M0 (0114H) Read/Write After reset 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA45 Mode Register PWM41 PWM40 TA5CLK1 ...
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Bit symbol TA1FFCR (0105H) Read/Write After reset Read-modify Function -write instruction is prohibited. TMRA1 Flip-flop Control Register TAFF1C1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care Inverse signal for timer ...
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Bit symbol TA3FFCR Read/Write (010DH) After reset Read-modify Function -write instruction is prohibited. TMRA3 Flip-flop Control Register TAFF3C1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care Inverse signal for timer ...
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Bit symbol TA5FFCR (0115H) Read/Write After reset Read-modify Function -write instruction is prohibited. TMRA5 Flip-flop Control Register TAFF5C1 1 00: Invert TA5FF 01: Set TA5FF 10: Clear TA5FF 11: Don’t care Inverse signal for timer ...
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Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first ...
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Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.32 s square wave pulse ...
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Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up-counter 1 2 (when ...
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The comparator match signal is output from TMRA0 each time the up-counter UC0 matches TA0REG, where the up-counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse ...
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In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up-counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller ...
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Example: To generate 1/4-duty 113.636kHz pulses ( Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: f FPH Calculate the value which should be set in the timer register. To obtain a ...
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PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT ...
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In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match ...
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Select Prescaler Gear Value Clock <GEAR2:0> <PRCK1:0> 000 (fc) 001 (fc/2) 00 010 (fc/ FPH 011 (fc/8) 100 (fc/16) 10 XXX (fc/16 clcok) XXX: Don’t care (5) Settings for each mode Table 3.8.4 shows the SFR settings for ...
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Timer/Event Counters (TMRB) The TMP91C630 incorporates multifunctional 16-bit timer/event counter (TMRB0) which has the following operation modes: 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) mode The timer/event counter channel consists of a ...
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Block Diagrams Figure 3.9.1 Block Diagram of TMRB0 91C630-102 TMP91C630 2003-07-22 ...
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Operation of Each Block (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock ( T0) is divided clock (divided by 4) from selected clock by the register SYSCR0<PRCK1:0> of clock-gear. This prescaler can be ...
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Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up-counter UC0 matches the value set in this timer register, the comparator match detect signal will go active. ...
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Capture input control This circuit controls the timing to latch the value of up-counter UC0 into TB0CP0 and TB0CP1. The latch timing for the capture register is determined by TB0MOD <TB0CPM1:0>. In addition, the value in the up-counter can ...
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SFRs 7 6 TB0RUN Bit symbol TB0RDE (0180H) Read/Write R/W R/W After reset 0 0 Function Double Write 0 buffer 0: Disable 1: Enable Note: The 1, 4 and 5 of TB0RUN are read as undefined value. Figure 3.9.2 ...
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TB0MOD Bit symbol TB0CT1 TB0ET1 (0182H) Read/Write R/W After reset 0 0 Function TB0FF1 inversion 0: Disable trigger 1: Enable trigger Invert when Invert when the UC the UC value is value captured to matches the TB0CP1. value ...
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TB0FFCR Bit symbol TB0FF1C1 TB0FF1C0 (0183H) Read/Write W* After reset 1 Function Control TB0FF1 00: Invert 01: Set 10: Clear 11: Don’t care * Always read as 11 TMRB0 Flip-flop Control Register TB0C1T1 TB0C0T1 TB0E1T1 ...
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Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1. 7 ...
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Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either Low-active or High-active. The PPG mode is obtained by inversion of the timer flip-flop ...
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The following block diagram illustrates this mode. Selector TB0IN0 T1 T4 T16 16-bit comparator Selector TB0RG0 TB0RG0-WR Register buffer 0 TB0RUN<TB0RDE> Figure 3.9.7 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: 7 ...
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Serial Channels TMP91C630 includes two serial I/O channels. Either UART mode (asynchronous transmission) or I/O interface mode (synchronous transmission) can be selected. I/O interface mode UART mode In Mode 1 and Mode 2 a parity bit can be added. ...
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STS0 and STS1 pins are built in port P83 and P87. STS0 and STS1 are the request signal for the next data send to the CPU. P8CR sets port as output mode, P8FC sets STS using mode, and bit 0 ...
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Block Diagrams Figure 3.10 block diagram representing serial channel 0. Prescaler T32 Serial clock generation circuit BR0CR <BR0CK1:0> BR0CR BR0ADD <BR0S3:0> <BR0K3:0> T32 BR0CR <BR0ADDE> ...
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Prescaler T32 Serial clock generation circuit BR1CR <BR1CK1:0> BR1CR BR1ADD <BR1S3:0> <BR1K3:0> T32 BR1CR <BR1ADDE> Baud rate generator f SYS SCLK1 Shared with P86 I/O interface mode SCLK1 ...
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Operation of Each Circuit (1) Prescaler, prescaler clock select There is a 6-bit prescaler for waking serial clock. The clock selected using SYSCR0<PRCK1:0> is divided by 4 and input to the prescaler as T0. The prescaler can be run ...
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Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, T0, T2 T32, is ...
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N (16 K)/16 divider (UART mode only) Accordingly, when the source clock frequency (fc) frequency T0, the frequency (BR0ADD<BR0K3:0>) 3, and BR0CR <BR0ADDE> follows: * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: ...
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Table 3.10.3 Transfer Rate Selection (When Baud Rate Generator is Used and BR0CR<BR0ADDE> fc [MHz] Frequency Divider 9.830400 12.288000 14.745600 Note 1: Transfer rates in I/O interface mode are eight times faster than the values given above. Note 2: The ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> 0, the basic clock is generated by dividing the output of the ...
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The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When bits ...
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Handshake function Serial channels 0 and 1 each have a in units of one frame; thus, overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD0<CTSE> setting. When the CTS transmission is halted until the ...
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Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU, in order one bit at a time starting with the least significant bit (LSB) and finishing with the most significant bit (MSB). ...
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Timing generation a. In UART mode Receiving Mode 9-bit (Note) Interrupt timing Center of last bit (bit 8) Framing error timing Center of stop bit Parity error timing Overrun error timing Center of last bit (bit 8) Note: In ...
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SFRs 7 SC0MOD0 Bit symbol TB8 CTSE (0202H) Read/Write After reset 0 Transfer Function Hand shake data bit 8 0: CTS disable 1: CTS enable Figure 3.10.7 Serial Mode Control Register (Channel 0, SC0MOD0 RXE ...
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SC1MOD0 Bit symbol TB8 CTSE (020AH) Read/Write After reset 0 Function Transfer Hand shake data bit 8 0: CTS disable 1: CTS enable Figure 3.10.8 Serial Mode Control Register (Channel 1, SC1MOD0 RXE WU SM1 ...
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SC0CR Bit symbol RB8 EVEN (0201H) Read/Write R After reset 0 Function Received Parity data bit 8 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with a ...
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SC1CR Bit symbol RB8 EVEN (0209H) Read/Write R After reset 0 Function Received Parity data bit 8 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with a ...
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BR0CR Bit symbol BR0ADDE (0203H) Read/Write After reset 0 Function Write “0” (16 K)/16 division 0: Disable 1: Enable (16 K)/16 division enable 0 Disable 1 Enable 7 BR0ADD Bit symbol (0204H) Read/Write After reset Function Sets Baud Rate ...
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BR1CR Bit symbol BR1ADDE (020BH) Read/Write After reset 0 (16 K)/16 Function Write “0” division 0: Disable 1: Enable (16 K)/16 division enable 0 Disable 1 Enable 7 BR1ADD Bit symbol (020CH) Read/Write After reset Function Sets Baud Rate ...
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TB7 TB6 TB5 SC0BUF (0200H RB7 RB6 RB5 Note: Read-modify-write instruction is prohibited for SC0BUF. Figure 3.10.13 Serial Transmission/Receiving Buffer Registers (Channel 0 and SC0BUF) 7 SC0MOD1 Bit symbol I2S0 FDPX0 (0205H) Read/Write R/W R/W After ...
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Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all the data has been output, INTES0<ITX0C> ...
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Receiving In SCLK output mode the synchronous clock is output on the SCLK0 pin and the data is shifted to receiving buffer 1. This is initiated when the receive interrupt flag INTES0<IRX0C> is cleared as the received data is ...
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Transmission and receiving (full duplex mode) When full duplex mode is used, set the receive interrupt level to 0 and set enable the level of transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer ...
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Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting the serial channel mode register SC0MOD0<SM1:0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled ...
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Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Main settings P8CR 0 SC0MOD0 SC0CR X 0 ...
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Protocol a. Select 9-bit UART mode on the master and slave controllers. b. Set the SC0MOD0<WU> bit on each slave controller enable data receiving. c. The master controller transmits data one frame at a time. Each frame ...
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Setting example: To link two slave controllers serially with the master controller using the internal clock f TXD RXD TXD Master Slave 1 Select code 00000001 Since serial channels 0 and 1 operate in exactly the same way, channel 0 ...
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Analog/Digital Converter The TMP91C630 incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11 block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are shared with the ...
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Analog/Digital Converter Registers The AD converter is controlled by the two AD mode control registers: ADMOD0 and ADMOD1. The eight AD conversion data upper and lower registers (ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L) store the results of AD conversion. Figure ...
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ADMOD1 Bit symbol VREFON I2AD (02B1H) Read/Write R/W R/W After reset 0 0 Function VREF IDLE2 application 0: Stop control 1: Operate 0: Off 1: On Figure 3.11.3 AD Converter Related Register AD Mode Control Register 1 5 ...
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AD Conversion Data Low Register 0/4 7 ADREG04L Bit symbol ADR01 ADR00 (02A0H) Read/Write R After reset Undefined Function Stores lower 2 bits of AD conversion result AD Conversion Data Upper Register 0/4 7 ADREG04H Bit symbol ADR09 ADR08 (02A1H) ...
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AD Conversion Result Lower Register 2/6 7 ADREG26L Bit symbol ADR21 ADR20 (02A4H) Read/Write R After reset Undefined Function Stores lower 2 bits of AD conversion result. AD Conversion Data Upper Register 2/6 7 ADREG26H Bit symbol ADR29 ADR28 (02A5H) ...
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Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between ...
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AD conversion modes and the AD conversion end interrupt The four AD conversion modes are: Channel fixed single conversion mode Channel scan single conversion mode Chanel fixed repeat conversion mode Channel scan repeat conversion mode The ADMOD0<REPET> and ADMOD0<SCAN> ...
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Channel scan repeat conversion mode Setting ADMOD0<REPET> and ADMOD0<SCAN> selects conversion channel scan repeat conversion mode. In this mode data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0<EOCF> is ...
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Table 3.11.3 Correspondence Between Analog Input Channels and AD Conversion Result Registers Analog Input Channel (Port A) AN0 AN4 AN1 AN5 AN2 AN6 AN3 AN7 <ADRxRF>, bit 0 of the AD conversion data lower register, is used as the AD ...
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Watchdog Timer (Runaway Detection Timer) The TMP91C630 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (runaway) due ...
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The watchdog timer consists of a 22-stage binary counter which uses the system clock ( the input clock. The binary counter can output f SYS Selecting one of the outputs using WDMOD<WDTP1:0> generates a Watchdog ...
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Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting ...
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WDMOD Bit symbol WDTE WDTP1 (0300H) Read/Write R/W After reset 1 0 Function WDT control Select detecting time 15 1: Enable 11: 2 Watchdog timer detection time SYSCR1 Gear ...
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Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be zero-cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if ...
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Multi-Vector Control (1) Outline By rewriting the value of multi-vector control register (MVEC0 and MVEC1), a vector table is arbitrarily movable. (2) Control register The amount of 228 bytes become an interruption vector area from the value set as ...
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Multi-Boot Mode (1) Outline The TMP91C630 has multi-boot mode available as an on-board programming operation mode. When in multi-boot mode, the boot ROM is mapped into memory space. This boot ROM is a mask ROM that contains a program ...
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Memory map Figure 3.14.2 shows memory maps for multi-chip and multi-boot modes. When start up in multi-boot mode, internal boot ROM is mapped in FFF800H address, the boot program starts up. When start up in multi-chip mode, internal boot ...
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SIO interface specifications The following shows the SIO communication format in multi-boot mode. Before on-board programming can be executed, the communication format on the programming controller side must also be set up in the same way as for the ...
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Table 3.14.3 Baud Fate Modification Command Baud rate (bps) 9600 Modification command 28H Table 3.14.4 Operation Command Operation command C0H Table 3.14.5 Version Management Information Version information FRM1 Table 3.14.6 Frequency Measurement Result Data Frequency of resonator 16.000 20.000 (MHz) ...
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The 7th byte is used to send information of the measured frequency. The controller should check that the frequency of the resonator is measured correctly. 7. The receive data in the 8th byte is the baud rate modification data. ...
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Error code The boot program sends the processing status to the controller using various code. The error code is listed in the table below. Table 3.14.7 Error Code Error code 62H Baud rate modification error occurred. 64H Operation command ...
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Transmit a user program not by the ASCII code but by binary. However, start mark “:” is 3AH (ASCII code). Example: Transmit data in the case of writing in 16 bytes data from address 1060H Data Record 3A 10 ...
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Ports setup of the boot program Only ports shown in Table 3.14.9 are set up in the boot program. At the time of boot program use, be careful of the influence on a user system. Do not use the ...
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Electrical Characteristics 4.1 Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output current (per pin) Output current (per pin) Output current (total) Output current (total) Power dissipation (Ta 85°C) Soldering temperature (10 s) Storage temperature Operating temperature Note: ...
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DC Characteristics (2/2) Parameter Symbol Input leakage current ILI Output leakage current ILO Power down voltage VSTOP (at STOP, RAM back-up) pull-up resistor RRST RESET pull-up resistor RBT BOOT Pin capacitance CIO Schmitt width VTH , , , INT0 to ...
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AC Characteristics (1) Vcc 2.7 to 3.6 V No. Parameter 1 f period ( x ) FPH A23 vaild / fall rise A0 to A23 hold RD 4 rise A0 to A23 hold ...
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Read cycle t FPH f FPH A0 to A23 CSn WAIT Port input (Note D15 Note: Since the CPU accesses the internal area to read data from a port, the control signals of external ...
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Write cycle f FPH A0 to A23 CSn WAIT Port output (Note HWR D0 to D15 Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such ...
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AD Conversion Characteristics Parameter Analog reference voltage ( ) Analog reference voltage ( ) Analog input voltage range Analog current for analog Reference voltage <VREFON> 1 <VREFON> 0 Error (not including quantizing errors) Note 1: 1 LSB (VREFH VREFL)/1024 ...
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Serial Channel Timing (I/O Internal Mode) Note: Symbol x in the below table means the period of clock f f for CPU core. The period of f SYS (1) SCLK input mode Parameter SCLK period Output data SCLK rising/falling ...
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Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1) Parameter Clock perild Clock low level width Clock high level width Note: Symbol x in the above table means the period of clock f f for CPU core. The period of f SYS ...
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Bus Request/Bus Acknowledge BUSRQ BUSAK D0 to D15 A0 to A23 CS0 CS3 HWR Parameter Output buffer to low BUSAK high to output buffer on BUSAK Note 1: Even if the signal goes Low, ...
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Table of SFRs The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 000FFFH. (1) I/O port (2) I/O port control (3) Interrupt control (4) Chip select/wait ...
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Port Address Name 0000H P1CR P2FC Address Name 0070H ...
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CS/WAIT Address Name 00C0H B0CS 1H B1CS 2H B2CS 3H B3CS BEXCS 8H MSAR0 9H MAMR0 AH MSAR1 BH MAMR1 CH MSAR2 DH MAMR2 EH MSAR3 FH MAMR3 [5] TMRA Address Name 0100H TA01RUN 1H ...
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TMRB0 Address Name 0180H TB0RUN 1H 2H TB0MOD 3H TB0FFCR TB0RG0L 9H TB0RG0H AH TB0RG1L BH TB0RG1H CH TB0CP0L DH TB0CP0H EH TB0CP1L FH TB0CP1H [8] 10-bit ADC Name Address 02A0H ADREG04L 1H ADREG04H ...
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I/O port Symbol Name Address 7 P17 P1 Port 1 01H P27 P2 Port 2 06H P5 Port 5 0DH P6 Port 6 12H P7 Port 7 13H P87 P8 Port 8 18H P9 Port 9 19H PA7 PA ...
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I/O port control (1/2) Symbol Name Address 7 P17C P1CR Port 1 04H control (Prohibit 0 RMW) P27F P2FC Port 2 09H function (Prohibit 1 RMW) P5CR Port 5 10H control (Prohibit RMW) P5FC Port 5 11H function (Prohibit ...
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I/O port control (2/2) Symbol Name Address 7 P9CR Port 9 1CH control (Prohibit RMW) P9FC Port 9 1DH function (Prohibit RMW) PZCR Port Z 7EH control (Prohibit RMW) PZFC Port Z 7FH function (Prohibit RMW) ODE Sirial open 2FH ...
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Interrupt control (1/3) Symbol Name Address 7 Interrupt IADC 90H INTE0AD enable R INT0 & INTAD Interrupt 91H I2C INTE12 enable R INT2 INT2 Interrupt 92H I4C INTE34 enable R INT4 INT4 ...
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Interrupt control (2/3) Symbol Name Address 7 ITX0C Interrupt 9CH INTES0 enable R serial INTTX0 ITX1C Interrupt 9DH INTES1 enable R serial INTTX1 Interrupt A0H ITC1C INTETC01 enable R INTTC0/1 0 Interrupt ITC3C INTETC23 ...
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Interrupt control (3/3) Symbol Name Address 7 80H DMA0 DMA0V (Prohibit start vector RMW) 81H DMA1 DMA1V start (Prohibit RMW) vector 82H DMA2 DMA2V (Prohibit start vector RMW) DMA3 83H DMA3V (Prohibit start RMW) vector Interrupt 88H INTCLR (Prohibit clear ...
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Chip select/Wait control (1/2) Symbol Name Address 7 B0E B0CS Block 0 C0H W CS/WAIT 0 control 0: Disable register (Prohibit 1: Enable RMW) B1E B1CS Block 1 C1H W CS/WAIT 0 control 0: Disable register (Prohibit 1: Enable ...
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Chip select /Wait control (2/2) Symbol Name Address 7 S23 Memory start MSAR2 CCH address 1 register 2 V22 Memory address MAMR2 CDH mask 1 register 2 S23 Memory start MSAR3 CEH address 1 register 3 V22 Memory address MAMR3 ...
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Clock gear Symbol Name Address 7 SYSCR0 System E0H clock 1 control Always register 0 write 1 SYSCR1 System E1H clock control register 1 SYSCR2 System E2H clock control register 2 PROTECT EMCCR0 EMC E3H R control 0 register ...
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TMRA01 Symbol Name Address 7 TA0RDE R/W TMRA01 TA01RUN 100H RUN 0 Double buffer 0: Disable 1: Enable TMRA0 102H register 0 TA0REG (Prohibit RMW) TMRA1 103H register 1 TA1REG (Prohibit RMW) TA01M1 TA01MOD ...
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TMRA23 Symbol Name Address 7 TA2RDE TA23RUN TMRA23 108H R/W RUN 0 Double buffer 0: Disable 1: Enable TMRA2 10AH TA2REG register 0 (Prohibit RMW) TMRA3 10BH TA3REG register 1 (Prohibit RMW) TA23M1 TA23MOD TMRA23 ...
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TMRA45 Symbol Name Address 7 TA4RDE R/W TA45RUN TMRA45 0 RUN 110H Double buffer 0: Disable 1: Enable TMRA4 112H register 0 (Prohibit TA4REG RMW) TMRA5 113H register 1 (Prohibit TA5REG RMW) TA45M1 TA45MOD TMRA45 114H ...
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TMRB0 Symbol Name Address 7 TB0RDE TB0RUN TMRB0 180H R/W control 0 Double buffer 0: Disable 1: Enable TB0CT1 TB0MOD TMRB0 182H R/W source 0 CLK & TB0FF1 inversion MODE trigger 0: TRG disable 1: TRG ...
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UART/Serial channel control (8-1) UART/SIO channel 0 Symbol Name Address 7 Serial RB7/TB7 SC0BUF channel 0 200H buffer RB8 R Serial 0 SC0CR channel 0 201H Receiving control data bit 8 TB8 0 Serial Transfer SC0MOD0 channel 0 202H ...
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UART/SIO Channel 1 Symbol Name Address 7 RB7/TB7 Serial SC1BUF 208H channel 1 buffer RB8 R Serial 0 SC1CR 209H channel 1 Receiving control data bit 8 TB8 Serial 0 SC1MOD0 20AH channel 1 Transmissi on data bit 8 ...
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AD converter Symbol Name Address 7 AD EOCF ADMOD0 MODE 2B0H register End AD VREFON ADMOD1 MODE 2B1H R/W register VREF On IDLE2 AD result ADR01 ADREG04L register 2A0H 0/4 Low Undefined AD ...
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Watchdog timer control Symbol Name Address 7 WDTE WDT R/W MODE WDMOD 300H 1 register 1: WDT enable WDCR WDT 301H control (10) Multi vector control Symbol Name Address 7 VEC7 Multi R/W MVEC0 vector 00AEH 1 control Symbol Name ...
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Port Section Equivalent Circuit Diagrams Reading the circuit diagrams The gate symbols used are essentially the same as those used for the standard CMOS logic IC [74HCXX] Series. The dedicated signal is described below. STOP: This signal becomes Active ...
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PA0 to PA7 (AN0 to AN7) Analog input Channel select Analog input Input data P56 (INT0) Output data Output enable Stop Input data P70 (INT1), P72 (INT2), P73 (INT3), P75 (INT4) and P90 (INT5) Output data Output enable Stop Input ...
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AM0 to AM1 Input data BOOT BOOT Schmitt RESET Reset WDTOUT Reset enable X1 and X2 Oscillator P-ch High-frequency oscillation enable VREFH and VREFL VREFON Input V CC P-ch Input V CC P-ch Input Schmitt N-ch Clock P-ch VREFH String ...
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Points to Note and Restrictions (1) Notation a. The notation for built-in/I/O registers is as follows register symbol <bit symbol> e.g.) TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN. b. Read-modify-write instructions An instruction in which the CPU reads data ...
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Points to note a. AM0 and AM1 pins Those pins are connected to the VCC or VSS pin Do not alter the voltage level of those pins when theTMP91C630 is processing b. EMU0and EMU1 Open pins. c. Reserved address ...
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Diversity of TMP91C630 and TMP91C829 TMP91C630 is based on TMP91C829, the significant different points of TMP91C630 and TMP91C829 are shown below. Because power supply is different, the electrical characteristic specification is changed, please refer to Chapter 4. Electrical characteristics. ...