AD9054 Analog Devices, AD9054 Datasheet
AD9054
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AD9054 Summary of contents
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... MSPS conversion rate. In the single- channel (nondemultiplexed) mode, all data is piped at the full clock rate to the Channel A outputs. Fabricated with an advanced BiCMOS process, the AD9054 is provided in a space-saving 44-lead TQFP surface mount plastic package (ST-44) and specified over the full industrial (– +85 C) temperature range ...
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... Full VI 500 Full VI 500 + Full IV 400 Full IV 1.5 Full IV 0 Full IV 1.5 Full IV 2.0 Full IV 0 Full VI 2.4 Full VI Binary –2– = max unless otherwise noted) S AD9054BST-135 Max Min Typ Max 8 +1.5/–1.0 0.9 +1.5/–1.0 +2.0/–1.0 1.0 +2.0/–1.0 1.5 0.6 1.5 2.0 0.9 2.0 Guaranteed 160 512 3.2 1.8 3 ...
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... C/ C/W. JA AD9054 Units Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9054 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... SAMPLE N SAMPLE N+1 SAMPLE N 1 SDS INVALID IF OUT OF SYNC DATA N– SYNC INVALID IF OUT OF SYNC DATA N– SYNC Figure 2. Timing—Dual Channel Mode –5– AD9054 SAMPLE N+3 SAMPLE N DATA N–2 DATA N–1 DATA N SAMPLE N+3 SAMPLE N+4 SAMPLE N DATA N–2 DATA N– ...
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... AD9054 EQUIVALENT CIRCUITS AIN Figure 3. Equivalent Analog Input Circuit V DD VREF IN Figure 4. Equivalent Reference Input Circuit 300 ENCODE OR DS Figure 5. Equivalent ENCODE and Data Select Input Circuit V DD AIN V DD 17.5k 300 ENCODE OR DS 7.5k Figure 8. Equivalent Reference Output Circuit –6– 17.5k 300 ...
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... MHz Figure 13. SNR vs. Temperature 225 250 270 300 Figure 14. SNR vs. Clock Pulsewidth 70.1 MHz –7– AD9054 50MHz 20MHz 70MHz 0 – – 135 MSPS S 20MHz 50MHz 70MHz –60 –40 – – ...
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... AD9054 200MSPS 10.3MHz IN SNR 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ENCODE PULSEWIDTH – ns Figure 15. SNR vs. Clock Pulsewidth 70MHz –60 –40 – – Figure 16. SINAD vs. Temperature 50MHz 42 70MHz –60 –40 –20 ...
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... S 0 –10 –20 –30 –40 –50 –60 –70 –80 – 100 Figure 26. Spectrum 200 MSPS S –9– AD9054 NYQUIST FREQUENCY 100MHz 50 100 150 200 250 300 350 400 450 f – MHz IN = 200 MSPS S FUNDAMENTAL = –0.5dBfs SNR = 45.8dB SINAD = 45.2dB 2ND HARMONIC = 69 ...
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... AD9054 55.0MHz – 56.0MHz –7.0dBfs –20 –30 –40 –50 –60 –70 –80 –90 –100 MHz Figure 27. Two Tone Intermodulation Distortion 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0 –9.0 I – Figure 28. Output Voltage HIGH vs. Output Current 1 ...
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... Lower effective sampling rates may be easily supported by oper- ating the converter in dual port output mode and using only one output channel. A majority of the power dissipated by the AD9054 is static (not related to conversion rate) so the penalty for clock- ing at twice the desired rate is not high. ...
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... Figure 34. Input Signal Level Definitions Single Port Mode When operated in a Single Port mode (DEMUX = HIGH), the timing of the AD9054 is similar to any high speed A/D Con- verter (Figure 1). A sample is taken on every rising edge of ENCODE, and the resulting data is produced on the output pins following the FOURTH rising edge of ENCODE after the sample was taken (four pipeline delays) ...
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... For example, synchronization may be provided at the beginning of each graphics line or frame. The data are presented at the output of the AD9054 in a ping- pong (alternating) fashion to optimize the performance of the converter. It may be aligned for presentation as sixteen bits in parallel by adding a register stage to the output ...
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... Channel Mode it is needed for two reasons: to synchronize the timing of Port A data and Port B data with a known clock edge, as described in the data sheet, and to synchronize the evaluation board’s latch clocks with the data coming out of the AD9054. DAC Reset can be driven in two ways: by pushing the reset button on the board, or externally, with a TTL pulse through connector ...
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... GND REV. 0 (LSB) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DA3 DA4 DA5 DA6 DA7 GND GND VDD +5VA GND GND VDD +5VA Figure 38. Evaluation Board Schematic –15– AD9054 SLEEP REFLO REFIO FSADJ COMP1 COMP2 AVDD DVDD ...
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... AD9054 Figure 39. Assembly—Top View Figure 40. Assembly—Bottom View Figure 41. Conductors—Top View Figure 42. Conductors—Bottom View –16– REV. 0 ...
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... U4, U5 SO-20 OCTAL D TYPE FLIP-FLOP U1 SOIC-8 OP AMP U8 10-BIT CMOS DAC SOIC-28 UA1 TQFP-44 DUAL 8-BIT ADC B1 SURFACE MOUNT MOMENTARY PUSHBUTTON – BUMPON PROTECTIVE BUMPER –17– AD9054 MFG/DISTRIBUTOR TTI DIGI-KEY DIGI-KEY TTI DIGI-KEY DIGI-KEY DIGI-KEY DIGI-KEY CENTURY ELEC DIGI-KEY TTI NEWARK NEWARK ...
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... AD9054 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Thin Quad Flatpack (TQFP) (ST-44) 0.063 (1.60) MAX 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN 0.006 (0.15) 0.002 (0.05) 0.018 (0.45) 0.031 (0.80) 0.057 (1.45) BSC 0.012 (0.30) 0.053 (1.35) –18– 0.394 (10. REV. 0 ...
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