MDS213CG Zarlink Semiconductor, MDS213CG Datasheet
MDS213CG
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... Figure 10/100Mbps + 2Gbps Port System Configuration Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. 12-Port 10/100Mbps + 1Gbps MDS213CG - Protocol filtering - Local port filtering - Aging control for secure MAC addresses - Provides 256-port and ID Tagged Virtual LANs (VLANs) 802 ...
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... The MDS213 is fabricated with 2.5 V technology, where the inputs are 3.3V tolerant and the outputs are capable of directly interfacing to Low-Voltage TTL levels. The Zarlink MDS213 is packaged in a 456-pin Ball Grid Array. MDS213 2 Zarlink Semiconductor Inc. Data Sheet ...
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... The LED interface has 3 output signals (1 data and 2 control). The XPipe is 32-bits wide. MDS213 32 CPU Interface TM HISC Registers Search Engine Frame Engine GMAC Twelve GMII/PCS(TBI) 10/100 MACs Interface RMII GMII or PCS Figure 2 - System Block Diagram 3 Zarlink Semiconductor Inc. Data Sheet 32 Reduced Xpipe 3.2Gbps Engine TM XPipe 32 LED Xface ...
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... Switching Database Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.4 Send and Receive Frames for Management CPU 7.3.5 Communication Between HISC and Switching Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.6 Communication Between Search Engine and HISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.7 Communication Between HISC and Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 Communication Between Management CPU and HISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MDS213 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... CPU Transmitting Unicast CPU Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.2 CPU Transmitting Multicast CPU Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.3 CPU Receiving Unicast Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3.4 CPU Receiving Multicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.0 Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.2 Physical Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2.1 Setting Register For Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2.1.1 APMR- Port Mirroring Register 14.0 Virtual Local Area Networks (VLAN MDS213 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... AMA - RAM Counter Block Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.3.8 Reserve Register 18.2.3.9 Reserve Register 18.2.4 Frame Control Buffers Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.1 FCBSL - FCB Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.2 FCBST - FCB QUEUE - Buffer Low Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.3 BCT - (FCB) Buffer Counter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.4.4 BCHL - Buffer Counter Hi-low Selection MDS213 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... THKM [0:7] - Trunking Forwarding Port Mask 0 18.2.11.4 IPMCAS - IP Multicast MAC Address Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.11.5 IPMCMSK- IP Multicast MAC Address Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 18.2.11.6 CFCBHDL - FCB Handle Register For CPU Read 18.2.11.7 CPU Access Internal RAMs (Tables 18.2.11.8 CPUIRCMD - CPU Internal RAM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 MDS213 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... ECR4 - Port Status Counter Wrapped Signal 105 18.2.12.6 PVID Register 107 19.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 19.1 Absolute Maximum Ratings 108 19.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 20.0 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 20.1 XPIPE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 20.2 CPU BUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 20.3 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MDS213 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 31 - Reduce Media Independent Interface - Input Setup and Hold Timing 114 Figure 32 - Reduce Media Independent Interface - Output Delay Timing 114 Figure 33 - Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 34 - Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 35 - LED Interface - Output Delay Timing 117 MDS213 List of Figures 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Table Characteristics - Port Mirroring Interface 115 Table Characteristics - Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table Characteristics - Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table Characteristics - Physical Media Attachment Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table Characteristics - LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 MDS213 List of Tables 10 Zarlink Semiconductor Inc. Data Sheet ...
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... M6_T M6_R M7_T M7_R M8_T M8_R M9_C RXD XD0 XD0 XD0 XD0 XD1 XD0 RS_ Zarlink Semiconductor Inc. Data Sheet X_DI X_DI X_DI X_DI X_DI X_DI X_DI P_CS X_DI ...
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... N2 L_BW4# P2 L_BW5# P1 L_BW6# P4 L_BW7# P3 L_D32 R5 L_D33 R1 L_D34 R2 L_D35 R4 L_D36 R3 L_D37 T1 L_D38 T2 L_D39 T3 L_D40 U1 L_D41 T4 L_D42 U2 L_D43 U3 12 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. L_D44 V1 L_D45 V2 L_D46 U4 L_D47 U5 L_D48 V3 L_D49 W1 L_D50 W2 L_D51 V4 L_D52 W3 L_D53 Y1 L_D54 Y2 L_D55 Y3 L_D56 W4 L_D57 W5 L_D58 AA1 ...
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... AD16 M10_LNK AF17 M10_TXEN AC16 M10_TXD1 AE17 M10_TXD0 AD17 M10_CRS_DV AF18 M10_RXD1 AB17 M10_RXD0 AC17 M11_LNK AE18 M11_TXEN AD18 13 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. M11_TXD1 AF19 M11_TXD0 AB19 M11_CRS_DV AE19 M11_RXD1 AC18 M11_RXD0 AD19 M12_CRS AF20 M12_TXCLK/GP_TXCL AE20 K ...
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... P_D19 K24 P_D20 J26 P_D21 J25 P_D22 K23 P_D23 J24 P_D24 H26 P_D25 K22 P_D26 H25 P_D27 J23 14 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. P_D28 H24 P_D29 G26 P_D30 G25 P_D31 G24 P_A1 H23 P_A2 F26 P_A3 F25 P_A4 ...
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... X_DO18 B10 X_DO19 C10 X_DO20 A9 X_DO21 B9 X_DO22 E10 X_DO23 D10 X_DO24 C9 X_DO25 A8 X_DO26 B8 X_DO27 D9 X_DO28 C8 X_DO29 A7 X_DO30 B7 X_DO31 C7 L_A3 D8 15 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name No. L_A4 A6 L_A5 B6 L_A6 C6 L_A7 D7 L_A8 A5 L_A9 E8 L_A10 B5 L_A11 A4 L_A12 D6 L_A13 C5 L_A14 B4 L_A15 E6 L_A16 D5 ...
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... GND P14 GND P15 GND P16 GND R11 GND R12 GND R13 GND R14 GND R15 GND R16 GND T11 GND T12 GND T13 GND T14 GND T15 GND T16 GND AB5 GND AB14 GND AB22 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Bus Grant to CPU - Only using in debug mode when system in unmanaged. Input/Output Bus Request from secondary MDS212 to primary MDS212. Only using in debug mode when system is unmanaged. Input/Output Bus Grant to secondary MDS212 from primary MDS212. Only using in debug mode when system is unmanaged. 17 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Output Frame Buffer Write Chip Select [1:0] Output Frame Buffer Read Chip Select [1:0] Output MII Management Data Clock - (Common for all RMII Ports [11:0]) I/O-TS MII Management Data I/O - (Common for all RMII Ports [11:0]) Input Reference Input Clock 18 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Data Valid Output Ports [11:0] - Transmit Enable Output Ports [11:0] - Transmit Data Bit [1] Output Ports [11:0] - Transmit Data Bit [0] Input- ST, U Ports [11:0] Link Status I/O Input-U Port [12] -- Receive Data Bit [7:0] Input-U Port [12] -- Receive Data Valid Input- U Port [12] -- Receive Error 19 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... Port [12] - TBI Transmit Data Bit [9:0] Output Port [12] - TBI Gigabit Transmit Clock Input- ST, U Port [12] - TBI Link Status Input - U Port [12] - TBI Gigabit Reference Clock I/O Input XPipe Data Clock Input Input XPipe Data Enable Input Input XPipe Flow Control Input 20 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... Port Mirroring Data Enable Input Input- TS, U Port Mirroring Input Data Bit [1:0] Output Port Mirroring Data Enable Output Output Port Mirroring Output Data Bit [1:0] I/O-TS, U Test Pin - Set Mode upon Reset, and provides test status output. 21 Zarlink Semiconductor Inc. Data Sheet Description ...
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... LED Serial Data Input Stream Input- U LED Input Data Stream Output LED Serial Interface Output Clock Output LED Serial Data Output Stream Output LED Output Data Stream I/O Input System Clock at 100 MHz Power +2.5 Volt DC Supply Power +3.3 Volt DC Supply 22 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... CPU Read/Write Control Polarity Selection Default=1 0=R/W#; Input Switch mode: Default=1 0=Managed mode Input Primary Device Enable Pin Default=1 0=Secondary Input Option of merge the P_RDY# and P_BRDY# as one pin Default=1 0=Merged pin 23 Zarlink Semiconductor Inc. Data Sheet Description 1=W/R# 1= Unmanaged 1=Primary 1=Separated pins ...
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... The MAC/GMAC monitors the Carrier Sense (CRS) signal to determine if the medium is available before attempting to transmit data. If the transmission medium is busy, the MAC/GMAC defers (delays) its own transmissions to decrease the load on the network. This is called collision avoidance. MDS213 24 Zarlink Semiconductor Inc. Data Sheet ...
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... MDS213 initiates the flow control mechanism appropriate to the current mode of operation. Setting the Flow Control (FC_Enable) bit in the MAC Port Configuration Register (ERC1) turns this operation on, thereby initiating PAUSE frames or applying backpressure flow control when necessary MDS213 25 Zarlink Semiconductor Inc. Data Sheet ...
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... FCS Coverage Late Collision Threshold: Slot Time - Header Size = 4032 bits GMAC Frame with Carrier Extension InterFrame Mac Frame Inter Frame Burst Limit 65,536 bits Carrier Event Duration GMAC Frame Bursting 26 Zarlink Semiconductor Inc. Data Sheet FCS Carrier Extension Mac Frame ...
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... To keep track of per-frame control information, the Frame Engine maintains one Frame Control Buffer (FCB) per frame. FCBs are internal. Since the Frame Engine does not access the external memory for frame control information, this conserves memory bandwidth for better performance. MDS213 27 Zarlink Semiconductor Inc. Data Sheet ...
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... If all buffers are used, no more frames can enter the device. The Frame Engine keeps buffer counters that limit the number of buffers occupied by frames destined for each output port buffer counter exceeds a programmable MDS213 28 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 4 - Frame Buffer Memory Configuration MDS213 One Bank Size ½MB 1MB Table 1 - Type and Size of Memory Chips SRAM 64Kx32 CE SRAM 64Kx32 SRAM 128Kx32 CE SRAM 128Kx32 29 Zarlink Semiconductor Inc. Data Sheet Two Bank Address Size L_A[19:3] 1M L_A[20:3] 2M L_D[31:0] SRAM 64Kx32 L_D[31:0] CE L_A[18:3] MDS213 L_A[19] L_D[63:32] ...
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... K bytes to 1.5M bytes 52 (4 level 26 Kbytes to 208 Kbytes priority) (at 4 level priority level priority) 128 bytes to 32 Kbytes (at 32 Bytes each) 30 Zarlink Semiconductor Inc. Data Sheet Reference CPU, HISC & HISC & HISC & SE ...
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... VLAN MAC Table (2k entry) (each entry=256, 128 or 64 bit) Byte Byte Byte ByteByte ByteByte Byte Figure 5 - Memory Map of Managed System 31 Zarlink Semiconductor Inc. Data Sheet 0 0 Programmable Size Programmable Size 32KB 16 64KB MAX 1/2MB, 1MB or 2MB 0 ...
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... Queue = 128 to 1K) HISC Mailing List (#entry = 128 to 1K) (each mail entry=32 bytes to 64 bytes) Byte Byte Byte ByteByte ByteByte Byte Zarlink Semiconductor Inc. Data Sheet 0 Programmable Size Programmable Size MAX 1/2MB, 1MB or 2MB ...
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... Options + Padding Source Port # Sequence Number Acknowledgement Number Offset Reserved Checksum Options + Padding Data . . . Figure 7 - Typical Packet Header Information 33 Zarlink Semiconductor Inc. Data Sheet Packet FCS Total Length Fragment Offset Header Checksum 64 Bytes Destination Port # Window Urgent Pointer ...
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... Search Engine, instructing it to learn a new address received from the other MDS213. The HISC processor can also use this method to make simple edits to the MCT entries for port changes (i.e. source MAC address is now connected to a different port on the MDS213). MDS213 34 Zarlink Semiconductor Inc. Data Sheet ...
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... Multicast Protocol (IGMP) packets when parsing the packet header information provided by the Frame Engine. IGMP packets are identified when the destination MAC address is 01-00-5E-xx-xx-xx, the Protocol field has the value of 2, and the source IP address is 224.0.0.x. MDS213 35 Zarlink Semiconductor Inc. Data Sheet ...
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... Send and receive frames for management CPU 7.3.1 Resource Initialization The HISC initializes all internal data structures including the mail box and switching database data structures, which are used by the management CPU, HISC and switching hardware. MDS213 36 Zarlink Semiconductor Inc. Data Sheet ...
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... Communication Between Management CPU and HISC The HISC serves as an intermediary communication channel between the switching hardware and the external management CPU. There are two communication mechanisms provided for messages exchanged between the management CPU and HISC. MDS213 37 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 8 - XPipe System Block Diagram for the MDS213 MDS213 X_DO[31:0] X_DI[31:0] X_DCLKO X_DCLKI X_DENO X_DENI X_FCO X_FCI X_DO[31:0] X_DI[31:0] X_DCLKI X_DCLKO X_DENI X_DENO X_FCI X_FCO 38 Zarlink Semiconductor Inc. Data Sheet Receive FIFO Rcvd Ctrl Target Transmit FIFO Xmit Ctrl Source MDS213 ...
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... Transmit Data Enable - Provided by the source end to envelop the entire XPipe message Flow Control Signal- A flow control pin from the target end to signal the source end to active XON/XOFF. 0-64 Words Payload 2-4 Words Header XpipeFlow Message Data Payload Header Figure 9 - XPipe Message Header 39 Zarlink Semiconductor Inc. Data Sheet Description ...
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... It is capable of supporting 10Mbps and 100Mbps data rates • A single clock reference is sourced from the MAC to PHY (or from an external source) MDS213 Cycle #5 ......... D Word 1 D Word 2 D Word 3 Figure 10 - Basic Timing Diagram of XPipe 40 Zarlink Semiconductor Inc. Data Sheet Cycle #6 ......... Last Cycle Idle *1 ......... ......... D Word N . ...
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... Synchronous clock reference for receive, transmit and control interface Input Carrier Sense/Receive Data Valid Input Receive Data Output Transmit Enable Output Transmit Data Input (Not required) Receive Error Table 5 - RMII Specification Signals 41 Zarlink Semiconductor Inc. Data Sheet Direction (with respect to the MAC) ...
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... Intel 486 CPUs • Motorola MPC860 and 801 CPUs • Intel i960Jx CPU • MIPS processor with minimum conversion MDS213 Control Bus MDS213 CPU Control Bus Secondary DEV MDS213 42 Zarlink Semiconductor Inc. Data Sheet Flash Memory Flash Memory ...
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... Primary Device Enable (only in Unmanaged Mode) 0=Secondary Mode 1=Primary Mode (The arbiter is activated in the chip with Primary Device.) 1 Option of merger the P_RDY# and P_BRDY# 0=merged P_RDY# and P_BRDY# pin 1=Separated P_RDY# and P_BRDY# pins Table 6 - Bootstrapping Options 43 Zarlink Semiconductor Inc. Data Sheet ...
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... The connections between the master device, slave device, and the CPU are used for debugging purposes only. See Figure 14. MDS213 Read Cycle wait Read wait Read Read Read Read Figure 13 - Control Bus I/O 44 Zarlink Semiconductor Inc. Data Sheet Sample Burst ...
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... Figure 14 - Block Diagram of the Arbiter No byte swapping for CPU data write in or read out to/from MWDR, MRDR registers. Automatic Byte swapping for CPU data write in or read out to/from MWDR, MRDR registers. 45 Zarlink Semiconductor Inc. Data Sheet MDS213 Secondary Master state Machine ...
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... This device may be customized for different system configurations. MDS213 Byte 1 Byte 0 Byte Byte 1 Byte 3 Byte 2 Figure example of byte swapping MDS213 Slave LE_CLKO LE_SYNCO LE_DO LE_SYNCI LE_DI Figure 17 - LED Interface Connections 46 Zarlink Semiconductor Inc. Data Sheet Byte Byte 0 LED- DECODER LED-DISPLAY ...
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... A synchronous pulse -- defines the boundary between frames. The length of each LED data frame is about 256 bits that shift out by LE_CLKO per bit. A continuous serial stream of data for all status LEDs which repeat once every frame time. 47 Zarlink Semiconductor Inc. Data Sheet ...
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... The end-of-frame (EOF) of the current frame has arrived at the TxFIFO. MDS213 One Frame 256x80nsec Slave dev sub-frame 16 slots Cycle #3 Cycle #4 Cycle #5 Cycle #6 Cycle #7 Cycle #8 bit 2 bit 3 bit 4 bit 5 Figure 18 - Time Diagram of LED Interface 48 Zarlink Semiconductor Inc. Data Sheet P1 bit 6 bit 7 bit 0 bit 1 ...
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... When the destination port is ready to send the frame, the destination Frame Engine send a Data Request message to the source Frame Engine. • After the source Frame Engine receives the Data Request Message, it start to move the frame in granule form, which is directly written in the destination TxFIFO. MDS213 49 Zarlink Semiconductor Inc. Data Sheet ...
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... HISC informs the CPU via a mail, which indicates the handle of FDB. CPU then obtains the frame through the MDS213. After read the frame from FDB, CPU will inform HISC to release the FDB. Finally, HISC passes the release command to Frame Engine to release the FDB accommodated CPU frame. MDS213 50 Zarlink Semiconductor Inc. Data Sheet ...
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... Mirror port Port 0 can be RMII mirror port and mirror port 1-11. Port 13 can be a RMII mirror port and mirror port 0-11, 14-24. Dedicated MII mirror port can mirror port 0-11, 13-24. 51 Zarlink Semiconductor Inc. Data Sheet PM_DO[1:0] PM_DENO MII ...
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... MP0=1 Mirror to port 0 MP0=0 Mirror not go to port 0. i.e., to PM_DO pins. Bit [31:15]Reserve We use examples to illustrate how to set the APMR register. The following examples are based on the configuration of Figure 20. MDS213 Rx/ L Zarlink Semiconductor Inc. Data Sheet 0 Mirror Port ...
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... Set APMR[13]= Don't careBit[13] has meaning only in the chip of mirrored port Set APMR[14]=0Port 13 is not the mirroring port Note that CPU needs to find out the speed of the mirrored port and configures the mirroring port to the same speed. MDS213 53 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN member can be covered by a wide range of switches in a network. GVRP allows both VLAN-aware workstations and switches to issue and revoke VLAN memberships. VLAN-aware switches register and propagate VLAN membership to all ports belonging to the active topology of the VLAN. MDS213 54 Zarlink Semiconductor Inc. Data Sheet ...
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... C V P12P11 P10 P28 Figure 21 - VLAN ID Table 55 Zarlink Semiconductor Inc. Data Sheet 0 FDB block must start from 0 Programmable Size Programmable Size 32KB 64 16KB (up to the number of supported VLAN ...
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... VLAN. The total size of the VLAN Table may be 64 16KB. This table must be located at the boundary of its own table size. MAC handle This table can be accessed by CPU software through CPUIRCMD and CPUIRDAT registers. MDS213 256 ......................... 100 Figure 22 - VLAN MAC Table 56 Zarlink Semiconductor Inc. Data Sheet VLAN ID ...
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... Internet Group Management Protocol (IGMP) that support automatic multicast group membership. IGMP is configured to create, update, and/or remove MDS213 13 12 VLAN Port Enable [12: Priority 57 Zarlink Semiconductor Inc. Data Sheet 0 TAG Enable [12: Port VLAN ID ...
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... MAC address is 01-00-5E-xx-xx-xx, Protocol field value equals 2 and the destination IP address is 224.0.0.x. The external CPU then instructs the HISC to setup an MCT entry for this IP Multicast Address in the Switch Database Memory. If this is a new IP Multicast group, it sets up an entry in the VLAN Port Mapping Table by itself. MDS213 58 Zarlink Semiconductor Inc. Data Sheet ...
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... MAC3 MAC2 MAC1 Port number MAC5 P 59 Zarlink Semiconductor Inc. Data Sheet MAC0 MAC4 Next Handle ...
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... MDS213 VLAN ID IP1 IP0 C VLAN Index IP3 Zarlink Semiconductor Inc. Data Sheet IP2 Next Handle ...
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... TGID will be compared against the Trunk Group ID in the source MCT to decide whether the source MAC address has moved to another Trunk Group or not. MDS213 If a programmable option, DCR2, bit 26, is turned on, the 61 Zarlink Semiconductor Inc. Data Sheet ...
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... Table must be set by the CPU to THKM[0:7] registers beforehand. The format of this table and the method of setting it up are shown below. MDS213 TG provided by Dev ID Search Eng (1 bit) TG Hash Key . (3 bits Hash Keys . . . Port Mapping Table for MDS213 Figure 23 - Port Mapping Table 62 Zarlink Semiconductor Inc. Data Sheet Port ID (4 bit) ...
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... VLAN Member Port AND Forwarding Ports Figure 24 - Forwarding Port Mask Table 63 Zarlink Semiconductor Inc. Data Sheet CPU sets up this table as follows: 1. Set up one entry of these registers at a time until table is exhausted. 2. Set all bits not in any Trunk Group to 1. ...
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... Key=3 VLAN Member for INDEX=5 Forwarding Ports Turn this port off since port 2 has the same TGID of source port 0 64 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN ID & MAC member Table Base Pointer MBCR Mulitcast Buffer Control Register RAMA RAM block access Register Reserve Must Set to "0x0001 0008" Reserve Must Set to "0x0001 0000" MDS213 Description Table 8 - MDS212 Register Map 65 Zarlink Semiconductor Inc. Data Sheet Address W/R 7C0 W/-- 7C0 --/R 7C4 W/R 7C8 W/R 7CC ...
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... MII Command Register AMIIS MII Status Register AFCRIA Flow Control Ram Input Address AFCRID0 Flow Control Ram Input Data AFCRID1 Flow Control Ram Input Data Table 8 - MDS212 Register Map (continued) MDS213 Description 66 Zarlink Semiconductor Inc. Data Sheet Address W/R 740 W/R 744 W/R 74C W/R 750 W/R 708 ...
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... IP multicast MAC address Mask High Register - Byte[5:4] CFCBHDL FCB Handle Register for CPU CPUIRCMD CPU Internal RAM Command Register CPUIRDAT0 CPU Internal RAM Data Register - 0 Table 8 - MDS212 Register Map (continued) MDS213 Description 67 Zarlink Semiconductor Inc. Data Sheet Address W/R 670 W/R 674 W/R 678 W/R 67C ...
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... Device Reset: -- Resets all internal state machines of each device and stays in RESET state (except the Processor Bus Interface logic). Execution: -- Allows state machines to start their normal operations. No-Op No-Op Table 9 - Global Control Register 68 Zarlink Semiconductor Inc. Data Sheet Address W/R 58C W/R 590 W/R ...
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... Execution: Device is under normal operation. Table 10 - Device Status Register Write/Read Signature 8-bit Device Signature 5-bit Device ID (Read/Write) Direct Access, Write/Read Configuration 69 Zarlink Semiconductor Inc. Data Sheet 1 0 Status Rev ...
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... Default = 0 Default = 128K x 32-bit 11 = 512K x 32-bit Default = enable aging Default = 00 01=mode 1 11=mode 3 Default = 01 01= 9 11= TDB Default = VLAN Aware Default = 1 0 =IP Multicast Enable Default = Learning Enable Default=0 1= Partial Synchronization for MCT table 70 Zarlink Semiconductor Inc. Data Sheet ...
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... Gate 0ff TX_En when Link down IP Multicast privileges enable: IP multicast traffic has a privilege over regular multicast traffic. 0= disable (Read only bit) (Read only bit) 71 Zarlink Semiconductor Inc. Data Sheet Default = enable aging Power-up default = Forward oversize frames 1 = enable 1 = collect status in ...
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... Write FIFO Empty, the FIFO that CPU writes is empty Reserved Queue Manager Interface Status CPU Input Queue is ready for CPU to write into queue CPU Input Queue is full Direct Access, Write/Read WCL 72 Zarlink Semiconductor Inc. Data Sheet Mem_Stat RCL Default=16 Default=16 ...
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... Link manager informs CPU that at least 16 Free Mail entry available after CPU encounters empty Free Mail list situation. Interrupt from MAC ports Bit [11] for Port 0, Bit [12] for Port 1 … Bit [23] for port 12, port Giga port 73 Zarlink Semiconductor Inc. Data Sheet Read only Write/Read Write only MA ...
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... BE [1] via FIFO, Write Address MA[20:2] I/E Lock Flag memory LK=0 Unlock Swap Byte Order Buffer memory address Bit [20:2] - Indicate the Address is Internal or External memory I/E=0 Internal memory 74 Zarlink Semiconductor Inc. Data Sheet I/E=1 External memory Bit [29] Bit [28] BE [1] BE [0] BE [ ...
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... D-words. Burst size for external memory 16-Dwords 00001 = 1 D-word, ……01000 = 8 D-word 01111 = 15 D-word Valid value range for internal memory Valid value range for external memory 16} 75 Zarlink Semiconductor Inc. Data Sheet (Bit [1:0] = 00) 10000= 16 D-word ...
Page 76
... ID Table is 32KB) The size of VLAN MAC Table Default=11 00= reserved 10=32K (for 128 VLANs)11=64K (for 256 VLANs) VLAN MAC Table Base, serves as [20:14] bit of address. This table indicates the association of MAC address and VLAN 76 Zarlink Semiconductor Inc. Data Sheet Byte [ ...
Page 77
... Direct Access, Write/Read ST_ADR R Read/write burst (length) of RAM Block. (Unit = 1double words) Read/Write Start Address. RAM Block Access Write/Read indicator 1 = Write 0 = Read 77 Zarlink Semiconductor Inc. Data Sheet RMC_BUF_RSV MAX_MC_FD 01=50% 11= 100 BST_CNT ...
Page 78
... Aging Time = (Number of valid FCB Buffers* Aging Timer Base) msec Direct Access, Write/Read Buffer Low Threshold - The number of frame control buffer handles left in the Queue to be considered as running low and trigger the interrupt to the CPU. 78 Zarlink Semiconductor Inc. Data Sheet 0x0008 0x0000 0 ...
Page 79
... Selection for Low or High Limit of Buffer Counter for Remote device 13 bits maps to 13 ports in Remote Device 1 = select hi limit 0 = select low limit Direct Access, Write only 32-bit data from CPU input queue 79 Zarlink Semiconductor Inc. Data Sheet 0 Low Limit 0 0 ...
Page 80
... Halt State: -- Stopped HISC execution, waiting for HT=0. Micro-Code Loading State: -- Stopped HISC execution, increment IP for every Wr/Rd to HMPC Start State: -- Reset IP=0, and start HISC execution. Execution State: -- Continue HISC execution without reset IP. Illegal State. 80 Zarlink Semiconductor Inc. Data Sheet ...
Page 81
... HISC Instruction Word [31:0] HISC Instruction Word has total 40 bit-wide. Needs to be broken into two registers. Direct Access, Write/Read 8 7 HISC Instruction [39:32] Direct Access, Write/Read 16 15 DataBit[31:0] Direct Access, Write/Read 20 19 Data bit[51:32] (Write only bits) 81 Zarlink Semiconductor Inc. Data Sheet ...
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... Suggestion value: 5msec. MDS213 Direct Access, Write/Read Time U2MR Unicast to CPU rate Base 001 = 200us 010 = 400us 011 = 800us 101 = 3.2ms 110 = 6.4ms 111 = 100us Direct Access, Write/Read MCT Aging Timer 82 Zarlink Semiconductor Inc. Data Sheet Multicast to CPU rate 0 ...
Page 83
... Write/Read 8 7 8-bit Table entry Index Value set to 0 Direct Access, Write/Read Trunking port Device ID Direct-Access Write/Read UC_TM MC_TM MC_TM Default =5 Default =6 Default =5 Default =5 83 Zarlink Semiconductor Inc. Data Sheet 0 Entry Index Port G_TM 100_TM ...
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... In Read mode, CPU receives Mail from HISC 31 30 MDS213 Direct Access, Write/Read 22 21 MCT threshold Alert system when free MCT entries are below this threshold Direct Access, Read only Direct Access, Write/Read 21 20 Entry Handle 84 Zarlink Semiconductor Inc. Data Sheet ...
Page 85
... AXSC - Transmission Scheduling Control Register Access: Non-Zero-Wait-State, Address: h64C 31 MDS213 Direct Access, Write/Read 21 20 Entry Handle Direct Access, Write/Read Direct Access, Write/Read 12 11 QSW2 85 Zarlink Semiconductor Inc. Data Sheet VLAN Type Code QSW1 QSW0 ...
Page 86
... Tx FIFO reaches the threshold or EOF. Direct Access, Write only REG_AD Start of frame - always = "01" Operation code - "10" for read command and "01" for write command 5-bit PHY Address 86 Zarlink Semiconductor Inc. Data Sheet depart_time qmt_cnt DATA (16-bit) ...
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... Read Data from PHY Description Data field contains valid data from the PHYs Data field contains invalid data from the PHYs Data field is not ready to be read by Switch Manager CPU Direct Access, Write only 87 Zarlink Semiconductor Inc. Data Sheet DATA (16-bit address ...
Page 88
... Write only Content of Input Flow Control Frame[63:32] Direct Access, Write/Read XON_Th queue aging function enable When stack is full, enable flush procession 0 = disable 1 = enable Full Duplex XON enable 0 = disable 1 = enable 88 Zarlink Semiconductor Inc. Data Sheet ...
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... MAC Offset[n] is defined by the following registers MDS213 Direct Access, Write/Read 16 15 MAC 2 MAC 1 MAC 5 Direct Access, Write/Read 16 15 Frame Type Direct Access, Write/Read MAC 2 MAC 1 MAC 5 89 Zarlink Semiconductor Inc. Data Sheet MAC 0 MAC MAC MAC 4 ...
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... Bit [15:12] MAC Offset address for Port 11 Bit [19:16] MAC Offset address for Port 12 Bit [31:20] Reserved MDS213 Direct Access, Write/Read Direct Access, Write/Read Port10_offset Port9_offset Port11_offset Port12_offset 90 Zarlink Semiconductor Inc. Data Sheet Port8_offset ...
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... HBK_TM_100 Holding time to remote station for 100Mbps port when the chip detects the head of line blocking counter has run out. The holding time value is embedded in the flow control frame sent to the remote station. 91 Zarlink Semiconductor Inc. Data Sheet XOFF_CKTM 0 ...
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... Direct Access, Write/Read 16 15 FL_OFF_100M Off time to remote station for 100Mbps Port when the chip detects the buffer resource is not available. The OFF time value is embedded in the flow control frame sent to the remote station. 92 Zarlink Semiconductor Inc. Data Sheet ...
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... Not support 1G port Mirroring.) Indicates whether the mirror is receiving data or transmitting data Mirror to Port 0 (Default=0) MP0=1 Mirror to port 0 MP0=0 Mirror not go to port 0 Direct Access, Write/Read Zarlink Semiconductor Inc. Data Sheet 0 0 Mirror Port ...
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... Forwarding Port mask for hash key 0 Forwarding Port mask for hash key 1 Forwarding Port mask for hash key 2 Forwarding Port mask for hash key 3 Forwarding Port mask for hash key 4 Forwarding Port mask for hash key 5 94 Zarlink Semiconductor Inc. Data Sheet ...
Page 95
... These two registers define the MAC address signature of IP multicast. • Default = h" 01:00:5e:7f:ff:ff" MDS213 Forwarding Port mask for hash key 6 Forwarding Port mask for hash key MAC 2 MAC 1 MAC 5 95 Zarlink Semiconductor Inc. Data Sheet 0 TK_MSK MAC 0 MAC 4 ...
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... CPUIRDAT2: Data Register for specific entry of content Bit[95 64] • CPUIRRDY: Data Read Ready. MDS213 MASK 2 MASK 1 MASK 5 Direct Access, Read only 10 9 FCB Handle Address FCB Handle Ready 0=Not Ready 96 Zarlink Semiconductor Inc. Data Sheet MASK 0 MASK 4 0 FCB_Handle[9:0] 1=Ready ...
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... MCID=1 Use Table VMAP=1 Use VLAN port mapping Table (VMAP) BMCT=1 Use Buffer Manager Control Table (BM control) FCB=1 Use FCB Table QCNT=1 Use Transmission Queue control Table (QM control) Command Ready 0=Not Ready 1=Ready 97 Zarlink Semiconductor Inc. Data Sheet 0 Entry Index [9:0] ...
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... Ethernet MAC Port Identify the ports associated with each VLAN 0 = disable 1 = enable one bit for each Ethernet MAC Port 0 = disable 1 = enable Remote Ports Enable: Indicate some members in the remote device. 0=disable1=enable 98 Zarlink Semiconductor Inc. Data Sheet 0 0 MCID[5:0] 0 VLAN Port Enable [12:0] ...
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... Address_Write_Entry[2:0]= 0 (The address [2:0] is always equal to 0.) Read Pointer Address_Read_Entry[20:9]=Base[11:0]+RdPt[9:7] Address_Read_Entry[9:3]= RdPt[6:0] Address_Read_Entry[2:0]= 0 (The address [2:0] is always equal to 0.) Cache Valid CV=1, Cache of Queue Entry QE[31:0] is valid. Cache a queue entry 99 Zarlink Semiconductor Inc. Data Sheet BM[11: QS[2:0] Base[11:0] WrPT[9:6] RdPt[9:0] Cache Queue Entry[31:17] ...
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... MII related controls applies to Port [1:0] only Port 12 is always dedicated to GMAC MDS213 Write/Read Data in Data registers is ready for CPU Read Direct Access, Write/Read UDEF3 UDEF2 01=16msec 11=64msec 01= 100M/16=6.25Mhz 11= 100M/64-1.5625Mhz 100 Zarlink Semiconductor Inc. Data Sheet UDEF1 ...
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... ECR0_p4 ECR0_p5 ECR0_p6 ECR0_p7 ECR0_p8 ECR0_p9 ECR0_p10 ECR0_p11 ECR0_p12 Reset Receiver Reset Transmitter RX Enable RST_PCS, Reset PCS logic (Only apply Gigabit Port) Direct Access, Write/Read ECR1_p0 ECR1_p1 ECR1_p2 ECR1_p3 ECR1_p4 ECR1_p5 101 Zarlink Semiconductor Inc. Data Sheet ...
Page 102
... Enables full duplex modeDefault =0 - Half Duplex Selects the output polarity of Full_Duplex control signal 0 = Low true (Default High true Setting this bit cause internal connect TXCLK, TXD, TXD[0:3] to RXCLK, RXD, RXD[0:3] 102 Zarlink Semiconductor Inc. Data Sheet ...
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... Default =0 - Disable Inter-frame Gap (Default=7'd24) Use to adjust the inter-frame gap. (Unit =transmit Clock.) The default is 7'd24, stands for 24 transmit clock (each clock transmit 4 bits). Direct Access, Write/Read x: port number ECR2_p0 ECR2_p1 ECR2_p2 ECR2_p3 ECR2_p4 103 Zarlink Semiconductor Inc. Data Sheet ...
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... If set, the status counter wrap around signal is masked. If set, the Link_Up and Link_Down Interrupts are masked. Direct Access, Read only x: port number ECR3_p0 ECR3_p1 ECR3_p2 ECR3_p3 ECR3_p4 ECR3_p5 ECR3_p6 ECR3_p7 ECR3_p8 ECR3_p9 ECR3_p10 ECR3_p11 ECR3_p12 104 Zarlink Semiconductor Inc. Data Sheet Mask ...
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... Direct Access, Read only x: port number ECR4_p0 ECR4_p1 ECR4_p2 ECR4_p3 ECR4_p4 ECR4_p5 ECR4_p6 ECR4_p7 ECR4_p8 ECR4_p9 ECR4_p10 ECR4_p11 ECR4_p12 Status Wrapped Signal Bytes Sent(D) Unicast Frames Sent Flow Control Sent 105 Zarlink Semiconductor Inc. Data Sheet Status 1=Link UP 0 ...
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... Frames with length between 128-255 bytes Frames with length between 256-511 bytes Frames with length between 512-1023 bytes Frames with length between 1024-1528 bytes Undersize Frames Fragment CRC Short Event Collision Drop Filtering Counter Delay exceed discard counter Late Collision 106 Zarlink Semiconductor Inc. Data Sheet ...
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... Direct Access, Write/Read x: port number PVIDR_p0 PVIDR _p1 PVIDR _p2 PVIDR _p3 PVIDR _p4 PVIDR _p5 PVIDR _p6 PVIDR _p7 PVIDR _p8 PVIDR _p9 PVIDR _p10 PVIDR _p11 PVIDR _p12 Priority 107 Zarlink Semiconductor Inc. Data Sheet 0 Port VLAN ID ...
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... Thermal resistance between junction and case jc When external heat sink is attached, θ Note 1: MDS213 -0 (VCC + 3 +70 C AMBIENT Min 2.4 2.0 is reduced by about 8-12% in still air. JA 108 Zarlink Semiconductor Inc. Data Sheet Type Max Unit 100 MHz 270 351 mA 780 1014 mA V 0.4 V VCC + 2 ...
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... XPIPE INTERFACE - Output valid delay timing Figure 26 - XPIPE Interface - Output Valid Delay Timing MDS213 X_DCLKI X_DI[31:0] X_DENI X_FCI XPIPE INTERFACE - Input setup and hold timing S_CLK X_DCLK 109 Zarlink Semiconductor Inc. Data Sheet X17 X18 X19 X20 X21 X22 X15 X16 ...
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... X_DI[31:0] input set-up time X18 X_DI[31:0] input hold time X19 X_DENI input set-up time X20 X_DENI input hold time X21 X_FCI input set-up time X22 X_FCI input hold time Table Characteristics - XPipe Interface Zarlink Semiconductor Inc. MDS213 -100MHZ Min (ns) Max (ns ...
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... P26-min P_GNT1 Figure Characteristics - CPU BUS Interface MDS213 P_CLK P_RST# P_ADS# P_RWC# P_CSI# P_A[10:1] P_D[31:0] CPU BUS INTERFACE - Input setup and hold timing P_REQC P_REQ1 111 Zarlink Semiconductor Inc. Data Sheet P10 P11 P12 P15 P16 ...
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... P22 P_ADS# output valid delay P23 P_RDY# output valid delay P24 P_INT output valid delay P25 P_GNTC output valid delay P26 P_GNT1 output valid delay Table Characteristics - CPU Bus Interface Zarlink Semiconductor Inc. MDS213 -66MHZ Min (ns) Max (ns ...
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... L_D[63:0] L2 L_A[20:3] L_ADSC# L_BW[7:0]# L_WE[1:0]# L_OE[1:0]# Parameter Min (ns 113 Zarlink Semiconductor Inc. Data Sheet L3-max L3-min L4-max L4-min L6-max L6-min L7-max L7-min L8-max L8-min L9-max L9-min LOCAL MEMORY INTERFACE - Output valid delay timing -100MHZ Note Max (ns) ...
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... Figure 30 - Port Mirroring Interface - Output Delay Timing M_CLKI M[11:0]_RXD[1:0] M[11:0]_CRS_DV Figure 31 - Reduce Media Independent Interface - Input Setup and Hold Timing M_CLKI M[11:0]_TXEN M[11:0]_TXD[1:0] Figure 32 - Reduce Media Independent Interface - Output Delay Timing Zarlink Semiconductor Inc. MDS213 PM1 PM2 PM3 PM4 PM5 PM6-max PM6-min ...
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... Table Characteristics - Reduced Media Independent Interface MDS213 -50 MHZ Min (ns) Max (ns) 1 -50 MHZ Min (ns) Max (ns) 1 115 Zarlink Semiconductor Inc. Data Sheet Note Reference Input Clock 30pf 30pf L Note Reference Input Clock 30pf L 11 ...
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... M[12]_TX_EN M[12]_TX_ER Output Valid Delay Timing G10 -125 MHZ Min (ns) Max (ns 116 Zarlink Semiconductor Inc. Data Sheet G11-max G11-min G12-max G12-min G13-max G13-min Note Input Reference Clock Output Reference Clock 20pf 20pf L ...
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... Table Characteristics - Physical Media Attachment Interface LED_CLKO LED_DO LED_SYNCO Figure 35 - LED Interface - Output Delay Timing MDS213 GP1 GP2 GP3-max GP3-min -125 MHZ Min (ns) Max (ns LE1 LE2-max LE2-min LE3-max LE3-min 117 Zarlink Semiconductor Inc. Data Sheet Note Input Reference Clock Output Reference Clock 20pf L ...
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... Symbol Parameter LE1 LE_CLKO LE2 LE-DO Output Valid Delay LE3 LE_SYNCO Output Valid Delay Table Characteristics - LED Interface MDS213 Variable Freq. Min (ns) Max (ns 118 Zarlink Semiconductor Inc. Data Sheet Note Reference Output Clock 30pf 30pf L ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...