RS5C348A-E2 RICOH Co.,Ltd., RS5C348A-E2 Datasheet

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RS5C348A-E2

Manufacturer Part Number
RS5C348A-E2
Description
RS5C348A-E2Real-Time Clock
Manufacturer
RICOH Co.,Ltd.
Datasheet

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查询RS5C348A供应商
4-WIRE SERIAL INTERFACE REAL-TIME CLOCK IC
S
WITH VOLTAGE MONITORING FUNCTION
R 5C348A/B
APPLICATION MANUAL
ELECTRONIC DEVICES DIVISION
NO.EA-054-9908

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RS5C348A-E2 Summary of contents

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SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION APPLICATION MANUAL ELECTRONIC DEVICES DIVISION R 5C348A/B S NO.EA-054-9908 ...

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The products and the product specifications described in this application manual are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales representatives ...

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R 5C348A/B APPLICATION MANUAL CONTENTS ...................................................................................................... OUTLINE .................................................................................................. FEATURES ........................................................................................ BLOCK DIAGRAM ............................................................................................. APPLICATIONS ....................................................................................... SELECTION GUIDE ................................................................................... PIN CONFIGURATION ...................................................................................... PIN DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS DC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS GENERAL DESCRIPTION FUNCTIONAL DESCRIPTIONS ......................................................................................... ...

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... The 32-kHz clock circuit can be disabled by certain register settings for the R 5C348A but cannot be disabled by any register settings for the R 5C348B. Both these models come in an ultra-compact 10-pin SSOP (RS5C348A/B with a height of 1.25mm and a pin pitch of 0.5mm) and 10-pin SSOP-G(RV5C348A/B with a height of 1.2mm and a pin pitch of 0.5mm.) FEATURES • ...

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... Computer (desk-top and mobile PC, portable word-processor, PDA, electric note or video game) • AV components (portable audio unit, video camera,camera, digital camera or remote controller) • Home appliances (rice cooker, electric oven) • Other (car navigation system, multi-function watch) SELECTION GUIDE RS5C348A (Pitch 0.5mm, Height 1.25mm, Size 6.4 3.5mm) RS5C348B RV5C348A PIN CONFIGURATION (Pitch 0 ...

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PIN DESCRIPTIONS Pin No. Symbol Item 7 CE Chip Enable Input 2 SCLK Serial Clock Input 4 SI Serial Input 3 SO Serial Output 6 INTR Interrupt Output 1 32KOUT 32-kHz Clock Output 9 OSCIN Oscillatory Circuit 8 OSCOUT Input/Output ...

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R 5C348A/B ABSOLUTE MAXIMUM RATINGS Symbol Item V Supply Voltage DD V Input Voltage 2 I Output Voltage Output Voltage 2 P Power Dissipation D Topt Operating Temperature Tstg Storage Temperature Absolute Maximum ratings are threshold limit ...

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DC ELECTRICAL CHARACTERISTICS Symbol Item V “H” Input Voltage IH SCLK,CE “L” Input Voltage IL I “H” Output Current INTR, 32KOUT OL1 “L” Output Current I SO,32KOUT OL2 I Input Leakage Current SCLK ...

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R 5C348A/B AC ELECTRICAL CHARACTERISTICS Symbol Item t CE Set-up Time CES t CE Hold Time CEH t CE Recovery Time CR f SCLK Clock Frequency SCLK t SCLK Clock “H” Time CKH t SCLK Clock “L” Time CKL t ...

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GENERAL DESCRIPTION 1. Interface with CPU The R 5C348A/B are connected to the CPU by four signal lines CE (Chip Enable), SCLK (Serial Clock), SI (Serial Input), and SO (Serial Output), through which they read and write data from and ...

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R 5C348A/B 5. Oscillation Halt Sensing Function and Supply Voltage Monitoring Function The R 5C348A/B incorporate an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt, thereby identifying whether they are powered on from ...

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FUNCTIONAL DESCRIPTIONS 1. Address Mapping Address Second Counter Minute Counter Hour Counter ...

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R 5C348A/B 2. Register Settings 2.1 Control Register 1 (at Address Eh WALE DALE 12/24 WALE DALE 12/ Default settings: Default value means read/written values when the XSTP bit is set to “1” ...

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CLEN2 (R 5C348A) 32kHz Clock Output Bit 2 CLEN2 (R 5C348A) 0 Enabling the 32-kHz clock circuit 1 Disabling the 32-kHz clock circuit For the R 5C348A, setting the CLEN2 bit or the CLEN1 bit (D3 in the control ...

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R 5C348A/B 2.1 and Periodic Interrupt Selection Bits Waveform mode — — Pulse Mode ...

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Relation Between the Mode Waveform and the CTFG Bit • Pulse mode CTFG bit INTR pin (Increment of second counter the pulse mode, the increment of the second counter is delayed by approximately 92µs from the falling edge ...

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R 5C348A/B 2.2 Control Register 2 (at Address Fh VDSL VDET SCRATCH1 VDSL VDET SCRATCH1 Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on ...

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XSTP Oscillation Halt Sensing Bit XSTP 0 Sensing a normal condition of oscillation 1 Sensing a halt of oscillation The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation halt sensing circuit ...

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R 5C348A/B 2.2-6 CTFG Periodic Interrupt Flag Bit CTFG 0 Periodic interrupt output “H” (OFF) 1 Periodic interrupt output “L” (ON) The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin (“L”). ...

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Time Counters (at Addresses 0h to 2h) · Time digit display (BCD format) as follows: The second digits range from and are carried to the minute digit in transition from 59 to 00. The minute digits ...

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... RS5C348A/B 2.4 Day-of-week Counter (at Address 3h — — — Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. * · The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. ...

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Year Counter (at Address 6h Indefinite Indefinite Indefinite ) Default settings: Default value means read/written values when the XSTP bit is set to “1” ...

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R 5C348A/B An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm (2 / (32768 20 = 3.051ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time ...

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Example of Alarm Time Setting Sun. Mon. Tue. Wed. Thu. Fri. Preset alarm time 00:00 a.m. on all days 1 1 01:30 a.m. on all days 1 1 11:59 a.m. on all days 1 1 00:00 p.m. ...

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R 5C348A/B USAGES 1. Data Transfer Formats 1.1 Timing Between CE Pin Transition and Data Input/Output The R 5C348A/B adopt a 4-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), SI (Serial Input), and SO ...

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Data Transfer Formats Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). ...

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R 5C348A/B 1.3-2 Burst Writing Data Transfer Format The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which ...

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Burst Reading Data Transfer Format The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data ...

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R 5C348A/B 1.5 Considerations in Reading and Writing Time Data Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. For example, suppose a carry out of ...

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Good Example Time span more CE SI F4h SO Specifying Fh in the Reading from the control register 2 address pointer Writing 4h to the at address Fh transfer format register Bad Example (1): Where the ...

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R 5C348A/B 2. Configuration of Oscillation Circuit and Correction of Time Count Deviations 2.1 Configuration of Oscillating Circuit R 5C348A/B VDD 10 OSCIN OSCOUT The oscillation circuit is driven at ...

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Measurement of Oscillation Frequency R 5C348A/B VDD OSCIN 32.768kHz OSCOUT 32KOUT The R 5C348A is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin at power-on conditionally on setting the XSTP bit to ...

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R 5C348A/B Course (A) When the time count precision of each real-time clock is not to be adjusted, the crystal oscillator intended for use with that real-time clock may have any C frequency variations which are selectable within the allowable ...

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Another advisable way to select a crystal oscillator having an optimum C crystal oscillator intended for use with the R 5C348A/B. Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization ...

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R 5C348A/B 2.4-2 When Oscillation Frequency is Equal to Target Frequency (There is Neither a Time Count Gain nor a Time Count Loss) Writing the oscillation adjustment value setting of “0”, “+1”, “–64”, or “–63” to the oscillation adjustment register ...

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Oscillation Halt Sensing and Supply Voltage Monitoring The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage ...

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R 5C348A/B Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following: 1) Instantaneous power-down on the V 2) Condensation on the crystal oscillator 3) On-board noise to the crystal oscillator 4) Applying to individual ...

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Alarm and Periodic Interrupt The R 5C348A/B incorporate the alarm circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals, respectively, for output from the INTR pin as described below. 1) Alarm ...

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R 5C348A/B 4.1 Alarm Interrupt The alarm circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the control register 1) and the flag bits (i.e. the WAFG and DAFG bits in the control register 2). ...

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Periodic Interrupt Setting of the periodic selection bits (CT modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is cyclically driven low ...

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R 5C348A/B Relation Between the Mode Waveform and the CTFG Bit • Pulse Mode CTFG bit INTR pin (Increment of second counter the pulse mode, the increment of the second counter is delayed by approximately 92 µs from ...

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Typical Applications 6.1 Typical Power Circuit Configurations Sample circuit configuration 1 R 5C348A/B OSCIN 32.768kHz OSCOUT VDD 1 * VSS Sample circuit configuration 2 R 5C348A/B OSCIN 32.768kHz OSCOUT VDD VSS 1) Install bypass capacitors for high-frequency and low- ...

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R 5C348A/B 6.2 Connection of INTR Pin The INTR pin follows the N-channel open drain output logic and contains no protective diode on the power supply side. As such, it can be connected to a pull-up resistor ...

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Connection of CE Pin Connection of the CE pin requires the following considerations: 1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it should be driven low or open ...

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... R 5C348A/B 7. Typical Characteristics Test Circuit • R 5C348A/B VDD OSCIN 32.768kHz OSCOUT 32KOUT SS V 7.1 Timekeeping Current vs. Supply Voltage (with no 32-kHz clock output) (CE=Open, Output=Open, Topt=25˚C, RS5C348A) 1 0.8 0.6 0.4 0 Supply Voltage V 7.3 CPU Access Current vs. SCLK Clock Frequency (Output=Open, Topt=25˚ =5V ...

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Oscillation Frequency Deviation vs. External C (V =3V, Topt=25˚C, DD External C =0pF as standard –5 –10 –15 –20 –25 –30 –35 – External C (pF) G 7.7 Oscillation Frequency Deviation vs. ...

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R 5C348A/B 8. Typical Software-based Operations 8.1 Initialization at Power-on Power-on XSTP=1? Set Oscillation Adjustment Register and Control Registers 1 and 2, etc. 1) After power-on from 0 volts, the start of oscillation and the process of internal initialization require ...

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Reading Time and Calendar Data 8.3-1 Ordinary Process of Reading Time and Calendar Data Wait for 31 s Read from Time Counter and Calendar Counter 8.3-2 Basic Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt Set ...

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R 5C348A/B 8.3-3 Applied Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can ...

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Interrupt Process 8.4-1 Periodic Interrupt Set Periodic Interrupt 1 * Cycle Selection Bits Generate Interrupt to CPU NO CTFG=1? YES Periodic Interrupt Process 2 * Write “ ,1, ,1, ,0,1,1” to Control Register 2 8.4-2 Alarm Interrupt WALE or ...

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... R 5C348A/B PACKAGE DIMENSIONS • RV5C348A/B (10-pin SSOP-G) • RS5C348A/B (10-pin SSOP) 48 (Unit : mm 0.5 0.1 0.2 0.1 0.15 M 3.50 0 0.50 0.9MAX. 0.1 0.2 0.1 0.1 M ...

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... The RV5C348A/B have one designated taping direction. The product designations for the taping components are “RV5C348A-E2” and “RV5C348B-E2”. 0.3 2.0MAX. • RS5C348A/B (10-pin SSOP) The RS5C348A/B have one designated taping direction. The product designations for the taping components are “RS5C348A-E2” and “RS5C348B-E2”. 0.3 2.7MAX. (Unit : mm) +0.1 4.0 0.1 ø ...

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RICOH COMPANY, LTD. ELECTRONIC DEVICES DIVISION HEADQUARTERS 13-1, Himemuro-cho, Ikeda City, Osaka 563-8501, JAPAN Phone +81-727-53-6003 Fax +81-727-53-2120 YOKOHAMA OFFICE (International Sales) 3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222-8530, JAPAN Phone +81-45-477-1697 Fax +81-45-477-1694 · 1695 http://www.ricoh.co.jp/LSI/english/ RICOH CORPORATION ELECTRONIC ...

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