SC16C650AIN40 Philips Semiconductors, SC16C650AIN40 Datasheet
SC16C650AIN40
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SC16C650AIN40 Summary of contents
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SC16C650A Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder Rev. 04 — 20 June 2003 1. General description The SC16C650A is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is ...
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... SC16C650AIA44 PLCC44 plastic leaded chip carrier; 44 leads SC16C650AIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 SC16C650AIN40 DIP40 plastic dual in-line package; 40 leads (600 mil) 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder 5-, 6-, 7-, or 8-bit characters ...
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... Philips Semiconductors 4. Block diagram SC16C650A D0–D7 DATA BUS IOR, IOR AND IOW, IOW CONTROL LOGIC RESET A0–A2 REGISTER CS0, CS1, CS2 SELECT AS LOGIC DDIS INT TXRDY RXRDY INTERRUPT CONTROL LOGIC Fig 1. Block diagram. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder ...
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... Philips Semiconductors 5. Pinning information 5.1 Pinning Fig 2. PLCC44 pin configuration. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder RCLK SC16C650AIA44 CS0 14 CS1 15 16 CS2 BAUDOUT 17 Rev. 04 — 20 June 2003 SC16C650A 39 RESET ...
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... Philips Semiconductors Fig 3. LQFP48 pin configuration. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder RCLK SC16C650AIB48 CS0 9 CS1 10 11 CS2 BAUDOUT 12 Rev. 04 — 20 June 2003 SC16C650A RESET 34 OUT1 ...
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... Philips Semiconductors Fig 4. DIP40 pin configuration. 5.2 Pin description Table 2: Pin description Symbol Pin PLCC44 LQFP48 DIP40 A0-A2 28, 27, 28, 27, 28, 27 BAUDOUT 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder ...
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... Philips Semiconductors Table 2: Pin description …continued Symbol Pin PLCC44 LQFP48 DIP40 CS0, CS1, 14, 15, 9, 10, 12, 13, CS2 CTS D(7:0) 2-9 43-47, 8-1 2-4 DCD DDIS DSR DTR INT OUT1, OUT2 38, 35 34 RCLK 9397 750 11622 ...
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... Philips Semiconductors Table 2: Pin description …continued Symbol Pin PLCC44 LQFP48 DIP40 IOR, IOR 24, 25 19 RTS RXRDY TXRDY 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder ...
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... Philips Semiconductors Table 2: Pin description …continued Symbol Pin PLCC44 LQFP48 DIP40 IOW, IOW 20, 21 16 XTAL1 [1] XTAL2 [1] In sleep mode, XTAL2 is left floating. 6. Functional description The SC16C650A provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections ...
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... Philips Semiconductors 6.1 Internal registers The SC16C650A provides 15 internal registers for monitoring and control. These registers are shown in in the standard 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR) ...
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... Philips Semiconductors a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. Table 4: Selected trigger level (characters ...
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... Philips Semiconductors characters are not placed (stacked) in the user accessible RX data buffer or FIFO. When using a software flow control the Xon/Xoff characters cannot be used for data transfer. In the event that the receive buffer is overfilling and flow control needs to be executed, the SC16C650A automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem ...
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... Philips Semiconductors 6.7 Programmable baud rate generator The SC16C650A supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460 ...
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... Philips Semiconductors Table 5: Using 1.8432 MHz crystal Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 XTAL1 XTAL2 Fig 6. Baud rate generator circuitry. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Baud rates using 1 ...
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... Philips Semiconductors 6.8 DMA operation The SC16C650A FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins ...
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... Philips Semiconductors In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Status Register (MSR[0-3]) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER. ...
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... Philips Semiconductors 7. Register descriptions Table 8 The assigned bit functions are more fully defined in Table 8: SC16C650A internal registers Shaded bits are only accessible when EFR[4] is set. [ Register Default [2] General Register Set RHR THR IER ...
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... Philips Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty fl ...
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... Philips Semiconductors Table 9: Bit 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level ...
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... Philips Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode Mode 0 (FCR bit 3 = 0): receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will logic 0 whenever an empty transmit space is available in the Transmit Holding Register (THR) ...
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... Philips Semiconductors Table 10: Bit Table 11: FCR[ Table 12: FCR[ 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C650A is in FIFO mode (FCR[0] = logic 1 ...
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... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C650A provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Philips Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15: Bit 1-0 [1] When LCR[ the general register set cannot be accessed until LCR[ ...
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... Philips Semiconductors Table 16: LCR[ Table 17: LCR[ Table 18: LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19: Bit 7 6 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder ...
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... Philips Semiconductors Table 19: Bit 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Modem Control Register bits description Symbol Description MCR[5] INT typ select. Logic 0 = Enable active or 3-State interrupt output mode (normal default condition). Logic Enable open source interrupt output mode. Provides shared interrupts in the STD mode by producing a wire-OR output driver capability for interrupts ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C650A and the CPU. Table 20: Bit 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Line Status Register bits description ...
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... Philips Semiconductors Table 20: Bit 0 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C650A is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...
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... Philips Semiconductors Table 21: Bit 1 0 [1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C650A provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. ...
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... Philips Semiconductors Table 22: Bit 5 4 3-0 Table 23: Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Enhanced Feature Register bits description ...
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... Philips Semiconductors 7.11 SC16C650A external reset conditions Table 24: Register IER ISR LCR MCR LSR MSR FCR EFR Table 25: Output TX RTS DTR RXRDY TXRDY INT 8. Limiting values Table 26: In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg ...
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... Philips Semiconductors 9. Static characteristics Table 27: DC electrical characteristics + 2 5.0 V 10%, unless otherwise specified. amb CC Symbol Parameter V LOW-level clock input voltage IL(CK) V HIGH-level clock input voltage IH(CK) V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage OL [1] ...
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... Philips Semiconductors 10. Dynamic characteristics Table 28: AC electrical characteristics + 2 10%, unless otherwise specified. amb CC Symbol Parameter clock pulse duration oscillator/clock frequency 3w t address strobe width 4w t address set-up time 5s t address hold time 5h t chip select set-up time to AS ...
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... Philips Semiconductors Table 28: AC electrical characteristics + 2 10%, unless otherwise specified. amb CC Symbol Parameter t delay from start to reset TXRDY 28d t Reset pulse width RESET N baud rate divisor [1] Applies to external clock, crystal oscillator max 24 MHz. [2] Applicable only when AS is tied LOW. ...
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... Philips Semiconductors A0– CS2 CS1–CS0 t 13d t 14d IOW, IOW D0–D7 Fig 9. General write timing when using AS signal. A0–A2 ADDRESS IOR D0–D7 Fig 10. General read timing when AS is tied to GND. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder ...
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... Philips Semiconductors A0–A2 ADDRESS IOW D0–D7 Fig 11. General write timing when AS is tied to GND. IOW ACTIVE RTS CHANGE OF STATE DTR DCD CTS DSR INT IOR RI Fig 12. Modem input/output timing. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder ...
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... Philips Semiconductors t 2w EXTERNAL CLOCK Fig 13. External clock timing. START BIT RX INT IOR Fig 14. Receive timing. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 04 — ...
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... Philips Semiconductors START BIT RX RXRDY IOR Fig 15. Receive ready timing in non-FIFO mode. START BIT RX RXRDY IOR Fig 16. Receive ready timing in FIFO mode. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder DATA BITS (5– DATA BITS (5–8) ...
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... Philips Semiconductors START BIT TX INT t 23d ACTIVE IOW Fig 17. Transmit timing. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 04 — ...
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... Philips Semiconductors Fig 18. Transmit ready timing in non-FIFO mode. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder Rev. 04 — 20 June 2003 SC16C650A © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Philips Semiconductors START BIT TX ACTIVE IOW D0–D7 BYTE #16 t 27d TXRDY Fig 19. Transmit ready timing in FIFO mode (DMA mode ‘1’). 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS ...
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... Philips Semiconductors TX DATA IRTXA–IRTXD Fig 20. Infrared transmit timing. IRRXA–IRRXD RX DATA Fig 21. Infrared receive timing. 9397 750 11622 Product data UART with 32-byte FIFO and IrDA encoder/decoder UART FRAME DATA BITS BIT TIME RX BIT TIME Rev. 04 — 20 June 2003 ...
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... Philips Semiconductors 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.81 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.66 0.180 0.021 0.032 inches 0.02 0.01 0.12 0.165 0.026 ...
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... Philips Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 1.6 mm 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors DIP40: plastic dual in-line package; 40 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.70 mm 4.7 0.51 4 1.14 0.067 inches 0.19 0.02 0.16 0.045 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... Philips Semiconductors 12. Soldering 12.1 Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board ...
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... Philips Semiconductors – for packages with a thickness – for packages with a thickness < 2.5 mm and a volume thick/large packages. • below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm Moisture sensitivity precautions, as indicated on packing, must be respected at all times ...
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... Surface mount [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26 ...
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... Philips Semiconductors 13. Revision history Table 30: Revision history Rev Date CPCN Description 04 20030620 - Product data (9397 750 11622). ECN 853-2378 30030 of 16 June 2003. Modifications: • Figure 5 “Crystal oscillator connection.” on page added connection with resistor. 03 20030313 - Product data (9397 750 11207). ECN 853-2378 29622 of 07 March 2003. ...
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... Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. ...
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... Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 Internal registers 6.2 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 Hardware flow control . . . . . . . . . . . . . . . . . . . 11 6.4 Software flow control . . . . . . . . . . . . . . . . . . . 11 6.5 Special feature software flow control . . . . . . . 12 6.6 Hardware/software and time-out interrupts ...