GAL16V8B-10LJ Lattice Semiconductor Corp., GAL16V8B-10LJ Datasheet

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GAL16V8B-10LJ

Manufacturer Part Number
GAL16V8B-10LJ
Description
High performance E2CMOS PLD generic array logic, 10ns, low power
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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• HIGH PERFORMANCE E
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
• ACTIVE PULL-UPS ON ALL PINS
• E
• EIGHT OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL16V8C, at 5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL16V8 are the PAL architectures
listed in the table of the macrocell description section. GAL16V8
devices are capable of emulating any of these PAL architectures
with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor guarantees 100% field programmability
and functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are guaranteed.
Copyright © 1996 Lattice Semiconductor Corporation. E 2 CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered
trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD,
ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice
Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.lattice.com
DESCRIPTION
FEATURES
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
tion/Fuse Map/Parametric Compatibility
2
) floating gate technology to provide the highest speed
®
Advanced CMOS Technology
2
CMOS
®
Devices with Full Func-
®
TECHNOLOGY
3-65
I/CLK
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
I
I
I
I
I
I
I
I
I
I
I
I
I
4
6
8
I
9
I
GAL16V8
GND
Top View
2
I
PLCC
Specifications GAL16V8
I/CLK
I/OE
11
High Performance E
I/O/Q
Vcc
20
I/O/Q
I/O/Q
13
18
16
14
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
GAL16V8
I/CLK
8
8
8
8
8
8
8
8
GND
CLK
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
I
1996 Data Book
5
1
10
2
1996 Data Book
CMOS PLD
OE
16V8
GAL
DIP
20
11
15
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE

Related parts for GAL16V8B-10LJ

GAL16V8B-10LJ Summary of contents

Page 1

... Copyright © 1996 Lattice Semiconductor Corporation CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation ...

Page 2

... PART NUMBER DESCRIPTION GAL16V8C Device Name GAL16V8B Speed (ns Low Power Q = Quarter Power ...

Page 3

OUTPUT LOGIC MACROCELL (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is ac- complished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration ...

Page 4

REGISTERED MODE In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register ...

Page 5

REGISTERED MODE LOGIC DIAGRAM 1 0 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 DIP & PLCC Package Pinouts 2128 28 PTD 4 8 ...

Page 6

COMPLEX MODE In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell six I/O's ...

Page 7

COMPLEX MODE LOGIC DIAGRAM 1 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 DIP & PLCC Package Pinouts 2128 ...

Page 8

SIMPLE MODE In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of generic output ...

Page 9

SIMPLE MODE LOGIC DIAGRAM 1 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 DIP & PLCC Package Pinouts 2128 ...

Page 10

ABSOLUTE MAXIMUM RATINGS Supply voltage V ....................................... –0.5 to +7V CC Input voltage applied .......................... –2 Off-state output voltage applied .......... –2 Storage Temperature ................................. –65 to 150 C Ambient Temperature with Power Applied ........................................ –55 ...

Page 11

AC SWITCHING CHARACTERISTICS TEST DESCRIPTION PARAMETER COND Input or I/O to Comb. Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, Input or ...

Page 12

... MAX. Vin = MAX. Vin = 0.5V CC OUT = 0. 3. 15MHz Outputs Open = 0. 3. 15MHz Outputs Open = 3-76 Specifications GAL16V8B Specifications GAL16V8 ) ............................... ...........................– MIN. TYP. — Vss – 0.5 2.0 — — — — — — — ...

Page 13

... MAXIMUM 3-77 Specifications GAL16V8B Specifications GAL16V8 COM / IND IND COM / IND -10 -15 -20 -25 MAX. MIN. MAX. MIN. MAX. MIN — — — — — — ...

Page 14

SWITCHING WAVEFORMS INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width INPUT or I/O FEEDBACK CLK VALID ...

Page 15

... Input Pulse Levels Input Rise and GAL16V8B Fall Times GAL16V8C Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GAL16V8B Output Load Conditions (see figure) Test Condition 200 B Active High Active Low 200 ...

Page 16

ELECTRONIC SIGNATURE An electronic signature is provided in every GAL16V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision num- bers, or inventory control. The signature data is ...

Page 17

POWER-UP RESET INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL16V8 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q t outputs set low after a specified time ( ...

Page 18

GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 ...

Page 19

GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 Supply Voltage (V) Delta ...

Page 20

GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 ...

Page 21

GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol 1 0.75 0.5 0.25 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 Supply Voltage (V) ...

Page 22

GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 ...

Page 23

GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage ...

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