MBM29F800TA-90PFTN Fujitsu, MBM29F800TA-90PFTN Datasheet

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MBM29F800TA-90PFTN

Manufacturer Part Number
MBM29F800TA-90PFTN
Description
MBM29F800TA-90PFTN8M (1M X 8/512K X 16) BIT
Manufacturer
Fujitsu
Datasheet

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FUJITSU SEMICONDUCTOR
查询29F800供应商
FLASH MEMORY
CMOS
8M (1M
MBM29F800TA
Embedded Erase
FEATURES
• Single 5.0 V read, write, and erase
• Compatible with JEDEC-standard commands
• Compatible with JEDEC-standard world-wide pinouts
• Minimum 100,000 write/erase cycles
• High performance
• Sector erase architecture
• Boot Code Sector Architecture
• Embedded Erase
• Embedded Program
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
• Low Vcc write inhibit
• Erase Suspend/Resume
• Hardware RESET pin
• Sector protection
• Temporary sector unprotection
DATA SHEET
Minimizes system level power requirements
Uses same software commands as E
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
55 ns maximum access time
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
T = Top sector
B = Bottom sector
Automatically pre-programs and erases the chip or any sector
Automatically writes and verifies data at specified address
Hardware method for detection of program or erase cycle completion
Suspends the erase operation to allow a read data in another sector within the same device
Resets internal state machine to the read mode
Hardware method disables any combination of sectors from write or erase operations
Temporary sector unprotection via the RESET pin.
TM
and Embedded Program
TM
Algorithms
TM
Algorithms
3.2 V
TM
8/512K
-55/-70/-90
are trademarks of Advanced Micro Devices, Inc.
2
PROMs
/MBM29F800BA
16) BIT
DS05-20841-4E
-55/-70/-90

Related parts for MBM29F800TA-90PFTN

MBM29F800TA-90PFTN Summary of contents

Page 1

... FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 8M (1M MBM29F800TA FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN – ...

Page 2

... MBM29F800TA -55/-70/-90 PACKAGE 48-pin TSOP(I) Marking Side (FPT-48P-M19) 2 /MBM29F800BA Marking Side (FPT-48P-M20) -55/-70/-90 44-pin SOP Marking Side (FPT-44P-M16) ...

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... MBM29F800TA GENERAL DESCRIPTION The MBM29F800TA/ 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The MBM29F800TA/BA is offered in a 48-pin TSOP(I) and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5 required for write or erase operations ...

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... MBM29F800TA Sector Architecture 4 /MBM29F800BA ( 8) ( 16) FFFFFH 7FFFFH 64K byte FBFFFH 7DFFFH 64K byte F9FFFH 7CFFFH ...

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... Buffer State Control BYTE RESET Command Register CE OE Low V Detector /MBM29F800BA -55/-70/-90 MBM29F800TA/MBM29F800BA -55 — — - RY/BY Erase Voltage Generator Program Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer for Address Program/Erase Latch ...

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... FPT-48P-M19 A 24 (Marking Side RY/BY 15 N.C. 14 N.C. 13 MBM29F800TA/MBM29F800BA RESET 12 Reverse Pinout WE 11 N. FPT-48P-M20 6 /MBM29F800BA TSOP(I) A ...

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... MBM29F800TA LOGIC SYMBOL RY/BY RESET BYTE /MBM29F800BA -55/-70/-90 Table 1 MBM29F800TA/BA Pin Configuration Pin Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable OE Write Enable WE Ready/Busy Output RY/BY Hardware Reset Pin/ ...

Page 8

... Read (3) Standby Output Disable Write Enable Sector Protection (2) Verify Sector Protection (2) Temporary Sector Unprotection Reset (Hardware)/Standby Table 3 MBM29F800TA/BA User Bus Operation (BYTE = V Operation Auto-Select Manufacturer Code (1) Auto-Select Device Code (1) Read (3) Standby Output Disable Write (Program/Erase) Enable Sector Protection (2) Verify Sector Protection (2) ...

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... MBM29F800TA ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29F800 T A -55 DEVICE NUMBER/DESCRIPTION MBM29F800 8Mega-bit (1M 5.0 V-only Read, Write, and Erase /MBM29F800BA -55/-70/-90 PFTN PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout ...

Page 10

... FUNCTIONAL DESCRIPTION Read Mode The MBM29F800TA/BA has two control functions which must be satisfied in order to obtain data at the outputs the power control and should be used for a device selection the output control and should be used to gate data to the output pins if a device is selected. ...

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... Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The MBM29F800TA/BA features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. ...

Page 12

... Autoselect codes. Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the MBM29F800TA/BA device in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. ...

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... SA9 1 0 SA10 1 0 SA11 1 0 SA12 1 1 SA13 1 1 SA14 1 1 SA15 1 1 SA16 1 1 SA17 1 1 SA18 1 1 /MBM29F800BA -55/-70/-90 Sector Address Tables (MBM29F800TA ...

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... MBM29F800TA Table 6 Sector Address SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 1 SA8 0 1 SA9 0 1 SA10 0 1 SA11 1 0 SA12 1 0 SA13 1 0 SA14 1 0 SA15 1 1 SA16 1 1 SA17 ...

Page 15

... The read or eset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. /MBM29F800BA -55/-70/-90 MBM29F800TA/BA Command Definitions Second Fourth Bus Third Bus Bus ...

Page 16

... The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read cycle from address XX01H for 16 (XX02H for 8) returns the device code (MBM29F800TA = D6H and MBM29F800BA = 58H for 8 mode; MBM29F800TA = 22D6H and MBM29F800BA = 2258H for 16 mode). ...

Page 17

... MBM29F800TA Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations ...

Page 18

... MBM29F800TA When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin and the DQ bit will be at logic “1”, and DQ ...

Page 19

... DQ 6 Toggle Bit I The MBM29F800TA/BA also feature the “Toggle Bit I” method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ toggling between one and zero ...

Page 20

... MBM29F800TA The DQ failure condition may also appear if a user tries to program a non blank location without erasing. In this 5 case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ bit and bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly 5 used ...

Page 21

... RY/BY Ready/Busy The MBM29F800TA/BA provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation ...

Page 22

... MBM29F800TA Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one must be a logical zero while logical one. Power-Up Write Inhibit Power-up of the device with The internal state machine is automatically reset to the read mode on power-up ...

Page 23

... Supply Voltages CC MBM29F800TA/BA-55 ..............................................................................+4. +5.25 V MBM29F800TA/BA-70/-90 ........................................................................+4. +5.50 V Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges ...

Page 24

... MBM29F800TA MAXIMUM OVERSHOOT +0.8 V –0.5 V –2.0 V Figure +2.0 V Figure 2 +14.0 V +13 +0 Note: This waveform is applied for A Figure 3 24 /MBM29F800BA -55/-70/- Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform OE, and RESET. 9 Maximum Positive Overshoot Waveform 2 ...

Page 25

... MBM29F800TA DC CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current OE, RESET Inputs Leakage 9 I LIT Current I V Active Current (Note 1) CC1 Active Current (Note 2) CC2 Current (Standby) CC3 Current (Standby, Reset) CC4 CC V Input Low Level ...

Page 26

... Input rise and fall times Input pulse levels: 0 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V Device Under Test Notes including jig capacitance (MBM29F800TA/BA-55 100 pF including jig capacitance (MBM29F800TA/BA-70/-90 /MBM29F800BA -55/-70/-90 Description Test Setup — ...

Page 27

... MBM29F800TA • Write/Erase/Program Operations Parameter Symbols JEDEC Standard t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data Hold Time WHDX DH — t Output Enable Setup Time OES Output — ...

Page 28

... FHQV — t Program/Erase Valid to RY/BY Delay BUSY — t Delay Time from Embedded Output Enable EOE Notes: 1. This does not include the preprogramming time. 2. These timing is for Sector Protection operation. 28 /MBM29F800BA -55/-70/-90 Description -55/-70/-90 MBM29F800TA/BA -55 -70 -90 Min. 500 500 500 Min Max Min. ...

Page 29

... MBM29F800TA SWITCHING WAVEFORMS • Key to Switching Waveforms WAVEFORM Addresses OEH WE High-Z Outputs Figure 5 /MBM29F800BA -55/-70/-90 INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from from May Will Be Change Changing from from “H” or “L” ...

Page 30

... MBM29F800TA 3rd Bus Cycle Addresses 555H A0H Data t DS 5.0 V Notes address of the memory location to be programmed data to be programmed at byte address the output of the complement of the data written to the device the output of the data written to the device. ...

Page 31

... MBM29F800TA 3rd Bus Cycle Addresses 555H GHEL CPH A0H Data t DS 5.0 V Notes address of the memory location to be programmed data to be programmed at byte address the output of the complement of the data written to the device. ...

Page 32

... MBM29F800TA Addresses CE t GHWL Data VCS Notes the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase. 2. These waveforms are for the Figure 8 32 /MBM29F800BA -55/-70/- 555H 2AAH 555H ...

Page 33

... MBM29F800TA OEH WE DQ Data 7 Data Valid Data (The device has completed the Embedded operation). 7 Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations CE t OEH WE t OES OE Data Toggle stops toggling (The device has completed the Embedded operation). ...

Page 34

... MBM29F800TA CE WE RY/BY Figure 11 RY/BY Timing Diagram during Program/Erase Operations WE RESET RY/BY 34 /MBM29F800BA -55/-70/-90 The rising edge of the last WE signal READY Figure 12 RESET/RY/BY Timing Diagram -55/-70/-90 Entire programming or erase operations t BUSY t RB ...

Page 35

... MBM29F800TA CE BYTE ELFH Figure 1 Timing Diagram for Word Mode Configuration CE BYTE t ELFL Figure 2 Timing Diagram for Byte Mode Configuration BYTE Figure 3 BYTE Timing Diagram for Write Operations /MBM29F800BA -55/-70/-90 Data Output Data Output ...

Page 36

... MBM29F800TA SAX VLHT VLHT WE CE Data t VLHT V CC SAX = Sector Address for initial sector SAY = Sector Address for next sector Note byte mode. ...

Page 37

... MBM29F800TA VIDR t VCS RESET CE WE RY/BY Figure 1 Temporary Sector Unprotection Timing Diagram Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend Read Toggle DQ and with OE Note read from the erase-suspended sector. 2 /MBM29F800BA -55/-70/-90 t Program or Erase Command Sequence ...

Page 38

... MBM29F800TA EMBEDDED ALGORITHMS Increment Address * : The sequence is applied for The addresses differ from 38 /MBM29F800BA -55/-70/-90 Start Write Program Command Sequence (See Below) Data Polling Device No Last Address ? Yes Programming Completed Program Command Sequence* (Address/Command): 555H/AAH 2AAH/55H 555H/A0H Program Address/Program Data 16 mode. 8 mode. ...

Page 39

... MBM29F800TA EMBEDDED ALGORITHMS Chip Erase Command Sequence* (Address/Command): 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H * : The sequence is applied for The addresses differ from 8 mode. Figure 3 /MBM29F800BA -55/-70/-90 Start Write Erase Command Sequece (See Below) Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Sector/Multiple Sector* ...

Page 40

... MBM29F800TA Note rechecked even /MBM29F800BA -55/-70/-90 Start Read Byte ( Addr Yes DQ = Data Yes Read Byte ( Addr Yes DQ = Data Pass Fail = “1” because DQ may change simultaneously with Figure 4 Data Polling Algorithm ...

Page 41

... MBM29F800TA No Note rechecked even changing to “1”. 5 Figure 5 /MBM29F800BA -55/-70/-90 Start Read Byte ( Addr. = “H” or “L” Toggle 6 ? Yes Yes Read Byte ( Addr. = “H” or “L” Toggle 6 ? Yes Fail Pass = “ ...

Page 42

... MBM29F800TA Increment PLSCNT PLSCNT = 25? Remove V Write Reset Command Device Failed * : byte mode /MBM29F800BA -55/-70/-90 Start Setup Sector Addr 16, PLSCNT = Activate WE Pulse Time out 100 should remain V 9 Read from Sector (Addr ...

Page 43

... MBM29F800TA Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 7 Temporary Sector Unprotection Algorithm /MBM29F800BA -55/-70/-90 Start RESET = V ID (Note 1) Perform Erase or Program Operations RESET = V IH Temporary Sector Unprotection Completed (Note 2) -55/-70/-90 43 ...

Page 44

... MBM29F800TA ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Erase/Program Cycle TSOP PIN CAPACITANCE Parameter Parameter Description Symbol C Input Capacitance IN C Output Capacitance OUT C Control Pin Capacitance IN2 Note: Test conditions T = 25° 1.0 MHz ...

Page 45

... MBM29F800TA PACKAGE DIMENSIONS 48-pin plastic TSOP(I) (FPT-48P-M19) LEAD No. 1 INDEX 24 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) 0.10(.004) 19.00±0.20 (.748±.008) 1996 FUJITSU LIMITED F48029S-2C-2 C /MBM29F800BA -55/-70/-90 *: Resin protrusion. (Each side: 0.15(.006) Max) 48 Details of "A" part "A" 0.15(.006) ...

Page 46

... MBM29F800TA 48-pin plastic TSOP(I) (FPT-48P-M20) LEAD No. 1 INDEX 24 19.00±0.20 (.748±.008) 0.10(.004) 18.40±0.20 * (.724±.008) 20.00±0.20 (.787±.008) 1996 FUJITSU LIMITED F48030S-2C /MBM29F800BA -55/-70/-90 *: Resin protrusion. (Each side: 0.15(.006) Max) 48 Details of "A" part "A" 25 0.50±0.10 (.020±.004) 0.15± ...

Page 47

... MBM29F800TA (Continued) 44-pin plastic SOP (FPT-44P-M16) 28.45 44 INDEX LEAD No. 1 1.27(.050)TYP 0.10(.004) 26.67(1.050)REF 1998 FUJITSU LIMITED F44023S-4C-4 C /MBM29F800BA -55/-70/-90 +0.25 +.010 1.120 –0.20 –.008 23 13.00±0.10 16.00±0.20 (.512±.004) (.630±.008) 22 +0.10 +0.10 0.40 0.20 –0.05 –0.15 Ø0.13(.005) M +.004 (Stand off) .016 –.002 -55/-70/-90 2.35±0.15(.093±.006) (Mounting height) 0.80± ...

Page 48

... MBM29F800TA FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division ...

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