KM44C4103CK-6 Samsung, KM44C4103CK-6 Datasheet

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KM44C4103CK-6

Manufacturer Part Number
KM44C4103CK-6
Description
4M x 4Bit CMOS quad CAS DRAM with fast page mode, 5V, 60ns
Manufacturer
Samsung
Datasheet

Specifications of KM44C4103CK-6

Case
SOJ

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KM44C4003C, KM44C4103C
This is a family of 4,194,304 x 4 bit Quad CAS with Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access
of memory cells within the same row. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low
power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only
refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for
seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
• Part Identification
• Refresh Cycles
• Performance Range
• Active Power Dissipation
Speed
C4003C
C4103C
- KM44C4003C/C-L (5V, 4K Ref.)
- KM44C4103C/C-L (5V, 2K Ref.)
Speed
-5
-6
Part
NO.
-5
-6
50ns
60ns
t
RAC
Refresh
cycle
4K
2K
13ns
15ns
t
CAC
495
440
4K
4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode
Refresh Cycle
110ns
90ns
Normal
t
64ms
32ms
RC
Refresh period
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
35ns
40ns
t
PC
605
550
2K
Unit : mW
128ms
L-ver
Remark
5V/3.3V
5V/3.3V
DESCRIPTION
(A0 - A10)
(A0 - A10)
CAS0 - 3
A0-A11
A0 - A9
RAS
Note)
W
*1
*1
*1
: 2K Refresh
FUNCTIONAL BLOCK DIAGRAM
• Fast Page Mode operation
• Four seperate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast paralleltest mode capability
• TTL compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V 10% power supply
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
Memory Array
4,194,304 x 4
Row Decoder
Cells
CMOS DRAM
Vcc
Vss
Data out
Data in
Buffer
Buffer
OE
DQ0
DQ3
to

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KM44C4103CK-6 Summary of contents

Page 1

... Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode. This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsung s advanced CMOS process to realize high band- width, low power consumption and high reliability. ...

Page 2

KM44C4003C, KM44C4103C V CC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 *A11 is N.C for KM44C4103C(5V, 2K Ref. product 300mil 28 SOJ S : 300mil 28 TSOP II PIN CONFIGURATION (Top ...

Page 3

KM44C4003C, KM44C4103C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" ...

Page 4

KM44C4003C, KM44C4103C DC AND OPERATING CHARACTERISTICS Symbol Power I Don t care CC1 Normal I Don t care CC2 L I Don t care CC3 I Don t care CC4 Normal I Don t care CC5 L I Don t ...

Page 5

KM44C4003C, KM44C4103C CAPACITANCE (T = Parameter Input capacitance [A0 ~ A11] Input capacitance [RAS, CASx, W, OE] Output capacitance [DQ0 - DQ3] AC CHARACTERISTICS ( Test condition : V =5.0V 10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V CC Parameter ...

Page 6

KM44C4003C, KM44C4103C AC CHARACTERISTICS (Continued) Parameter Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to ...

Page 7

KM44C4003C, KM44C4103C TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time ...

Page 8

KM44C4003C, KM44C4103C NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles 1. before proper device operation is achieved (min) and V (max) are reference levels for measuring ...

Page 9

KM44C4003C, KM44C4103C READ CYCLE NOTE : D = OPEN OUT RAS CAS0 CAS1 CAS2 ...

Page 10

KM44C4003C, KM44C4103C WRITE CYCLE ( EARLY WRITE ) RAS CAS0 CAS1 CAS2 CAS3 ...

Page 11

KM44C4003C, KM44C4103C WRITE CYCLE ( OE CONTROLLED WRITE ) RAS CAS0 CAS1 CAS2 ...

Page 12

KM44C4003C, KM44C4103C READ - MODIFY - WRTIE CYCLE RAS CAS0 CAS1 CAS2 CAS3 ...

Page 13

KM44C4003C, KM44C4103C FAST PAGE READ CYCLE NOTE : D = OPEN OUT RAS CRP CAS0 CAS1 CAS2 V ...

Page 14

KM44C4003C, KM44C4103C FAST PAGE WRITE CYCLE ( EARLY WRITE ) RAS CRP CAS0 CAS1 CAS2 ...

Page 15

KM44C4003C, KM44C4103C FAST PAGE READ - MODIFY - WRITE CYCLE RAS CAS0 CAS1 CAS2 ...

Page 16

KM44C4003C, KM44C4103C RAS - ONLY REFRESH CYCLE NOTE : W, OE Don t care OPEN OUT RAS CRP CASX ASR V ...

Page 17

KM44C4003C, KM44C4103C HIDDEN REFRESH CYCLE ( READ ) RAS CASX ...

Page 18

KM44C4003C, KM44C4103C HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CASX ...

Page 19

KM44C4003C, KM44C4103C CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE Don t care RAS CASX DQ0 ~ DQ3 ...

Page 20

KM44C4003C, KM44C4103C PACKAGE DIMENSION 28 SOJ 300mil #28 #1 0.0375 (0.95) 28 TSOP(II) 300mil 0.037 (0.95) 0.741 (18.82) MAX 0.720 (18.30) 0.730 (18.54) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.741 (18.81) MAX 0.721 (18.31) 0.047 (1.20) ...

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