KM416C4104CS-6 Samsung, KM416C4104CS-6 Datasheet

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KM416C4104CS-6

Manufacturer Part Number
KM416C4104CS-6
Description
4M x 16Bit CMOS dynamic RAM with extended data out, 5V, 4K refresh, 60ns
Manufacturer
Samsung
Datasheet
KM416C4004C, KM416C4104C
• Performance Range
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-5 or -6) are optional features of this family.
All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 EDO Mode DRAM family
is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
• Active Power Dissipation
• Refresh Cycles
* Access mode & RAS only refresh mode
KM416C4004C*
KM416C4104C
Speed
CAS-before-RAS & Hidden refresh mode
- KM416C4004C(5.0V, 8K Ref.)
- KM416C4104C(5.0V, 4K Ref.)
: 8K cycle/64ms
: 4K cycle/64ms
-5
-6
Speed
-5
-6
Part
NO.
50ns
60ns
t
RAC
Refresh
cycle
13ns
15ns
t
4M x 16bit CMOS Dynamic RAM with Extended Data Out
495
440
8K
4K
CAC
8K
104ns
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
84ns
t
RC
Refresh time
Normal
64ms
660
605
Unit : mW
4K
20ns
25ns
t
HPC
DESCRIPTION
(A0~A11)*1
(A0~A9)*1
UCAS
LCAS
A0~A12
RAS
A0~A8
W
FUNCTIONAL BLOCK DIAGRAM
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) package
• +5.0V 10% power supply
Note) *1 : 4K Refresh
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
4,194,304 x 16
Memory Array
Row Decoder
Cells
CMOS DRAM
Vcc
Vss
Data out
Data out
Data in
Data in
Lower
Buffer
Lower
Buffer
Upper
Buffer
Upper
Buffer
DQ0
DQ7
OE
DQ15
DQ8
to
to

Related parts for KM416C4104CS-6

KM416C4104CS-6 Summary of contents

Page 1

... Refresh cycle(4K Ref Ref.), access time (-5 or -6) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 EDO Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES • ...

Page 2

KM416C4004C, KM416C4104C PIN CONFIGURATION (Top Views) • KM416C40(1)04CS DQ0 DQ15 3 48 DQ1 DQ14 4 47 DQ2 DQ13 5 46 DQ3 DQ12 DQ4 DQ11 ...

Page 3

KM416C4004C, KM416C4104C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM ...

Page 4

KM416C4004C, KM416C4104C DC AND OPERATING CHARACTERISTICS Symbol Power Speed I Don t care CC1 I Normal Don t care CC2 I Don t care CC3 I Don t care CC4 I Normal Don t care CC5 I Don t care ...

Page 5

KM416C4004C, KM416C4104C CAPACITANCE (T = Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] AC CHARACTERISTICS ( Test condition : V =5.0V 10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.0/0.8V ...

Page 6

KM416C4004C, KM416C4104C AC CHARACTERISTICS (Continued) Parameter Data hold time Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time CAS to W delay time RAS to W delay time Column address W delay time CAS set-up time (CAS ...

Page 7

KM416C4004C, KM416C4104C TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time ...

Page 8

KM416C4004C, KM416C4104C NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles 1. before proper device operation is achieved. V (min) and V (max) are reference levels for measuring timing ...

Page 9

KM416C4004C, KM416C4104C t is specified from W falling edge to the earlier CAS rising edge. 16. CWL t 17. is referenced to the earlier CAS falling edge before RAS transition low. CSR 18 referenced to the later CAS ...

Page 10

KM416C4004C, KM416C4104C WORD READ CYCLE RAS CRP UCAS CRP LCAS ASR ROW A ADDRESS V - ...

Page 11

KM416C4004C, KM416C4104C LOWER BYTE READ CYCLE NOTE : D = OPEN RAS CRP UCAS CRP LCAS ASR V ...

Page 12

KM416C4004C, KM416C4104C UPPER BYTE READ CYCLE NOTE : D = OPEN RAS CRP UCAS CRP LCAS ASR V ...

Page 13

KM416C4004C, KM416C4104C WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS ...

Page 14

KM416C4004C, KM416C4104C LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V - ...

Page 15

KM416C4004C, KM416C4104C UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V - ...

Page 16

KM416C4004C, KM416C4104C WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V - ...

Page 17

KM416C4004C, KM416C4104C LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V ...

Page 18

KM416C4004C, KM416C4104C UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS V ...

Page 19

KM416C4004C, KM416C4104C WORD READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS ASR ROW ...

Page 20

KM416C4004C, KM416C4104C LOWER-BYTE READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS ASR ROW ...

Page 21

KM416C4004C, KM416C4104C UPPER-BYTE READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP LCAS ASR ROW ...

Page 22

KM416C4004C, KM416C4104C HYPER PAGE MODE WORD READ CYCLE RAS CRP UCAS CRP LCAS RAD t t ASR RAH V ...

Page 23

KM416C4004C, KM416C4104C HYPER PAGE MODE LOWER BYTE READ CYCLE RAS CRP UCAS LCAS RAD t t ASR RAH V - ...

Page 24

KM416C4004C, KM416C4104C HYPER PAGE MODE UPPER BYTE READ CYCLE RAS CRP UCAS CRP LCAS RAD t t ASR RAH ...

Page 25

KM416C4004C, KM416C4104C HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS ...

Page 26

KM416C4004C, KM416C4104C HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP ...

Page 27

KM416C4004C, KM416C4104C HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP ...

Page 28

KM416C4004C, KM416C4104C HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE RAS CRP t RCD UCAS CRP t RCD LCAS V - ...

Page 29

KM416C4004C, KM416C4104C HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE RAS CRP UCAS CRP t RCD LCAS ...

Page 30

KM416C4004C, KM416C4104C HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE RAS CRP t RCD UCAS CRP LCAS ...

Page 31

KM416C4004C, KM416C4104C HYPER PAGE READ AND WRITE MIXED CYCLE RAS UCAS t RCD LCAS t RAD RAH t t ASR ASC ...

Page 32

KM416C4004C, KM416C4104C RAS - ONLY REFRESH CYCLE NOTE : Don t care OPEN OUT RAS CRP UCAS CRP ...

Page 33

KM416C4004C, KM416C4104C HIDDEN REFRESH CYCLE ( READ ) RAS CRP UCAS CRP LCAS ASR ROW A ...

Page 34

KM416C4004C, KM416C4104C HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CRP UCAS CRP LCAS ...

Page 35

KM416C4004C, KM416C4104C CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : Don t care RAS RPC UCAS ...

Page 36

KM416C4004C, KM416C4104C PACKAGE DIMENSION 50 TSOP(II) 400mil 0.841 (21.35) 0.821 (20.85) 0.829 (21.05) 0.034 (0.875) MAX 0.047 (1.20) MAX 0.0315 (0.80) 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) CMOS DRAM Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.010 (0.25) ...

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