AD28MSP01KR Analog Devices, AD28MSP01KR Datasheet
AD28MSP01KR
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AD28MSP01KR Summary of contents
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... DSP, freeing the processor for other voice or data communications tasks. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use ...
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AD28msp01 ANALOG INPUT SIGMA-DELTA AMP MODULATOR 500k VOLTAGE REFERENCE V OUT+ ANALOG SMOOTHING FILTER V OUT– OUTPUT DIFF. AMP TSYNC CLOCK GENERATION t t CONV BAUD Name Type Description Analog Interface V I Analog input to ...
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PIN DESCRIPTIONS (Continued) Name Type Description TCONV O Transmit conversion clock. This clock indicates when the ADC has finished a sampling cycle. The frequency of TCONV is programmed by setting the sample rate field in Control Register 0. The programmed ...
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AD28msp01 The output of the ADC is transferred to the AD28msp01’s se- rial port (SPORT) for transmission to the host DSP processor. D/A CONVERSION The D/A conversion circuitry of the AD28msp01 consists of a sigma-delta digital-to-analog converter (DAC) and a ...
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ADSP-2101 program initializes the AD28msp01} {and executes a loopback, or talk-through, routine.} . MODULE/RAM/BOOT = 0 MSP01; . VAR/DM/CIRC rec[2]; . VAR/DM/CIRC trans[2]; rset: JUMP start; RTI; RTI; RTI; irq2v: RTI; RTI; RTI; RTI; sprt0t: AX0 = 0x25; DM(0x3ff3) ...
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AD28msp01 AX0 = DM(I2, M1); AY0 = AX1 – AY0 JUMP goodstuff; RTI; goodstuff; MODIFY (I3, M1); DM(I3, M0) = AX0; MX1 = 0x06a7; DM(0x3ff3) = AR; TX0 = MX1; RTI; .ENDMOD; ...
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Since the resample phase is locked to RCONV, it can be ad- vanced or slipped by writing a signed-magnitude value to the Receive Phase Adjust Register (Control Register 2). The phase advance or slip is equal to the master clock ...
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AD28msp01 If any low-pass filter is bypassed, the resampling interpolation filter should be disabled (in Control Register 0.) Control Register 2 address = 0x02 This register is used to: • Select the frequency of the Receive baud clock (RBAUD) • ...
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Control Register 4 address = 0x04 This register is the Receive Phase Adjust Register and it is used to: • Change the phase of the receive clocks (RBAUD, RBIT, RCONV – Phase advance 1 – Phase ...
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AD28msp01 Data Register 1 address = 0x07 Interpolation Filter Input Register (write-only): The 16-bit twos complement values written to this register are input to the resampling interpolation filter. Data Register 2 address = 0x08 ADC Output Register (read-only): The 16-bit ...
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V.32 TSYNC Mode In V.32 TSYNC Mode, shown in Figure 7, the AD28msp01’s transmit circuitry is synchronized to an external TSYNC signal. The AD28msp01 receive circuitry is sampled synchronous to the transmit circuitry, but the data can be resampled at ...
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AD28msp01 V.32 Internal Sync Mode In V.32 Internal Sync Mode, shown in Figure 8, the AD28msp01’s transmit clocks are generated internally. The receive circuitry operates synchronous to the transmit circuitry, but the data can be resampled at a different phase ...
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V.32 Loopback Mode In V.32 Loopback Mode, shown in Figure 9, the AD28msp01’s receive circuitry and transmit circuitry are locked together. RCONV is generated internally and can be phase adjusted with the Receive Phase Adjust Register (Control Register 4). RBIT, ...
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AD28msp01 Asynchronous Fallback TSYNC Mode The Asynchronous Fallback TSYNC Mode is shown in Figure 10. TCONV, TBIT and TBAUD are generated internally but phase locked to the external TSYNC input signal. RCONV, RBIT and RBAUD are generated internally and can ...
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A/D ANALOG IN TX CLOCKS RX CLOCKS PHASE ADJUST MCLK TX CLOCKS PHASE ADJUST ANALOG OUT D/A Figure 11. Asynchronous Fallback Mode Block Diagram Operating Mode Summary Table III summarizes the operating modes. Initial Phase Lock After Normal DPLL* ...
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... The V OUTP do not use either as a single-ended output. Figure 15 shows an example circuit which can he used to convert the differential output to a single-ended output. The circuit uses a differential- to-single-ended amplifier, the Analog Devices SSM2141 –16– 330pF V ...
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F GND SSM2141 SSM-214 OUT 1 4 GND A 0.1 F GND A –12V Figure 15. Example Circuit for Single-Ended Output Single Power Supply Operation Use of a single +5 V power supply is ...
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AD28msp01–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Symbol Parameter Supply Voltage Ambient Operating Temperature AMB Refer to Environmental Conditions for information on case temperature and thermal specifications. ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . ...
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DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage OL I High Level Input Current IH I Low Level Input Current IL I Low ...
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AD28msp01 TIMING PARAMETERS Parameter Clock Signals Timing Requirement: F MCLK Frequency MCK t MCLK Period MCK t MCLK Width Low MKL t MCLK Width High MKH Switching Characteristic: t SCLK Period SCK t SCLK Width Low SKL t SCLK Width ...
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Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high-impedance state. The output disable time ( the ...
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AD28msp01 DIGITAL TEST CONDITIONS DIGITAL INPUT DIGITAL OUTPUT Figure 20. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) GAIN Parameter ADC Absolute Gain ADC Gain Tracking Error DAC Absolute Gain DAC Gain Tracking Error FREQUENCY RESPONSE* ADC Passband Ripple ...
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NOISE AND DISTORTION Parameter ADC Signal-to-Noise Ratio ADC Total Harmonic Distortion DAC Signal-to-Noise Ratio DAC Total Harmonic Distortion ADC Idle Channel Noise DAC Idle Channel Noise 1 ADC Crosstalk 1 DAC Crosstalk 1 ADC Intermodulation Distortion 1 DAC Intermodulation Distortion ...
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AD28msp01 GND GND GND RESET TSYNC TCONV TBIT TBAUD PIN CONFIGURATIONS 28-Pin DIP and 28-Lead SOIC OUTP OUTN GND 6 A AD28msp01 ...
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PIN 1 0.200 (5.080) MAX SEATING PLANE REV. A 44-Lead Thin Quad Flat Pack GND A GND D GND D RESET NC TOP VIEW TSYNC (Pins Down) TCONV NC TBIT TBAUD ...
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AD28msp01 0.048 (1.21) 0.042 (1.07) 0.020 (0.50 0.0118 (0.30) 0.0040 (0.10) P-44A 44-Lead Plastic Leaded Chip Carrier (PLCC) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.048 (1.21) 0.042 (1.07) 0.042 (1.07 PIN 1 IDENTIFIER TOP ...
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... SEATING PLANE 0.004 (0.10) 0.006 (0.15) 0.002 (0.05) Part Number Temperature Range AD28msp01KP +70 C AD28msp01KN +70 C AD28msp01KR +70 C AD28msp01KST† +70 C NOTES *P = PLCC Plastic DIP Small Outline (SOIC TQFP. †In Development. REV. A ST-44 0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.549 (13.95) 0.063 (1.60) 0.397 (10.07) MAX 0 ...
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