MCM69F618CTQ12 Motorola, MCM69F618CTQ12 Datasheet

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MCM69F618CTQ12

Manufacturer Part Number
MCM69F618CTQ12
Description
64K x 18 bit flow-through burstRAM synchronous fast static RAM
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
64K x 18 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 64K
words of 18 bits each. This device integrates input registers, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). BiCMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability.
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
addresses can be generated internally by the MCM69F618C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
chronous write enable SW are provided to allow writes to either individual bytes
or to both bytes. The two bytes are designated as “a” and “b”. SBa controls DQa
and SBb controls DQb. Individual bytes are written if the selected byte writes SBx
are asserted with SW. Both bytes are written if either SGW is asserted or if all SBx
and SW are asserted.
from the memory array.
outputs are LVTTL compatible and 5 V tolerant.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.
REV 2
2/18/98
MOTOROLA FAST SRAM
Motorola, Inc. 1998
The MCM69F618C is a 1M–bit synchronous fast static RAM designed to pro-
Addresses (SA), data inputs (DQx), and all control signals except output
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
Write cycles are internally self–timed and initiated by the rising edge of the
Synchronous byte write (SBx), synchronous global write (SGW), and syn-
For read cycles, a flow–through SRAM allows output data to simply flow freely
The MCM69F618C operates from a 3.3 V power supply and all inputs and
MCM69F618C–8.5 = 8.5 ns Access / 12 ns Cycle
MCM69F618C–9 = 9 ns Access / 12 ns Cycle
MCM69F618C–10 = 10 ns Access / 15 ns Cycle
MCM69F618C–12= 12 ns Access / 16.6 ns Cycle
Single 3.3 V + 10%, – 5% Power Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
5 V Tolerant on all Pins (Inputs and I/Os)
100–Pin TQFP Package
MCM69F618C
Order this document
by MCM69F618C/D
CASE 983A–01
TQ PACKAGE
MCM69F618C
TQFP
1

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MCM69F618CTQ12 Summary of contents

Page 1

... V Tolerant on all Pins (Inputs and I/Os) 100–Pin TQFP Package The PowerPC name is a trademark of IBM Corp., used under license therefrom. i960 and Pentium are trademarks of Intel Corp. REV 2 2/18/98 MOTOROLA FAST SRAM Motorola, Inc. 1998 Order this document by MCM69F618C/D MCM69F618C TQ PACKAGE TQFP CASE 983A–01 ...

Page 2

... SA0 SGW SW SBa SBb SE1 SE2 SE3 G MCM69F618C 2 FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 16 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b K2 ENABLE REGISTER 2 16 64K x 18 ARRAY DATA–IN REGISTER K DQa, DQb MOTOROLA FAST SRAM ...

Page 3

... DQb 18 DQb DQb 22 DQb 23 DQb MOTOROLA FAST SRAM PIN ASSIGNMENT ...

Page 4

... Other vendors’ RAMs may have implemented this Sleep Mode (ZZ) feature. NC — No Connection: There is no connection to the chip. Description MOTOROLA FAST SRAM ...

Page 5

... INTERLEAVED BURST ADDRESS TABLE 1st Address (External ) 2nd Address (Internal ) X00 X01 X10 X11 WRITE TRUTH TABLE Cycle Type Read Read Write Byte a Write Byte b Write All Bytes Write All Bytes MOTOROLA FAST SRAM SE2 SE3 ADSP ADSC ADV ...

Page 6

... Max Unit Notes MOTOROLA FAST SRAM ...

Page 7

... Data states are all zero. 4. Device in Deselected mode as defined by the Truth Table. CAPACITANCE (f = 1.0 MHz 3 Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM (Voltages Referenced Symbol Min V DD 3.135 V IL – 0. ...

Page 8

... Max Min Max Unit Notes — 16.6 — ns — 6 — ns — 6 — — — — 0 — — 3 — — 0 — — — 2.5 — ns — 0.5 — ns MOTOROLA FAST SRAM ...

Page 9

... MOTOROLA FAST SRAM MCM69F618C 9 ...

Page 10

... ADSP Sync Non–Burst, Flow–Through SRAM NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low Q(C) Q(D) D( ADSC ADV SE1 SE2 LBO D(F) D(G) D(H) WRITES MOTOROLA FAST SRAM ...

Page 11

... Opportunity/Affirmative Action Employer. MOTOROLA FAST SRAM ORDERING INFORMATION (Order by Full Part Number) 69F618C Blank = Trays Tape and Reel Speed (8.5 = 8 ns) Package (TQ = TQFP) MCM69F618CTQ9 MCM69F618CTQ10 MCM69F618CTQ9R MCM69F618CTQ10R are registered trademarks of Motorola, Inc. Motorola, Inc Equal MCM69F618CTQ12 MCM69F618CTQ12R MCM69F618C 11 ...

Page 12

... VIEW AB How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola ...

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