PCD5008H Philips Semiconductors, PCD5008H Datasheet
PCD5008H
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DATA SHEET PCD5008 FLEX Pager Decoder Product specification Supersedes data of 1997 Oct 27 File under Integrated Circuits, IC17 INTEGRATED CIRCUITS 1998 Jun 17 ...
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... Philips Semiconductors FLEX Pager Decoder CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 General 8.2 Clocking, reset and start-up 8.2.1 Oscillator 8.2.2 Reset and start-up conditions 8.3 Serial peripheral interface (SPI) 8.3.1 General 8.3.2 SPI interconnect 8.3.3 SPI transfer initiated by the host 8 ...
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... EXTAL 5 ORDERING INFORMATION TYPE NUMBER NAME PCD5008H LQFP32 plastic low profile quad flat package; 32 leads; body 7 1998 Jun 17 3 GENERAL DESCRIPTION This data sheet describes the operation of the PCD5008 integrated paging decoder fully compatible with the ...
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... Philips Semiconductors FLEX Pager Decoder 6 BLOCK DIAGRAM handbook, full pagewidth 12 EXTS0 11 EXTS1 14 SYMCLK 2 OSCPD 5 XTAL 76.8 kHz 6 OSCILLATOR EXTAL 32 CLKOUT CLOCK RECEIVER CONTROL Fig.1 Functional block diagram for PCD5008 pager decoder. 1998 Jun 17 NOISE SYMBOL SYNC DETECTOR INTERNAL SYNC CONTROL ...
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... Philips Semiconductors FLEX Pager Decoder 7 PINNING SYMBOL PIN I/O COORDINATE TOUT0 1 O OSCPD DD1 TEST2 4 I XTAL 5 O EXTAL SS1 TEST3 8 I TOUT3 9 O LOBAT 10 I EXTS1 11 I EXTS0 DD2 SYMCLK TOUT2 ...
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... It is also capable of retrieving real time information from a FLEX channel. 1998 Jun PCD5008H Fig.2 Pin configuration. The PCD5008 connects to any receiver capable of providing a 2-bit digital signal. The PCD5008 operates the paging receiver in an efficient power consumption mode. ...
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... Philips Semiconductors FLEX Pager Decoder The PCD5008 interfaces to a host through a serial peripheral interface (SPI). The host can then interpret the message information in an appropriate manner (numeric, alphanumeric, binary, etc.). This function is provided by the FLEXstack software. The PCD5008 enables the host to operate in a low power mode when no message information for the paging device is being received ...
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... Philips Semiconductors FLEX Pager Decoder handbook, full pagewidth RESET READY t LH(RESET-READY) 8.3 Serial peripheral interface (SPI) 8.3.1 G ENERAL All data communication between the PCD5008 and the host is done via the SPI using 32-bit data packets at data rates Mbits/s. SPI transfers are full-duplex and can ...
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... Philips Semiconductors FLEX Pager Decoder 8.3.3 SPI TRANSFER INITIATED BY THE HOST The following steps occur when the host initiates an SPI packet transfer, see Fig.5 for event timings: 1. The host selects the PCD5008 by driving the SS pin LOW. 2. The PCD5008 indicates that it is ready to start the SPI transfer by driving the READY pin LOW ...
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... Philips Semiconductors FLEX Pager Decoder handbook, full pagewidth SS (2) READY (1) SCK (3) D31 MOSI Z o(off) MISO D31 Numbers within parenthesis refer to sequence numbers, see Section 8.3.4. Fig.6 Typical multiple SPI transfers initiated by the PCD5008. handbook, full pagewidth SS READY SCK D31 MOSI Z o(off) MISO D31 Fig ...
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... Philips Semiconductors FLEX Pager Decoder 8.3.5 SPI PACKET FORMAT SPI data packets consist of an 8-bit ID (byte 3), followed by 24 bits of information (byte 2 to byte 0). See Table 1, note that bit 7 of byte 3 is the first bit on the bus. Table 1 Packet bit assignments BYTE BIT 7 ...
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... Philips Semiconductors FLEX Pager Decoder 8.3 OST TO DECODER PACKETS OVERVIEW This section summarises the packets which can be sent from the host to the decoder. Table 2 Host-to-decoder packet ID map ID (HEX) 00 checksum 01 configuration 02 control 03 all frame mode reserved (host should never send) ...
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... Philips Semiconductors FLEX Pager Decoder ID (HEX) 86 user address assignment (user address 6) 87 user address assignment (user address 7) 88 user address assignment (user address 8) 89 user address assignment (user address 9) 8A user address assignment (user address 10) 8B user address assignment (user address 11) ...
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... Philips Semiconductors FLEX Pager Decoder 8.4 Configuration and synchronisation 8.4.1 G ENERAL After a reset, all configuration data has to be (re)loaded into the PCD5008 by the host using the SPI. PCD5008 features which do not change during operation are configured using the configuration packet (Section 8.4.4), the receiver control packets (Section 8.5) and the address configuration packets (Section 8 ...
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... Philips Semiconductors FLEX Pager Decoder handbook, full pagewidth Y 1998 Jun 17 reset PCD5008 disables SPI transmit PCD5008 initializes checksum register to part ID value PCD5008 initiates part ID packet PCD5008 waits for SPI packet from host Y checksum packet? PCD5008 SPI transmit enabled? N packet data N matches checksum ...
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... Philips Semiconductors FLEX Pager Decoder 8.4.3 C ONFIGURATION SEQUENCE A typical configuration and synchronisation sequence would be as follows, see Fig.11 for event timings: 1. The PCD5008 is reset by the host. 2. After 1 second the PCD5008 interrupts the host to read the part ID by pulling the READY line LOW. ...
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... Philips Semiconductors FLEX Pager Decoder 8.4.4 C ONFIGURATION PACKET The configuration packet defines a number of different configuration options for the PCD5008. The PCD5008 ignores this packet when decoding is enabled, i.e. the ON bit in the control packet is set (Table 11). OFD: oscillator frequency difference (Tables 4 and 5). These bits represent the maximum frequency difference between the 76 ...
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... Philips Semiconductors FLEX Pager Decoder Table 6 Input signal polarity SIGNAL POLARITY EXTS1 0 0 normal 0 1 normal 1 0 inverted 1 1 inverted Table 7 FLEX 4 level FSK modulation selection EXTS1 EXTS0 Table 8 Part ID packet bit assignments BYTE BIT 7 ...
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... Philips Semiconductors FLEX Pager Decoder 8.4.7 C (ID = 02H) ONTROL PACKET The control packet defines a number of different control bits for the PCD5008. FF: force frame (Table 11). When set, each of these bits forces the PCD5008 to decode one of the FLEX frames irrespective of the system collapse value (for details of collapse values see Section 8 ...
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... Philips Semiconductors FLEX Pager Decoder 8.4.9 S (ID = 7FH) TATUS PACKET The status packet contains various types of information that the host may require and is sent to the host: Whenever the PCD5008 is polled and has no other data to send On events for which the PCD5008 is configured to send the status packet (Sections 8 ...
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... Philips Semiconductors FLEX Pager Decoder 8.5 Receiver control interface 8.5.1 G ENERAL The PCD5008 has 8 programmable receiver control lines S7. The host can program via SPI packets what setting is applied to the receiver control lines, the duration of warm-up and shut-down stages and the polling of the LOBAT pin ...
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... Philips Semiconductors FLEX Pager Decoder 8.5 ECEIVER WARM UP SEQUENCES 8.5.5.1 Normal receiver warm-up sequence The PCD5008 allows for steps associated with warming up the receiver. When the PCD5008 turns on the receiver while decoding, it starts the warm-up sequence 160 ms before it requires valid signals at the EXTS1 and EXTS0 input pins ...
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... Philips Semiconductors FLEX Pager Decoder 8.5.5.3 Receiver warm-up setting packets (ID = 11H to 15H) CLS: control line setting (Table 15). This is the value to be output on the receiver control lines (S0 to S7) for this receiver warm-up state. Value after reset = 0. SE: step enable (Table 15). The receiver setting is enabled when the bit is set ...
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... Philips Semiconductors FLEX Pager Decoder 8.5.6 A CTIVE RECEIVER STATES 8.5.6.1 General In addition to the warm-up and shut-down states, the PCD5008 has four active receiver states. When these settings are applied to the receiver control lines, the PCD5008 is decoding the EXTS1 and EXTS0 input signals. The timing of these signals and their duration depends on the FLEX data stream ...
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... Philips Semiconductors FLEX Pager Decoder 8.5.6.2 Receiver on setting packets (ID = 16H to 19H) LBC: low battery check (Table 17). If this bit is set, the PCD5008 checks the status of the LOBAT port just before leaving this receiver sync setting state. Value after reset = 0. CLS: control line setting (Table 17). This is the value to be output on the receiver control lines for this receiver sync setting state ...
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... Philips Semiconductors FLEX Pager Decoder 8.5 ECEIVER SHUT DOWN SEQUENCE The PCD5008 allows steps associated with shutting down the receiver. When the PCD5008 decides to turn off the receiver, the first shut-down setting, if enabled, is applied to the receiver control lines for the corresponding shut-down time. At the end of the last used shut-down time, the receiver off setting is applied to the receiver control lines ...
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... Philips Semiconductors FLEX Pager Decoder 8.6 Configuration of the FLEX 8.6.1 G ENERAL A CAPCODE specifies a decoder address, the collapse value of the address and whether single-phase, any-phase or all-phase address. The PCD5008 supports single-phase and any-phase operation. The FLEX protocol provides a standard mechanism to derive phase and frame in which an address should be transmitted. ...
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... Philips Semiconductors FLEX Pager Decoder 8.6.3 CAPCODE RANGES A CAPCODE represents user addresses ranging from 1 to 5370810366. A short CAPCODE can have address values below 2031615 and are represented in the data stream by a single address codeword. Some short addresses have been reserved for special purposes: ...
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... Philips Semiconductors FLEX Pager Decoder 8.6.4 A DDRESS CALCULATION Address codeword values generally do not coincide with (part of) the user address as specified in the CAPCODE. To find the address codewords corresponding to a user address a conversion has to be done (Table 24). The type of conversion depends on the CAPCODE range in which the user address is located ...
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... Philips Semiconductors FLEX Pager Decoder 8.6.5 P HASE AND FRAME CALCULATION The method for specifying the phase and base frame of a pager is specified in the CAPCODE type: The phase, base frame are extracted by standard rules from the user address field in the CAPCODE (CAPCODE types A to L). ...
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... Philips Semiconductors FLEX Pager Decoder 8.6.6 C ONFIGURATION OF USER ADDRESSES (ID = 78H, 80H 8FH) TO The PCD5008 has 16 user address locations which can be programmed as long or short, and configured as priority and/or tone-only. After a reset all address locations are disabled. Short addresses occupy a single location, long addresses occupy two locations. The first word of a long ...
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... Philips Semiconductors FLEX Pager Decoder 8.6.7 C ONFIGURATION OF ASSIGNED FRAMES AND PAGER (ID = 20H COLLAPSE TO The assigned frame and collapse value determine the frames in which the decoding device typically looks for messages (other system factors can cause the decoding device to look in other frames in addition to the typical frames) ...
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... Philips Semiconductors FLEX Pager Decoder 8.7 Call data packets 8.7.1 G ENERAL The PCD5008 sends data extracted from the FLEX signal to the host in SPI packets using the following packet types: BIW packets which contain data transmitted in BIWs Address packets which indicate that a call has been ...
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... Philips Semiconductors FLEX Pager Decoder 8.7.4 N UMERIC VECTOR PACKET WN: word number of vector ( decimal) (Table 31). WN describes the location of the vector word in the frame. e: error (Table 31). Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed the vector value is determined to be invalid ...
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... Philips Semiconductors FLEX Pager Decoder 8.7 HORT MESSAGE TONE ONLY VECTOR PACKET V: vector type identifier, these bits set to 010 for a short message/tone-only vector (Table 33). WN: word number of vector ( decimal) (Table 33). WN describes the location of the vector word in the frame. e: error (Table 33). Set if more than 2 bit errors are ...
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... Philips Semiconductors FLEX Pager Decoder 8.7 BINARY ALPHANUMERIC AND SECURE MESSAGE VECTORS V: vector type identifier (Table 35). WN: word number of vector ( decimal) (Table 36). WN describes the location of the vector word in the frame. e: error (Table 36). Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed the vector value is determined to be invalid ...
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... Philips Semiconductors FLEX Pager Decoder 8.7.7 S HORT INSTRUCTION VECTOR V: these bits are set 001 for a short instruction vector. WN: word number of vector ( decimal) (Table 37). WN describes the location of the vector word in the frame. e: error (Table 37). Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed the vector value is determined to be invalid ...
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... Philips Semiconductors FLEX Pager Decoder 8.7.8 M (ID = 03H ESSAGE PACKETS 8.7.8.1 General The message field follows the vector field in the FLEX protocol. It contains the message data, checksum information, and may contain fragment and message numbers (Sections 8.8.7 and 8.8.5). If the error bit of a vector word is not set and the vector word indicates that there are message words associated with the page, the message words are sent in message packets to the host ...
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... Philips Semiconductors FLEX Pager Decoder K: least significant 2 bits of 6 bit message checksum (Tables 41 and 42), most significant 4 bits are in the vector word. See Section 8.8.6 for a description of message checksums. N: message number (Table 42). See Section 8.8.7 for a description of message numbering. R: message retrieval flag (Table 42). When this bit is set, the pager expects this message to be numbered ...
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... Philips Semiconductors FLEX Pager Decoder 8.7.8.3 Alphanumeric Message FLEX alphanumeric messages are encoded using the 7-bit encoded alphanumeric character set defined in Table 43. Characters are placed in codewords along with additional information about the message as described in Tables 44 and 45 and the following definitions. The 7-bit characters of the message are designated lower case letters etc ...
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... Philips Semiconductors FLEX Pager Decoder K: 10-bit fragment checksum (Tables 44 and 45). See Section 8.8.6 for a description of message checksum. C: 1-bit message continued flag (Tables 44 and 45). When this bit is set, fragments of this message are to be expected in following frames. See Section 8.8.5 for a description of message fragmentation. F: 2-bit message fragment number (Tables 44 and 45). ...
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... Philips Semiconductors FLEX Pager Decoder 8.7.8.4 Hex/binary message FLEX hexadecimal/binary messages may be encoded using any word size (blocking length) in the range bits. Words are placed in codewords along with additional information about the message as described in Tables 46 and 47 and these definitions. The message data in Tables 46 and 47 have blocking lengths of 4 bits ...
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... Philips Semiconductors FLEX Pager Decoder F: 2 bit message fragment number (Table 48). This is a modulo 3 message fragment number which is incremented successive message fragments. See Section 8.8.5 for a description of message fragmentation. Table 46 Vector type V = 110 first fragment MESSAGE WORD ...
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... Philips Semiconductors FLEX Pager Decoder 8.7 LOCK NFORMATION ORD (ID = 00H) The FLEX protocol allows systems to transmit time information using block information words. The information carried in a BIW depends on the BIW word format (Table 49). The first BIW of each phase, carrying information about the frame structure, is used internally by the PCD5008 and is never transmitted to the host ...
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... Philips Semiconductors FLEX Pager Decoder Y: year field (Table 50). This represents the year with modulo 32 arithmetic. 00000 to 11111 binary representing years 1994 to 2025 and 2026 to 2057. S: seconds field (Table 51). This represents a coarse value of the seconds field. These bits represent the 1 seconds in minute (7.5 s) increments. ...
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... Philips Semiconductors FLEX Pager Decoder 8.8 Message reception 8.8.1 FLEX SIGNAL STRUCTURE The FLEX signal transmitted on the radio channel (see Fig.17) consists of a series of four minute cycles, each cycle having 128 frames at 1.875 seconds per frame. A pager may be assigned to process any number of the frames ...
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... Philips Semiconductors FLEX Pager Decoder handbook, full pagewidth cycle 0 cycle 1 frame 0 frame 1 sync block 0 sync (115 ms) sync 1 frame info 112 bits @ 1600 bps (70 ms) 1998 Jun 17 15 cycles (1 hour) cycle cycle 13 1 cycle (4 minutes) = 128 frames frame frame 126 1 frame (1.875 seconds) = sync block 1 ...
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... Philips Semiconductors FLEX Pager Decoder 8.8.2 M ESSAGE BUILDING The PCD5008 sends data from the FLEX host in packets. Data is transmitted one block at a time, and one phase at a time. For a 2 phase transmission, information in block 0 phase-A is converted into packets and sent to the host, then information in block 0 phase-C ...
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... Philips Semiconductors FLEX Pager Decoder 8.8.3 A (ID = 03H) LL FRAME MODE The FLEX protocol requires pagers to be capable of receiving data in frames other than pagers’ programmed frames and frames implied by collapse values. This is achieved in the PCD5008 by all frame mode (AFM) which is required to implement the following features: Fragmented messages Section 8 ...
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... Philips Semiconductors FLEX Pager Decoder 8.8.4 T EMPORARY ADDRESSES FLEX allows dynamic group calls in which a common message is sent to a group of paging devices. This is achieved by assigning the same temporary address (TA) to each pager in the group using the pagers’ personal addresses and the short instruction vector. The short ...
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... Philips Semiconductors FLEX Pager Decoder 8.8.5 M ESSAGE FRAGMENTATION The FLEX frame length limits the maximum number of message codewords that can be associated with an address codeword. Messages longer than 84 codewords must be sent as several fragments. The PCD5008 uses AFM (Section 8.8.3) to allow the reception of fragmented messages. ...
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... Philips Semiconductors FLEX Pager Decoder Table 57 Alphanumeric message without fragmentation PACKET PHASE NUMBER TYPE 1st address 1 A 2nd vector 1 A 3rd message A 4th AFM Table 58 Alphanumeric message with fragmentation PACKET PHASE NUMBER TYPE 1st address 1 A 2nd vector 1 A 3rd message ...
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... Philips Semiconductors FLEX Pager Decoder 8.8.5.1 Fragmentation of non-7-bit character sets FLEX alphanumeric messages can be used to send symbolic characters like Chinese, Kanji, etc. In this case several ASCII characters are used to represent each symbolic character. Enhanced fragmentation (EF) rules are provided by FLEX to allow character positions within ...
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... Philips Semiconductors FLEX Pager Decoder 9 LIMITING VALUES In accordance with the absolute maximum rating system (IEC 134). SYMBOL PARAMETER V supply voltage DD I supply current input current (any input output current (any output input voltages (all inputs total power dissipation ...
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... Philips Semiconductors FLEX Pager Decoder 11 AC CHARACTERISTICS + 1 amb DD digital output; unless otherwise specified. SYMBOL PARAMETER Reset timing t RESET pulse width W(rst) t RESET LOW to READY HIGH LH(RESET-READY) t RESET HIGH to READY LOW stable 76.8 kHz clock HL(RESET-READY) Start-up timing ...
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... Philips Semiconductors FLEX Pager Decoder 12 OSCILLATOR CHARACTERISTICS +70 C; note 1. amb SYMBOL PARAMETER external capacitor at pin EXTAL external capacitor at pin XTAL 2 R external feedback resistor f g oscillator transconductance m(osc) I oscillator operating supply current osc Notes 1. Designed for quartz crystal type: SEIKO VTC200 or equivalent; parameters 76800Hz, R ...
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... Philips Semiconductors FLEX Pager Decoder 15 TEST AND APPLICATION INFORMATION 15.1 Example application handbook, full pagewidth V sup SYMCLK CLKOUT RECEIVER FRONT-END AND EXTS0, EXTS1 4-LEVEL 2 DEMODULATOR LOBAT 1998 Jun 17 DC/DC CONVERTER 10 F 100 nF OSCPD, V DD1 , V DD2 TEST2, TEST3 PCD5008 EXTAL XTAL V SS1 , V SS2 76 ...
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... Philips Semiconductors FLEX Pager Decoder 15.2 System block diagram handbook, full pagewidth PAGING RECEIVER RF RECEIVER INTEGRATED IF AMPLIFIER & DEMODULATOR 1998 Jun 17 BATTERY LOW DETECTOR battery low indication receiver control lines reset 8 PCD5008 demodulator serial data peripheral interface 2 5 76.8 kHz crystal Fig.19 System block diagram. ...
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... Philips Semiconductors FLEX Pager Decoder 15.3 FLEX encoding and decoding rules The encoding and decoding rules identify the minimum requirements which must be met by the paging device, paging terminal or other encoding equipment to properly format a FLEX data stream for RF transmission and to successfully decode it. ...
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... Philips Semiconductors FLEX Pager Decoder 16 PACKAGE OUTLINE LQFP32: plastic low profile quad flat package; 32 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.60 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors FLEX Pager Decoder 17 SOLDERING 17.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities ...
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... Philips Semiconductors FLEX Pager Decoder 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. ...
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... Philips Semiconductors FLEX Pager Decoder 1998 Jun 17 NOTES 63 Product specification PCD5008 ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...