SAA6721E Philips Semiconductors, SAA6721E Datasheet
SAA6721E
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SAA6721E Summary of contents
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... DATA SHEET SAA6721E SXGA RGB to TFT graphics engine Preliminary specification File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 1999 May 11 ...
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... TIMING CHARACTERISTICS 12 APPLICATION INFORMATION 13 PACKAGE OUTLINE 14 SOLDERING 14.1 Introduction to soldering surface mount packages 14.2 Reflow soldering 14.3 Wave soldering 14.4 Manual soldering 14.5 Suitability of surface mount IC packages for wave and reflow soldering methods 15 DEFINITIONS 16 LIFE SUPPORT APPLICATIONS 17 PURCHASE OF PHILIPS I 2 Preliminary specification SAA6721E 2 C COMPONENTS ...
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... Special mode for operation without external memory. 1.7 Miscellaneous Internal Phase-Locked Loop (PLL) for memory and panel clock generation from the system clock 2 I C-bus interface with 2 selectable addresses Boundary scan test circuit and Joint Test Action Group (JTAG) test controller. 3 Preliminary specification SAA6721E 16 SDRAM, 256k 32 SGRAM or ...
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... TYPE NUMBER NAME SAA6721E BGA292 1999 May 11 The SAA6721E must be embedded into a system containing a microcontroller with an I interface. For multi-sync capabilities a frame buffer built from SGRAM or SDRAM is needed. The size of this frame buffer depends on the maximum resolution and bandwidth needed for the application. For converting the analog RGB stream into a digital data stream one or two ADCs with 3 channels each for R, G and B are needed ...
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... INTERFACE frequency, phase and GLOBAL CONTROL JTAG colour UNIT CONTROLLER information LINE MEMORY UP COLOUR PANNING SCALER CORRECTION UNIT YUV RGB ON TEMPORAL SAA6721E SCREEN DITHERING DISPLAY MEMORY INTERFACE DE-INTERLACER DQ63 DQM BA A10 RAS CAS WE MCLKO V SSD to to DQ0 A0 Fig.1 Block diagram. OVVS ...
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... Fig.2 Pin configuration. (1) I/O input RGB/YUV sample clock input RGB/YUV vertical sync input RGB/YUV horizontal sync input video input port A; RGB port 0 red channel or YUV port luminance input input input input input input input 6 Preliminary specification SAA6721E MHB242 DESCRIPTION ...
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... VPD6 = HREF active horizontal video) input input input input input input video input port E; RGB port 1 green channel input input input input input input input input video input port F; RGB port 1 blue channel input input input input input input input 7 Preliminary specification SAA6721E DESCRIPTION ...
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... A green channel output output output output output output output output panel port A blue channel output output output output output output output output panel port B red channel output output output output output output output 8 Preliminary specification SAA6721E DESCRIPTION ...
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... Row Address Strobe (RAS) signal (active LOW) output memory Column Address Strobe (CAS) signal (active LOW) output memory Write Enable (WE) signal (active LOW) output memory data mask (active LOW) 9 Preliminary specification SAA6721E DESCRIPTION ...
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... Preliminary specification SAA6721E DESCRIPTION ...
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... JTAG test controller clock; note 2 input JTAG test controller reset (active LOW); note 2 input JTAG test data input; note 2 input JTAG test mode select; note 2 output JTAG test data output 11 Preliminary specification SAA6721E DESCRIPTION ...
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... PLL circuitry supply voltage for internal PLL circuitry not connected not connected not connected not connected not connected not connected not connected not connected not connected not connected 12 Preliminary specification SAA6721E DESCRIPTION ...
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... It can be generated internally by the PLL from the system clock (CLK external quartz oscillator. If the internal PLL is used, the memory clock frequency can be derived from the following formula: f_system f_memory = ----------------------- - N Where N = pre-divider ratio and f_system = clock at pin CLK. 13 Preliminary specification SAA6721E (VCLK) (MCLKI) 16 ...
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... VVS, and the horizontal synchronization pulse is connected to pin VHS. For calibrating the connected Analog-to-Digital Converter (ADC) the SAA6721E delivers a clamp pulse at pin CLAMP, and a gain correction pulse at pin GAINC (see Fig.4). The sample window of the RGB input port is controlled by four counters ...
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... VPD6 (HREF) and the end of valid video data is marked by the falling edge at pin VPD6. Figure 5 illustrates this at a YUV example ... ... Fig.5 CREF and HREF timing. 15 Preliminary specification SAA6721E MHB244 Y5 Y6 Y719 XX V716 U718 V718 XX MHB245 ...
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... X V04 X X V03 X X V02 X X V01 X X V00 X X VCLK VCLK ... MHB246 00 00 EAV XX MHB247 SAA6721E V07 Y17 V06 Y16 V05 Y15 V04 Y14 V03 Y13 V02 Y12 V01 Y11 V00 Y10 ...
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... Mbytes. But only half of this memory will be used by the SAA6721E. The memory port of the SAA6721E can be divided into 4 SDRAM channels. Each channel is 16 bits wide, and provides in High Speed Channel (HSC) mode with a 125 MHz memory clock and an effective bandwidth of 228 Mbits/s ...
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... With these devices a frame buffer can be built, without wasting memory because of bandwidth. In case of SGRAM usage, the memory data bus of the SAA6721E can be split into 2 channels of 32 bits each. Table 5 SGRAM channel configurations ...
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... If write mode was selected, the master sends the register address to be written and then the data bytes. If read mode was selected, the SAA6721E sends the data bytes starting from the last address accessed either by write command or the next address at a read command. ...
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... The odd line handling is done in the same way. 7.9 Scaling algorithm The SAA6721E features different scaling engines for up and downscaling, for both horizontal and vertical processing. The horizontal scaling engines are independent from each other. The vertical scaling engines share the line buffer, so they cannot operate in parallel ...
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... SYSTEM DESCRIPTION 8.1 Programming registers The SAA6721E is a highly integrated device with many features. To get the desired functionality and performance it must be programmed correctly. In general, before programming, the device must be switched to the internal reset state to prevent unwanted functions while changing the registers ...
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... Preliminary specification SAA6721E non_black_lines[ non_black_pixels[ memory_ reset_ reset_ init input_path memory_ path csm_ frc_on blank_ bypass screen post_div_ pll_enable pll_pclk ...
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... D4 yuv422_ mode SDRAM_burst_length_code SDRAM_burst_length CAS_latency down_v_ up_v_ up_h_ scaler_ coeff_prog coeff_prog mem up_v_corr Preliminary specification SAA6721E red_prog green_ blue_prog prog data_width[1 and 0] deint_mode[1 and 0] burst_seq_length t_RCD t_RP t_RC field1_row[ field2_row[ fi ...
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... Preliminary specification SAA6721E up_h_incr[ pic_v_offset[ pic_h_offset[ out_v_size[ out_h_size[ clk_ sample_ ovl_ gating_on edge syncs_ ...
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... W osd_fg_colour1_green 149 W osd_fg_colour1_blue 150 W osd_fg_colour2_red 151 W osd_fg_colour2_green 152 W osd_fg_colour2_blue 153 W osd_fg_colour3_red 1999 May osd_v_size osd_h_size Preliminary specification SAA6721E zoom2 char_size osd_v_offset[ osd_h_offset[ osd_ active ...
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... W osd_bg_colour7_green 191 W osd_bg_colour7_blue 192 W osd_fg_ colour7_ transp 1999 May osd_fg_ osd_fg_ osd_fg_ colour6_ colour5_ colour4_ transp transp transp 26 Preliminary specification SAA6721E osd_fg_ osd_fg_ osd_fg_ colour3_ colour2_ colour1_ transp transp transp D0 osd_fg_ colour0_ transp ...
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... Preliminary specification SAA6721E osd_fg_ osd_fg_ osd_fg_ colour3_ colour2_ colour1_ alpha alpha alpha osd_bg_ osd_bg_ osd_bg_ colour3_ colour2_ colour1_ ...
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... Vsync present Vsync not present Hsync polarity Negative Hsync Positive Hsync Vsync polarity Negative Vsync Positive Vsync 1999 May Preliminary specification SAA6721E h_hs_end[ h_de_start[ h_de_end[ h_active_start[ v_vs_end[ h_max_len[ SUBADDRESS R ...
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... R/W 5 and 6 7 and 8 9 and and and 19 20 and 21 22 and 23 29 Preliminary specification SAA6721E DATA R D10 D11 to D0 D10 to D0 D11 ...
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... Conversion YUV to RGB enabled Straight RGB processing enabled YUV processing clock multiplexer Clock will be applied at pin VCLK Clock will be applied at pin MCLKI 1999 May 11 SUBADDRESS R Preliminary specification SAA6721E DATA D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 ...
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... DIVIDER N OFFSET Post-divider n-counter offset programming 1999 May 11 SUBADDRESS R Preliminary specification SAA6721E DATA D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 logic 1 D6 logic 0 logic 1 ...
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... RGB processing enabled Input interface activation No data sampling Data sampling enabled Interlaced RGB mode Non-interlaced RGB processing Interlaced RGB processing 1999 May 11 SUBADDRESS R Preliminary specification SAA6721E DATA D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 ...
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... W 39 and and Preliminary specification SAA6721E DATA D0 logic 0 logic 1 D1 logic 0 logic 1 D3 and and and and and and and and and ...
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... SDRAM initialization code for burst length 1999 May 11 SUBADDRESS R Preliminary specification SAA6721E DATA D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic and and and ...
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... Blue colour component for blank screen generation 1999 May ABLE ) in clocks T 14 ABLE ) in clocks ) in clocks RRD T 14 ABLE ) in clocks Preliminary specification SAA6721E SUBADDRESS R and 57 W D10 and 60 W ...
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... Fraction of vertical downscaling increment ( H ORIZONTAL DOWNSCALE INCREMENT Increment for horizontal downscaling 1999 May 11 SUBADDRESS 76 and 100 79 and 100 1 ) 100 36 Preliminary specification SAA6721E R/W DATA logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 ...
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... Blue colour component for border generation 1999 May 11 SUBADDRESS 100 and 89 90 and 91 92 and 93 94 and Preliminary specification SAA6721E R/W DATA D10 D11 D10 D11 ...
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... May 11 SUBADDRESS R 100 and 101 W 102 and 103 W 104 W 105 and 106 W 107 and 108 W 109 and 110 W 38 Preliminary specification SAA6721E DATA D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 ...
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... W 138 and 139 W 140 and 141 W 142 W 143 W 144, 147, 150, W 153, 156, 159, 162 and 165 39 Preliminary specification SAA6721E DATA D10 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D10 to D0 D11 to D0 ...
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... W 179, 182, 185, 188 and 191 192 W 193 W 194 W 195 W 40 Preliminary specification SAA6721E DATA logic 0 logic logic 0 logic logic 0 logic 1 ...
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... SUBADDRESS R/W 196 W 197 W 198 W 199 W 200 W 201 W 202 W 41 Preliminary specification SAA6721E DATA and and and and and logic 0 logic 1 D1 ...
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... W 206 and 207 W 208 and 209 W 210 and 211 W 212 and 213 W 214 and 215 W 216 and 217 W 42 Preliminary specification SAA6721E DATA D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 ...
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... Clock management 8.2.1 C LOCK GENERATION AND MULTIPLEXING For normal operation the SAA6721E uses two clock inputs; pin VCLK and pin CLK. VCLK is used as the sample clock provided by the external ADCs or decoder. The frequency and the sample edges of this clock depend on the number of ADCs connected the video dot ...
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... Table 9 Clock divider programming P-COUNTER RATIO 1.5 2.0 2.5 3.0 3.5 1999 May 11 PRE-DIVIDER PLL 32 Fig.11 Clock generator. Fig.12 Clock waveforms. N-COUNTER (HEX) (HEX Preliminary specification SAA6721E MCLKO 2 POST-DIVIDER PCLK MHB251 N-OFFSET HALF CLK COUNTER (HEX MHB252 ...
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... Preliminary specification SAA6721E N-OFFSET HALF CLK COUNTER (HEX ...
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... Both start counting from the second edge of VHS. The polarity of CLAMP is given with clamp_pol. h_offset Fig.13 RGB data sampling. 46 Preliminary specification SAA6721E VCLK VCLK SAMPLE EDGE dot clock positive 1 dot clock both 2 ...
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... They are the same as for programming the RGB input, v_offset, h_offset, v_length, and h_length. All offset and length values are relative to the whole frame, and not to odd or even fields (see Fig.15). 47 Preliminary specification SAA6721E MHB254 DESCRIPTION 0 YUV with CCIR 656 codes ...
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... CREF and applied at pin VPD7. Data is only to be sampled if this signal is asserted. Alternatively the line-locked video clock divided by two can be used (if provided by the decoder). In this event CREF must be DESCRIPTION tied to logic 1 or logic 0 depending on its programmed polarity. 48 Preliminary specification SAA6721E line number 1 314 2 315 3 316 4 ...
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... RAM with SDRAM_burst_length_code taken from the specification data of the SDRAM or SGRAM. The memory interface must be programmed to 64 words bursts by programming the RAM burst length SDRAM_burst_length to 8, and the number of these bursts in burst_seq_length to 8. The internal structure of the SAA6721E is optimized for 64 words bursts. 49 Preliminary specification SAA6721E ...
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... Register Set Cycle (RSC) mode time internally defined; cannot be RSC 8.5.2 I NITIALIZATION OF EXTERNAL MEMORY All SGRAM and SDRAM devices must be powered-up and initialized correctly. The SAA6721E memory interface is implemented to fulfil the INTEL PC100 SDRAM specification. Table 15 shows the required programming steps to initialize the memory correctly. Table 15 Memory initialization programming STEP ...
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... May 11 ALGORITHM field1_row/column ODD FIELD field2_row/column EVEN FIELD deint_mode 1/2 Fig.16 Memory usage for de-interlacing. bytes_per_pixel ---------------------------------------------------------------------- - 2 data_bus_width (bytes) 51 Preliminary specification SAA6721E MEMORY NEEDS 1 frame buffer 2 field buffers 2 field buffers 4 field buffers field1_row/column ODD FIELD field2_row/column EVEN FIELD field3_row/column ODD FIELD field4_row/column ...
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... This is the value for programming the increment correction values up_v_corr and up_h_corr. Example: XGA Horizontal: This means up_h_incr = 80 and up_h_corr = 0. Vertical: This means up_v_incr = 85 and up_v_corr = 33. 52 Preliminary specification SAA6721E number_of_output_pixels ------------------------------------------------------------------ - 64 = number_of_input_pixels 1 100 XGA 1024 ------------ - 64 51 ...
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... If the input frame is to large only the right and bottom part will be cropped. The colour of the generated border region must be set via border_colour_red, border_colour_green, and border_colour_blue. C-bus write addresses pic_v_offset pic_h_offset pic_h_offset OUTPUT FRAME Fig.17 Picture positioning. 53 Preliminary specification SAA6721E Panning unit pic_v_offset out_v_size out_h_size MHB257 ...
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... The sampling of the ports ovl0 and ovl1 is done on the positive edge of OVCLK in the event that sample_edge is asserted, otherwise on the falling edge of OVCLK. ovl_hs_latency ovl_hs_start ovl_v_offset OVERLAY WINDOW OUTPUT FRAME Fig.18 Overlay window positioning. 54 Preliminary specification SAA6721E ovl_h_length MHB258 ...
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... OSD controller during internal blanking. Clock gating is enabled by clk_gating_on. 8.9 Colour space matrix The back-end processing of the SAA6721E and the TFT panels require RGB video data. So the built-in colour space matrix is used to convert video data from YUV space into RGB space. It can be enabled by setting ...
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... A logic 1 selects 24 24 font, and a logic 0 the smaller 12 16 font. If the small 12 128 different characters can be defined. Alternatively characters of the larger 24 Table 18 gives some possible OSD settings. 56 Preliminary specification SAA6721E osd_v_size MHB260 24 character 16 font is used font can be used. ...
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... Table 7). The definition of a character is done with 3 bytes per line at 24 (72 bytes per character), and with 3 bytes per 2 lines font (24 bytes per character), see Fig.21. 57 Preliminary specification SAA6721E EFFECT 0 OSD character colours are displayed instead of the picture colours 1 OSD character colours defined as ...
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... Fig.21 Character matrix organization. 8.12 Temporal dithering (frame rate controller) The SAA6721E is able to display true colour (8 bits per colour) on high colour displays (6 bits per colour). The algorithm used is temporal dithering. This feature can be enabled by setting frc_on to logic 1 in the general configuration register block (see Table 7) ...
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... The border colour inserted by the output interface is the same as the blank colour in the memory interface; blank_colour_red, blank_colour_green, blank_colour_blue. active video border blanking h_de_end Fig.22 Output frame and timing. 59 Preliminary specification SAA6721E h_len_border PHS h_len_blank h_len_active h_max_len MHB262 ...
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... SXGA RGB to TFT graphics engine 8.13.3 T IMING REFERENCE SIGNALS The SAA6721E supports three timing reference signals to drive the panels: PVS (vertical synchronization pulse), PHS (horizontal synchronization pulse) and PDE (data qualifier). The polarity of these signals is programmable. To program high polarity the three programming registers (vsync_pol, hsync_pol, de_pol) must be set to logic 1 ...
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... HIGH-level output OH(LVTTL) voltage at LVTTL pins 1999 May unless otherwise specified. amb CONDITIONS MIN. 3.0 3.1 0.5 0.7V DDD 0.5 2.0 outputs at 3-state SDA sink current SDA sink current 2.4 0.85V 61 Preliminary specification SAA6721E TYP. MAX. 3.3 3.6 600 tbf 2 3.3 3.5 tbf tbf tbf 2 +0.3V DDD V + 0.5 V DDD +0 0.5 V ...
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... PD(o) 1999 May see Fig.23; unless otherwise specified. amb CONDITIONS 24 40 single ADC mode 25 double ADC mode 12 6.0 62 Preliminary specification SAA6721E MIN. TYP. MAX. 70 MHz 150 MHz 75 MHz 4 MHz ...
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... Notes 15pF and 15pF and 10pF and 1999 May 11 CONDITIONS = Preliminary specification SAA6721E MIN. TYP. MAX. 125 MHz 125 MHz 6 6 ...
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... MCLKI MCLKO 1999 May 11 t su(i) t h(i) data data transition valid period t h(o) t PD(o) Fig.23 Data timing diagram Fig.24 Memory clock timing. 64 Preliminary specification SAA6721E 1.5 V MHB490 1.5 V MHB491 ...
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... APPLICATION INFORMATION handbook, full pagewidth VIDEO SAA7113A PORT TDA8752 VGA PORT TDA8752 1999 May 11 YUV SDRAM SDRAM SDRAM 16 MBits 16 MBits 16 MBits RGB SAA6721E RGB PANEL PORT Fig.25 Test board. 65 Preliminary specification SAA6721E SDRAM 16 MBits EEPROM MICROCONTROLLER P87C695 2 I C-bus USB MHB263 ...
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... scale 27.2 24.7 27.2 24.7 4.0 1.27 26.8 24.0 26.8 24.0 3.9 REFERENCES JEDEC EIAJ 66 Preliminary specification detail 1.84 1.84 0.15 0.35 0.3 1.04 1.04 EUROPEAN PROJECTION SAA6721E SOT489 ISSUE DATE 98-05-06 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 67 Preliminary specification SAA6721E ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 May 11 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 68 Preliminary specification SAA6721E (1) REFLOW suitable suitable suitable suitable suitable ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1999 May 11 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 69 Preliminary specification SAA6721E 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors SXGA RGB to TFT graphics engine 1999 May 11 NOTES 70 Preliminary specification SAA6721E ...
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... Philips Semiconductors SXGA RGB to TFT graphics engine 1999 May 11 NOTES 71 Preliminary specification SAA6721E ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...