PM7324-BI PMC-Sierra Inc, PM7324-BI Datasheet
PM7324-BI
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PM7324-BI Summary of contents
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... S/UNI-ATLAS DATASHEET PMC-1971154 SATURN USER NETWORK INTERFACE ATM LAYER SOLUTION PMC-Sierra, Inc. ISSUE 7 PM7324 S/UNI-ATLAS DATASHEET ISSUE 7: JANUARY, 2000 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... IWRENB[4:1], IAVALID, IADDR[4:0], IDAT[15:0], IPRTY, ISOC, ORDENB, RPRTY, RDAT[15:0], RCA[4:1], RSOC and TCA[4:1]. Table 40, 44, 45 – Changed prop delay times for ICA[4:1], ISD[63:0], ISP[7:0], ESD[31:0] and ESP[3:0]. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION and setup ...
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... CONTINUOUSLY VIOLATING MODE ........................................................... 107 8.11.4 ATLAS POLICING CONFIGURATION ........................................................... 107 8.12 CELL COUNTING......................................................................................................... 108 8.13 OPERATIONS, ADMINISTRATION AND MAINTENANCE (OAM) CELL SERVICING 111 8.14 FAULT MANAGEMENT CELLS ................................................................................... 113 8.15 LOOPBACK CELLS...................................................................................................... 115 8.16 ACTIVATION/DEACTIVATION CELLS ........................................................................ 115 8.17 SYSTEM MANAGEMENT CELLS ................................................................................ 115 PROPRIETARY AND CONFIDENTIAL ISSUE 7 i PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... EGRESS PERFORMANCE MONITORING ACTIVATION / DEACTIVATION 430 11.6 JTAG SUPPORT .......................................................................................................... 431 11.6.1 TAP CONTROLLER....................................................................................... 432 12 FUNCTIONAL TIMING ............................................................................................................... 436 12.1 INGRESS INPUT CELL INTERFACE........................................................................... 436 12.2 INGRESS OUTPUT CELL INTERFACE....................................................................... 439 12.3 EGRESS INPUT CELL INTERFACE............................................................................ 441 12.4 EGRESS OUTPUT CELL INTERFACE........................................................................ 444 PROPRIETARY AND CONFIDENTIAL ISSUE 7 ii PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... S/UNI-ATLAS DATASHEET PMC-1971154 13 ABSOLUTE MAXIMUM RATINGS.............................................................................................. 447 14 D.C. CHARACTERISTICS .......................................................................................................... 448 15 A.C. TIMING CHARACTERISTICS............................................................................................. 450 16 MECHANICAL INFORMATION .................................................................................................. 464 PROPRIETARY AND CONFIDENTIAL ISSUE 7 iii PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... FIGURE 45 EGRESS INPUT CELL INTERFACE POLLED MODE (IPOLL=1) ........................................ 443 FIGURE 46 EGRESS OUTPUT CELL INTERFACE DIRECT MODE (TPOLL=0) .................................... 444 FIGURE 47 EGRESS OUTPUT CELL INTERFACE POLLED MODE (TPOLL=1) ................................... 445 FIGURE 48 MICROPROCESSOR INTERFACE READ TIMING .............................................................. 451 PROPRIETARY AND CONFIDENTIAL ISSUE 7 ........................................................................................................ 86 ...................................................................................................... 116 iv PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... FIGURE 54 INGRESS SRAM INTERFACE TIMING................................................................................. 459 FIGURE 55 EGRESS SRAM INTERFACE TIMING.................................................................................. 460 FIGURE 56 JTAG PORT INTERFACE TIMING........................................................................................ 461 FIGURE 57 ATLAS THETA JA VS. AIR FLOW GRAPH........................................................................... 463 FIGURE 58 432 PIN SBGA – BODY -(B SUFFIX)................................................................ 464 PROPRIETARY AND CONFIDENTIAL ISSUE 7 v PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... TABLE 42 INGRESS INPUT CELL INTERFACE...................................................................................... 456 TABLE 43 EGRESS OUTPUT CELL INTERFACE ................................................................................... 457 TABLE 44 INGRESS SRAM INTERFACE ................................................................................................ 458 TABLE 45 EGRESS SRAM INTERFACE ................................................................................................. 459 TABLE 46 JTAG PORT INTERFACE ...................................................................................................... 460 TABLE 47 ORDERING INFORMATION.................................................................................................... 463 TABLE 48 THERMAL INFORMATION...................................................................................................... 463 PROPRIETARY AND CONFIDENTIAL ISSUE 7 ........................................................................................................ 46 ........................................................................................................ 63 ........................................................................................................ 76 vi PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... PHYID/VPI/VCI address range, programmable dual leaky bucket UPC/NPC, per-connection CLP0 and CLP1 cell counts (programmable), OAM-PM termination, generation and monitoring, and OAM-FM termination, generation and alarm generation (monitoring). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 1 ...
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... Forward Severely Errored Cell Block (BIP-16 violations). 6. Forward Severely Errored Cell Block Combined (non-saturating) 7. Forward Lost CLP0+1 cell count. 8. Forward Lost CLP0 cell count. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 2 ...
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... Backward Total Lost CLP0 cell count. 29. Backward Lost Fwd Monitoring PM cell count. 30. Backward Lost Backward Reporting PM cell count. 31. Total Transmitted CLP0+1 cell count. 32. Total Transmitted CLP0 cell count. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 3 ...
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... Low power 0.35 micron, 3.3V CMOS technology with a 3.3V UTOPIA (SCI-PHY), 3.3/5V Microprocessor I/O interfaces and 3.3V external synchronous SRAM interfaces. The UTOPIA (SCI-PHY) and external Synchronous SRAM interfaces are 52 MHz max. 432 Super BGA package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 4 ...
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... RM cells received, number of errored OAM cells, number of errored RM cells, number of cells with unassigned/invalid VPI/VCI/PTI and the number of cells received with a non-zero GFC (ingress UNI only). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 5 ...
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... DATASHEET PMC-1971154 2 APPLICATIONS Wide Area Network ATM Core and Edge switches. ATM Enterprise and Workgroup switches. Broadband Access multiplexers. XDSL Access Multiplexers (DSLAMs). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 6 ...
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... PMC-940212, ATM SCI-PHY, “SATURN Compliant Interface for ATM Devices”, July 1994, Issue 2. ATMF TM4.0 – ATM Forum Traffic Management Specification Version 4.0, af-tm-0056.000, April, 1996. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 7 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 (Slave) (Slave) Interface Level1 SCI-PHY Interface Level1/Level2 (Master) (Master) Interface Level1/Level2 SCI-PHY Interface Level1/Level2 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION SCI-PHY trstb tms tck tdi tdo esoeb esrwb esadsb esa[19:0] esp[3:0] esd[31:0] esysclk halfsecclk ...
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... PHY device) directions. The S/UNI-ATLAS uses external synchronous flow-through SRAM to store the per-connection data structures. The device is capable of supporting up to 65536 connections. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 6 cells ...
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... The S/UNI-ATLAS is packaged in a 432 thermally enhanced BGA -SBGA package having a body size 1.54 mm and a ball pitch of 1.27 mm. This pin diagram can be downloaded from the PMC-Sierra website (http://www.pmc-sierra.com). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 10 ...
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... It is not necessary for RSOC to be asserted for each cell. An interrupt may be generated if RSOC is high during any word other than the first word of the cell structure. RSOC is sampled on the rising edge of RFCLK and considered valid only when one of the RRDENB[4:1] signals so indicates. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 11 ...
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... The selection of a particular PHY device from which to transfer a cell is indicated by the state of RADDR[4:0] and when RRDENB[1] is asserted. Note, RCA[ input only. The RCA[4:1] signals are sampled on the rising edge of RFCLK. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 12 ...
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... If the RPOLL pin is high, the RAVALID pin indicates that the RADDR[4:0] bus is asserting a valid PHY address for polling purposes. When this signal is deasserted, the RADDR[4:0] bus is set to 0x1F. RAVALID is not necessary when less than 32 PHY devices are being polled. RAVALID is updated on the rising edge of RFCLK. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 13 ...
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... ISADSB, ISOEB, ISRWB are updated on the rising edge of ISYSCLK. When ISD[63:0] and ISP[7:0] are outputs, they are updated on the rising edge of ISYSCLK. When ISD[63:0] and ISP[7:0] are inputs, they are sampled on the rising edge of ISYSCLK. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 14 ...
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... ISD[63:0] pins upon the rising edge of AK5 ISYSCLK which is written into the SRAM on the next ISYSCLK AL5 rising edge. ISD[63:0] is tristated on the rising edge of ISYSCLK. Contention is avoided by not performing a write during the cycle AJ6 after a read burst. AK6 AL6 AJ7 AH8 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 15 ...
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... ISD[33] ISD[32] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Pin Function No. AK7 Continued AL7 AJ8 AH9 AK8 AL8 AJ9 AK9 AL9 AJ10 AH11 AK10 AL10 AJ11 AH12 AK11 AL11 AJ12 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 16 ...
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... ISD[19] ISD[18] ISD[17] ISD[16] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Pin Function No. AH13 Continued AK12 AL12 AJ13 AK13 AL13 AJ14 AK14 AH15 AJ15 AL16 AK16 AJ16 AH16 AL17 AK17 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 17 ...
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... ISD[3] ISD[2] ISD[1] ISD[0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Pin Function No. AJ17 Continued AK18 AH17 AJ18 AL19 AK19 AJ19 AL20 AK20 AH19 AJ20 AL21 AK21 AH20 AJ21 AL22 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 18 ...
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... SRAM, the ATLAS generates correct parity. When data are being read from the SRAM, the ATLAS asserts a maskable interrupt indication upon parity error detection. No other action is taken, therefore, the ISP[7:0] may be unconnected if parity protection is not required. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 19 ...
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... ATLAS drives the data and parity busses. ISRWB is updated on the rising edge of ISYSCLK. AK23 The Ingress VC Table SRAM Address Strobe (ISADSB) qualifies the address bus. If the ISADSB output is asserted low, an SRAM access is initiated. ISADSB is updated on the rising edge of ISYSCLK. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 20 ...
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... FIFO, and output on bus ODAT[15:0]. When ORDENB is sampled high, no read is performed and outputs ODAT[15:0], OPRTY and OSOC are tristated if the OTSEN input is high. ORDENB must operate in conjunction with OFCLK to access the FIFO at a high enough rate to avoid a FIFO overflow. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 21 ...
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... ODAT[15:0] bus. OSOC is updated on the rising edge OFCLK. When the Ingress Output Cell Interface is configured for tristate operation using the OTSEN input, tristating of the OSOC output is controlled by the ORDENB input. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 22 ...
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... If fewer than 32 PHY devices are used, the IAVALID pin can be tied high. Note: In direct addressing mode, the 4-PHY configuration is not recommended. Instead the 4-PHY address-polling mode should be used. This does not apply to the Single or Dual-PHY configurations. IPOLL is assumed static input. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 23 ...
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... PHY device will be asserted 4 words before the end of the cell transfer. The selection of a particular PHY device to which a cell transferred is indicated by the state of the IADDR[4:0] bus when IWRENB[4:1] is asserted. Note, ICA[ output only. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 24 ...
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... When this signal is deasserted, the IADDR[4:0] bus must be set to 0x1F. If fewer than 32 PHY devices are being polled and the IAVALID pin is not functionally used, then IAVALID must be tied high. IAVALID is sampled on the rising edge of IFCLK. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 25 ...
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... Egress Output Cell Interface. TFCLK must cycle MHz or lower instantaneous rate, but a high enough rate to avoid a FIFO overflow. TSOC, TWRENB[4:1], TADDR[4:0], TAVALID, TPRTY and TDAT[15:0] are updated on the rising edge of TFCLK. TCA[4:1] is sampled on the rising edge of TFCLK. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 26 ...
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... Sampling of the TCA[4:1] signals resumes the cycle after the last octet of a cell has been transferred. If the TPOLL pin is high, the TCA[3:2] pins are redefined as TADDR[4:3] and the TCA[4] pin is redefined as TAVALID. Note, TCA[ input only. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 27 ...
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... PHY device should drive TCA[1] during the following clock cycle. Polling is performed in incrementing sequential order. The PHY device selected for transfer is based on the TADDR[4:0] value present when TWRENB[1] falls. The TADDR[4:0] bus is updated on the rising edge of TFCLK. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 28 ...
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... TDAT[15:0] data bus. If TBUS8 is high, the TPRTY signal indicates parity over the TDAT[7:0] data bus. The TPRTY signal is updated on the rising edge of TFCLK and is considered valid only when one of the TWRENB[4:1] signals so indicates. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 29 ...
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... ESYSCLK which is written into the SRAM on the next C16 ESYSCLK rising edge. ESD[31:0] is tristated on the rising edge of ESYSCLK. Contention is avoided by not performing a write D16 during the cycle after a read burst. A15 B15 C15 B14 D15 C14 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 30 ...
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... SRAM, the ATLAS generates correct parity. When data are being read from the SRAM, the ATLAS asserts a maskable interrupt indication upon parity error detection. No other action is taken, therefore, the ESP[3:0] may be unconnected if parity protection is not required. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 31 ...
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... ESRWB is updated on the rising edge of ESYSCLK. The Egress VC Table SRAM Address Strobe (ESADSB) qualifies B8 the address bus. If the ESADSB output is asserted low, the external SRAM samples the address asserted by the ATLAS. ESADSB is updated on the rising edge of ESYSCLK PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 32 ...
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... Egress MCIF configuration register is a logic 1. The first read of the Egress MCIF Data register will return the first word of the cell. EDREQ is deasserted after the last word of the cell has been read or an abort has been signaled. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 33 ...
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... D[15:8] should contain the most significant 8-bits and D[7:0] J29 should contain the least significant 8-bits of a word. H31 The bi-directional data bus, D[15:0 tolerant bus. H30 J28 H29 G31 G30 H28 G29 F31 F30 F29 E31 E30 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 34 ...
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... HALFSECCLK tolerant input. The Interrupt Request (INTB) output goes low when an ATLAS K31 interrupt source is active and that source is unmasked. INTB returns high when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 35 ...
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... TRSTB tolerant input. +5V Bias (VBIAS). The VBIAS input is used to implement the 5V B25 tolerance on the inputs of the Microprocessor and JTAG interfaces Interface volt tolerance is not required, VBIAS should be connected to the 3.3 volt power supply (i.e. the same as VDD). PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 36 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Pin Function No. The VDD power pins should be connected to a well-decoupled A1 +3.3V DC supply. A31 B2 B30 C3 C29 D4 D7 D10 D14 D18 D22 D25 D28 G4 G28 K4 K28 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 37 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Pin Function No. Continued P4 P28 V4 V28 AB4 AE4 AB28 AE28 AH4 AH7 AH10 AH14 AH18 AH22 AH25 AH28 AJ3 AJ29 AK2 AK30 AL1 AL31 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 38 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Pin Function No. A2 The ground pins should be connected to GND. A3 A14 A17 A18 A29 A30 B1 B3 B17 B29 B31 C28 C30 C31 D3 D29 P1 P31 R1 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 39 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Pin Function No. R2 Continued. U30 U31 V1 V31 AH3 AH29 AJ1 AJ2 AJ4 AJ30 AJ28 AJ31 AK1 AK3 AK15 AK29 AK31 AL2 AL3 AL14 AL15 AL18 AL29 AL30 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 40 ...
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... The VDD power must be applied before input pins are driven or the input current per pin be limited to less than the maximum DC input current specification. (20 mA) 3.3 Power down the device in the reverse sequence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 41 ...
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... PMC-1971154 8 FUNCTIONAL DESCRIPTION The PM7324 S/UNI-ATM Layer Solution (S/UNI-ATLAS or abbreviated as ATLAS monolithic integrated circuit that implements the ATM Layer functions that include fault and performance monitoring, header translation and cell rate policing. The S/UNI-ATLAS is a bi-directional part which is intended to be situated between the physical layer (PHY) devices and a switch core in the ingress side, and a traffic shaper and the PHY devices in the egress side ...
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... GCRA can be programmed to police any combination of user cells, OAM cells, Resource Management cells, high priority cells or low priority cells. Any one of four PHY policing configurations may be chosen. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 43 ...
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... Egress Cell Processor). The apparent FIFO depth can be configured from (default) cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 44 ...
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... The Ingress VC Table is a total of 960 bits per connection, however, not all rows need be used if features are disabled. Unused bits should be set to zero for backward compatibility with future devices within the ATLAS family. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 45 ...
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... Configuration TAT2 (30) Action2 Action1 I2 (2) (2) (14) Non-Compliant3 Violate GFR (1) State (3) Header (40) PrePo5 PrePo6 PrePo7 (8) (8) Unused (5) PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Right Leaf Right Primary Table (1) Branch (16) Record (16 NNI Field B Active1 Addr1 (11) (1) (1) (7) OAM VPC Pointer (16) (9) TAT1 (30) ...
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... < PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION I ...
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... PHY ID field must be less than or equal to 16. Field A and the PHYID are always LSB justified within the Primary Key (any unused MSBs are set to logic 0). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 . The number of bits in Field A plus the number of A PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 48 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE its < its its < its PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION . The second field I its 49 ...
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... ISSUE ize & tio ize & tio rim PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
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... Table is set to all zeros, this signifies the connection is a VPC, and the VCI field ignored. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE max. binary tre e depth ISYSCLK 1 ( cell word length)(IS YSCLK PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 6 cells/s period cells/s period) 51 ...
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... E ntry Ing ress Ing ress ntry E ntry Ing ress ntry PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION (LP + LA) words of memory Ing ress Ing ress Ing ress Ing ress ...
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... If Right Leaf is a logic 1, Right Branch contains the (16-bit address identifying the VC Table Address for that connection. If Right Leaf is a logic 0, Right Branch contains the 16-bit address pointing to another Secondary Search Table entry. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 0 Right Branch Primary Search ...
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... When a new VC is provisioned, the management software must initialize the contents of the VC Table record. Once provisioned, the management software can retrieve the contents of the VC Table record. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION = 0), the root of the single A 54 ...
Page 63
... The Excessive Policing bit is a logic 1 if any of the per-VC non- compliant cell counts on this connection is greater than 32767 (i.e. the MSB on one or more of the non-compliant cell counts is set to logic 1). This bit indicates that the non-compliant cell counts should be read and cleared to avoid counter saturation. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 55 ...
Page 64
... Ingress Cell Counting Configuration 2 register 0x237. This bit enables the generation of segment and end-to-end AIS, RDI and Continuity Check alarm interrupts. If this bit is logic 1, the ATLAS will assert segment and end-to-end AIS, PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 56 ...
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... RDI cell) and RDI cells which are generated as a result of the Send_RDI_Segment or Send_RDI_end_to_End bits also this setting to determine which Defect Type will be inserted. If this bit is a logic 1, any change of alarm state on this PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 57 ...
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... Enables Continuity Checking on segment flows. If the ForceCC bit in the Cell Processor Configuration Register 0x238 is logic 0, then when no user cells are transmitted over a 1.0 second (nominal) interval, a segment CC OAM cell is generated. The segment CC cell is generated at an interval of one per second (nominally). PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 58 ...
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... The Send_Seg_CC_Count is set to logic 1 (to provide a one second count) at connection setup time and each time the ATLAS sends a user cell on this connection. The count is decremented at one second intervals. If this count reaches zero (i.e. if the ATLAS writes back a zero at a one second boundary and PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 59 ...
Page 68
... If the Seg_AIS_Count reaches 0, the AIS_segment Alarm is cleared. The End_AIS_Count is set to a value of 3 (to provide a 2.5 +/- 0.5 sec count) upon receipt of an end-to-end AIS cell, and decrements at one second intervals. If the End_AIS_Count reaches 0, the AIS_end_to_end Alarm is cleared. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 60 ...
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... CC_RDI process, either the local Defect Type field programmed in the Ingress Defect Type registers, 0x226-0x22D unused value (0x6A) will be used. This field is used to store the Defect Location from a segment AIS PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 61 ...
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... If RDI cell generation is forced (using either the send_RDI Ingress VC table bits or the per-phy RDI register bits, 0x224 and 0x225) or generated by the CC_RDI process, either the local Defect Type field programmed in the Ingress Defect Type registers, 0x226-0x22D unused value (0x6A) will be used. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 62 ...
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... Alternate Egress Cell Count 1 (32) Alternate Egress Cell Count 2 (32) Received End-to-End AIS Defect Location [95:64] Received End-to-End AIS Defect Location [63:32] Received Segment AIS Defect Location [95:64] Received Segment AIS Defect Location [63:32] PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION VPI VCI (12) (16) PM Addr2 ...
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... If header translation is enabled, all F5 cells received from the Egress Input Cell Interface will have the VCI portion of their header replaced with this VCI field. If the connection connection, the VCI portion of the cell header is passed transparently. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 64 ...
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... < < < PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION I ...
Page 74
... BCIFHECUDF bit of the Egress Cell processor Direct Lookup Index Configuration 1 register 0x282 and the Ingress BCIFHECUDF bit in the Ingress Cell Processor Configuration 2 register 0x238. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 66 ...
Page 75
... ESA[19:16] = 0000), to perform its odd parity check. If the parity is found error, the BADVCtoUP bit, in register 0x280, determines whether the cell will be output to the Egress Microprocessor Cell Interface for logging, or discarded. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 67 ...
Page 76
... CC cell This bit becomes a logic user or segment CC, or end-to-end CC cell has been received within the last 3.5 +/- 0.5 sec. This bit is cleared upon receipt of a user cell, segment CC cell or end-to-end CC cell PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 68 ...
Page 77
... Output Cell Interface). The setting of this bit supercedes all other routing bits. If the Drop_UP bit is set, the ATLAS will not output generated OAM cells (Fwd PM, Bwd PM and Fault management) on this connection. This bit must be set to a logic 0 during connection PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 69 ...
Page 78
... RDI cells which are generated as a result of the CC_RDI process, the Per-PHY RDI Cell Generation register, 0x28C and 0x28D, or the Send_RDI_Segment and Send_RDI_end_to_end bits also use this setting to determine which Defect Type will be inserted. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 70 ...
Page 79
... Egress Cell Processor Direct Lookup Index Configuration 2 register 0x283, is logic 0, then when no user cells are transmitted over a 1.0 second (nominal) interval, an end-to-end CC OAM cell is generated. The end-to-end CC cell is generated at an interval of one per second (nominally). PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 71 ...
Page 80
... For F5 connections (VCCs), all cells with PTI = 101 are terminated and processed. An End-to-End termination point will also terminate all Segment connections, since by definition the End-to- End point is the end point for all OAM traffic. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 72 ...
Page 81
... RDI cell, and decrements at one second intervals. If the Seg_RDI_Count reaches 0, the RDI_segment Alarm is cleared. The End_RDI_Count is set to a value of 3 (to provide a 2.5 +/- 0.5 sec count) upon receipt of an end-to-end RDI cell, and PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 73 ...
Page 82
... AIS cell. This field is used in end-to-end RDI cells generated via the AUTORDI function (see Egress Cell Processor Configuration 1 register 0x280). If RDI cell generation is forced (using either the send_RDI Egress VC table bits or the Per-PHY RDI Cell generation PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 74 ...
Page 83
... VC table bits or the Per-PHY RDI Cell Generation register 0x28C- 0x28D) or generated by the CC_RDI process, either the local Defect Type field programmed in the Egress Cell Processor OAM Defect Type registers 0x292-0x299 or an unused value (0x6A) will be used. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 75 ...
Page 84
... Fwd Lost (16) CLP0+1 (16) Bwd Bwd Bwd SECB SECB SECB Errored Lost Misins (8) (8) (8) Bwd Lost (16) CLP0+1 (16) Transmitted CLP0+1 Count (32) PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Current Count BLER Fwd BMCSN CLP0+1 (16) stored (8) (8) Fwd Unused Fwd TUC0+1 FMCSN (8) (16) (8) Bwd Bwd Bwd TUC0+1 ...
Page 85
... This bit controls the forced insertion of a Forward Monitoring PM cell when the ATLAS is configured to insert Forward Monitoring PM cells. When the Force_FwdPM bit is logic 1, the ATLAS will force the insertion of a Forward Monitoring PM cell when the current cell count of CLP0+1 cells reaches N+N/2, where N is the PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 77 ...
Page 86
... The Bwd_PM0 bit must be set to a logic 1 initially. This bit is cleared upon receiving the first Backward Reporting cell. This clears the TUC_0, TUC_0+1, TRCC_0 and TRCC_0+1 counts. The Bwd_PM0 bit suppresses accumulation of error counts. If this bit is not set, error counts will be accumulated. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 78 ...
Page 87
... The Stored Block Error Result is the Block Error Result calculated on reception of the previous Forward PM cell stored in this field until the generated Backwards Reporting cell can use it. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 79 ...
Page 88
... Forward Monitoring cell. When not a monitor point, Fwd TUC_0+1 will be inserted in the TUC_0+1 field of generated Backwards Reporting cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 80 ...
Page 89
... Forward Monitoring source point between successive Forward PM cells. This count will be initialized automatically on reception of the first BR cell. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 81 ...
Page 90
... Forward Severely Errored Cell Blocks Combined. This running counter increments each time a SECB is declared. This value is inserted into the SECBC field of generated Backwards Reporting cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 82 ...
Page 91
... PM session. This count is not dependent on a threshold. Bwd Total Lost That is, the Total Lost CLP0 cell count is always incremented by the number CLP0 (16) of lost CLP0 user cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 83 ...
Page 92
... All error (Lost, Misinserted and Errored) counts and the Total Transmitted CLP0 and Total Transmitted CLP0+1 saturate at all ones and will not rollover. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 84 ...
Page 93
... ISSUE 7 OAM Performance Function Management Type Function 4 Specific Fields 45x8 FM BR Time Unused Fwd 2x8 Stamp 6AH MCSN 4x8 27x8 1x8 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Reserved EDC 6 (CRC-10 SECBC TRCC_ Block TRCC_ 1x8 0 Error 0+1 2x8 Result 2x8 1x8 ...
Page 94
... E gres sso r O utpu Int erface In g ress M icro p ro cesso r M icro p ro cesso r Interfac e C ell Interfac e PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION PM Addr1[6:0] G enerated Backw eporting PM Cell ( ress O utpu t C ell G enerated Interf ace ...
Page 95
... F4 VPC flow must have one common PM Address for the F4 flow. All user cells (at the F4 level) will be considered to be part of the F4 PM flow, and thus counted as such. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 87 ...
Page 96
... A maskable interrupt for each FIFO is provided to notify when valid data are in the FIFO. A maskable interrupt for each FIFO is provided to notify when the FIFO is at least half full. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 88 ...
Page 97
... If this bit is logic 1, the connection is an end-to-end point. The Status field contains a copy of the Status field contained in the Ingress or Egress VC Table. This field contains the 16-bit connection address with which the change of state is associated. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 89 ...
Page 98
... The HEC and UDF bytes can be passed through transparently, or replaced by the output header word and the UDF field of the Ingress VC Table. This is controlled by the GHEC and GUDF bits in register 0x200. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 90 ...
Page 99
... The ATLAS supports two instances of the Generic Cell Rate Algorithm (GCRA) for each connection. The policing operation is performed according to the Virtual Scheduling Algorithm outlined in ITU-T I.371. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 91 ...
Page 100
... ATLAS is 0.19% in accordance with ITU-T I.371 5.4.1.2. The Limit field is defined as: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PCR where 0 512 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 511 ...
Page 101
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Tolerance ( SCR t 1 MBS 1 BT SCR (cells/s) at the Peak Cell Rate (cells where 0 512 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 1 PCR 511 ...
Page 102
... ISSUE 7 Integer cells/s (this is the maximum 707 . 798 ns min ( . 0 125 )( 0035 707 . 798 ns L TAT max 1 PCR min I t max L t max max PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Fraction cell rate at 622Mbps then L shall max PCR t 94 ...
Page 103
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 2 .98 cells .49 cells PCR min 0 .75 cells .37 cells Therefore max . 20ns . CDVT max 160 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 160 ns max ...
Page 104
... CLP=0 cells. Increment the appropriate non-compliant cell count. 10 Reduce the priority of high priority cells and discard the low priority cells. Increment the appropriate non-compliant cell count. 11 Discard all non-conforming cells. Increment the appropriate non-compliant cell count. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 96 ...
Page 105
... Update TAT2 Update TAT1, TAT2 Pass No Action Update TAT1 Update TAT1 Update TAT2 Update TAT2 No Update Update TAT2 No Update No Update No Update PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION GCRA2 Fail Tag Discard Update TAT1 Update TAT1 Update TAT1, Update TAT1, TAT2 TAT2 No Update No Update ...
Page 106
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Definition Non-compliant CLP=0 cells. Non-compliant CLP=0+1 cells. Discarded CLP=0 cells. Discarded CLP=0+1 cells. Definition Non-compliant CLP=0 cells. Non-compliant CLP=0+1 cells. Tagged CLP=0 cells which are not discarded. Discarded CLP=0+1 cells. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 98 ...
Page 107
... COCUP bit for the connection should be set to logic 1, when per-PHY policing is enabled. The table below describes the ATLAS actions when per-PHY policing is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 99 ...
Page 108
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Per-PHY GCRA Pass No Action Update VC TAT Update VC TAT Update PHY TAT Update PHY TAT No Update Update PHY TAT No Update No Update No Update PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Fail Tag Discard Update VC TAT No Update No Update No Update No Update No Update No Update No Update 100 ...
Page 109
... PHY GCRA. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PHYTAT (30) PHY I (14) PHY Non-Compliant1 PHY PHY PHY Non-Compliant3 Police Action Config. (2) (2) PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 0 PHY L (14) (16) (16) 101 ...
Page 110
... Increment the appropriate non-compliant cell count. 11 Discard all non-conforming cells. Increment the appropriate non- compliant cell count. Definition Non-compliant CLP=0 cells. Non-compliant CLP=0+1 cells. Discarded CLP=0 cells. Discarded CLP=0+1 cells. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 102 ...
Page 111
... Tagged CLP=0 cells which are not discarded. Discarded CLP=0+1 cells. Per-VC Policing Compliant No update. Don’t update per-VC non-compliant counts. Update per-PHY non- compliant counts PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Non-Compliant Update per-VC non- compliant counts Don’t update per-PHY non-compliant counts. Update per-VC non- compliant counts. ...
Page 112
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Per-VC Policing Compliant No update. Update per-VC non- compliant counts. Update per-PHY non- compliant counts PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Non-Compliant Update per-VC non- compliant counts Update per-PHY non- compliant counts. Update per-VC non- compliant counts. ...
Page 113
... Partial Packet Discard state. Irrespective of the setting of the CLPCC_EN bit, if the first cell of the frame is a CLP = 1 cell, then any otherwise conforming CLP = 0 cells in the frame will be tagged. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 105 ...
Page 114
... Generic Frame Rate policing. Setting the MFL bit in the Ingress Cell Processor Configuration 2 register 0x238 to logic 1 enables the field. Setting this field to all zeros disables the MFL conformance test when the MFL bit, is set to logic 1. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 106 ...
Page 115
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Description Take no forced action Tag all CLP=0 cells. Take no action on CLP=1 cells. Tag all CLP=0 cells. Discard all CLP=1 cells Discard all CLP=0+1 cells. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 107 ...
Page 116
... Number of misinserted CLP0+1 cells not in SECB (misinserted) Number of BIP-16 errors. BIP-16 errors are not counted if there are lost cells, misinserted cells the MCSN is out of sequence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 108 ...
Page 117
... Number of cells with errored headers. These include cells with unassigned/invalid VPI/VCIs or invalid PTI values. (Ingress only) Last Unknown VPI.VCI value. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 109 ...
Page 118
... ATLAS will begin incrementing the cell counts at the above addresses the responsibility of the management software to ensure these locations are cleared before the ATLAS begins accumulating. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 110 ...
Page 119
... The OAM functionality of the ATLAS is symmetric in the Ingress and Egress directions. The OAM Configuration field for both the Ingress and Egress VC Tables is shown below: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 111 ...
Page 120
... The end-to-end CC cell is generated at an interval of one per second (nominally). If the ForceCC register bit is logic 1, then when the CC_Activate_End_to_End bit is logic 1, an end-to-end CC cell will be generated at an interval of once per second (nominally), regardless of the flow of user cells. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 112 ...
Page 121
... For F5 connections (VCCs), all cells with PTI = 101 are terminated and processed. The End-to-End point, by definition, is also the end point for segment cells. Therefore, at End-to-End points all segment cells, as defined above, are also terminated. PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 113 ...
Page 122
... The Ingress of the ATLAS also supports the generation of F5 AIS and RDI cells when associated F4 connections, which are terminated, enter the AIS alarm state. This is described in detail in section 8.18. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 114 ...
Page 123
... The VCC connections have a VPC Pointer [15:0] at location ISA[19:16] = 0010. This pointer must be configured to point to the F4 OAM connection. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 115 ...
Page 124
... onnection The following Fault Management scenarios are supported by the ATLAS at the Ingress direction. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION Ingress able ...
Page 125
... PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ctio n w ith fin tio ith efin ed seg ...
Page 126
... PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ctio n w ith fin tio ith efin ed seg ...
Page 127
... VPC Segment AIS alarm condition is exited. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE I era ted vaila -AIS -E tE PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 119 ...
Page 128
... PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ctio n w ith fin tio ith efin ed seg ...
Page 129
... VPC connection would only terminate the segment VPC-AIS cell and no further action would be taken at the F4 level. The table below summarizes the behavior of the ATLAS for Fault Management: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 121 ...
Page 130
... Segment RDI (4), (6) (4) Generate VC Generate VC Segment RDI End-to-End RDI (4) (4) (5) Generate VC Generate VC End-to-End AIS Segment RDI (4), (6) (4) PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION VC Non End-Point Within a VC Not within a Segment VC Segment Generate VC Generate VC Segment AIS End-to-End (3), (4) AIS (4) Generate VC Generate VC ...
Page 131
... connection enters the AIS alarm condition (segment or end-to-end), the associated F5 connections will not enter the AIS alarm condition (i.e. the AIS_end_to_end alarm and/or the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 123 ...
Page 132
... Segment F4 connection points to the End-to-End F4 OAM connection. Figure OAM Flows onnection PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION gress VC T able ...
Page 133
... F4 (VPC) End-to-End flow. F42: F4 (VPC) Segment flow. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE I era ted vaila -AIS -E tE PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 125 ...
Page 134
... AIS AIS AIS PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 126 ...
Page 135
... AIS AIS , PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION AIS , AIS , ...
Page 136
... AIS AIS , PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...
Page 137
... PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION AIS AIS , ...
Page 138
... RDI cells will be generated. This ensures that no RDI cells will be lost due to overflow of the Ingress Backward Cell Interface. If the FIFO is filled, this background process will be suspended. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 130 ...
Page 139
... PHY devices in case a catastrophic event occurs on a particular PHY device. In normal operating mode, this situation will never be encountered. The Head-of-Line Time Out can be disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 131 ...
Page 140
... The BUSYB output can be connected to a DMA request input of a DMA controller. The rising edge of BUSYB would initiate the next external SRAM access upon completion of the current access. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 132 ...
Page 141
... Write the cell contents to the Ingress/Egress Microprocessor Cell Interface Data register. Each subsequent write enters the next word in the cell. The words shall be written in the following order: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 133 ...
Page 142
... Last postpended word, N<6 (optional) ATM Header: GFC, VPI, VCI[15:12] ATM Header: VCI[11:0], PTI, CLP HEC and UDF fields st 1 ATM payload word nd 2 ATM payload word … ATM payload word PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 134 ...
Page 143
... Ingress/Egress MCIF and provides cell status information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 LEN[2:0] Buffer Capacity PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 135 ...
Page 144
... Indicates the connection is provisioned as an OAM flow segment end point. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Definition PHYID[4] PHYID[3] PHYID[2] PHYID[1] PHYID[0] PROV End_to_End_Point Segment_End_Point TimeOut NNI VPC OAM_Type TYP[3] TYP[2] TYP[1] TYP[0] PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 136 ...
Page 145
... User 0001 AIS 0010 RDI 0011 Continuity Check 0100 Loopback 0101 Forward Monitoring 0110 Backward Reporting 0111 Reserved 1000 Activate/Deactivate 1001 Undefined OAM 1010 System Management OAM 1011 Forward RM 1100 Backward RM 1101 Invalid PTI/VCI PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 137 ...
Page 146
... DLL’s in the ATLAS are operating correctly and have locked-on to the input clock frequency. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 1110 Reserved 1111 OAM cell with errored CRC-10 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 138 ...
Page 147
... INGRESS BACKWARD REPORTING OAM CELL INTERFACE CONFIGURATION #1 .................................................................................... 218 REGISTER 0X081: RESERVED.................................................................................................... 219 REGISTER 0X082: RESERVED.................................................................................................... 219 REGISTER 0X083: RESERVED.................................................................................................... 219 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 MASTER INTERRUPT STATUS #1.............................................................. 152 ...................................................................................................... 217 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 139 ...
Page 148
... INGRESS VC TABLE DATA ROW 2, WORD 0 (LSW) (RAM DATA [15:0]) .. 249 REGISTER 0X199: INGRESS VC TABLE DATA ROW 2, WORD 1 (RAM DATA [31:16])............ 249 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 ...................................................................................................... 220 ...................................................................................................... 248 ...................................................................................................... 249 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 140 ...
Page 149
... INGRESS VC TABLE DATA ROW 13 WORD 1 (RAM DATA [31:16])........... 252 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 ...................................................................................................... 249 ...................................................................................................... 249 ...................................................................................................... 250 ...................................................................................................... 250 ...................................................................................................... 250 ...................................................................................................... 250 ...................................................................................................... 251 ...................................................................................................... 252 ...................................................................................................... 252 ...................................................................................................... 252 ...................................................................................................... 252 ...................................................................................................... 252 ...................................................................................................... 252 ...................................................................................................... 252 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 141 ...
Page 150
... INGRESS OAM DEFECT TYPE 14 AND 15 .................................................. 294 REGISTER 0X22E: INGRESS OAM DEFECT LOCATION OCTETS 0 & 1................................... 295 REGISTER 0X22F: INGRESS DEFECT LOCATION OCTETS 2 & 3........................................... 296 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 ...................................................................................................... 252 ...................................................................................................... 253 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 142 ...
Page 151
... EGRESS CELL PROCESSOR OAM DEFECT LOCATION OCTET 10 & 11 REGISTER 0X2A0: EGRESS CELL PROCESSOR OAM DEFECT LOCATION OCTET 12 &13 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 ...................................................................................................... 305 ...................................................................................................... 306 ...................................................................................................... 331 ...................................................................................................... 347 ...................................................................................................... 347 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 143 ...
Page 152
... EGRESS PERFORMANCE MONITORING RAM DATA WORD 4 (MSW)..... 370 REGISTER 0X2D6: EGRESS VC TABLE CHANGE OF CONNECTION STATUS DATA (LSW) .. 371 REGISTER 0X2D7: EGRESS VC TABLE CHANGE OF CONNECTION STATUS DATA (MSW) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 ...................................................................................................... 347 ...................................................................................................... 372 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 144 ...
Page 153
... REGISTER 0X5F0-0X5FC: PHY32 INGRESS STATUS AND COUNTS.................................................. 391 REGISTER 0X600: EGRESS PER-PHY COUNTER CONFIGURATION ...................................... 392 REGISTER 0X601: PHY1 EGRESS COUNTER STATUS ............................................................ 394 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION ...... 379 145 ...
Page 154
... REGISTER 0X7D0-0X7D9: PHY30 EGRESS STATUS AND COUNTS................................................... 406 REGISTER 0X7E0-0X7E9: PHY31 EGRESS STATUS AND COUNTS ................................................... 406 REGISTER 0X7F0-0X7F9: PHY32 EGRESS STATUS AND COUNTS.................................................... 406 REGISTER 0X800: MASTER TEST .............................................................................................. 408 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 146 ...
Page 155
... To ensure that the S/UNI-ATLAS operates, as intended, reserved register bits must only be written with the value indicated. Similarly, writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 147 ...
Page 156
... The TYPE bits can be read to distinguish the S/UNI-ATLAS from the other members of the S/UNI-ATLAS family of devices. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default RESET 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X TYPE[2] 0 TYPE[1] 0 TYPE[0] 1 ID[3] Note 1 ID[2] Note 1 ID[1] Note 1 ID[0] Note 1 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 148 ...
Page 157
... A hardware reset clears the RESET bit, thus negating the software reset. Otherwise, the effect of the software reset is equivalent to that of the hardware reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 149 ...
Page 158
... S/UNI- ATLAS. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X BUSYPOL 0 DREQINV 0 SEL1SEC 0 CLKRATE[1] 0 CLKRATE[0] 0 ESTANDBY 1 ISTANDBY 1 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 150 ...
Page 159
... The BUSYPOL bit sets the polarity of the BUSYB primary output. If BUSYPOL is logic 0, the BUSYB primary output is active low. If BUSYPOL is logic 1, the BUSYB output is active high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Assumed ISYSCLK frequency 25 MHz 50 MHz 52 MHz Reserved PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 151 ...
Page 160
... This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default REG6I X REG5I X REG4I X REG3I X I_XFERI X I_XPOLI X I_POLI X I_END_RDII X I_SEG_RDII X I_END_AISI X I_SEG_AISI X I_END_CCI X I_SEG_CCI X I_OAMERRI X I_PTIVCII X I_INVALI X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 152 ...
Page 161
... When logic 1, the I_END_RDII bit indicates the End-to-End RDI Alarm bit in the Ingress VC Table has changed state for one or more virtual connections. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 153 ...
Page 162
... Status #4, is currently asserted. REG6I: The REG6I bit indicates that at least one bit in register 0x006, S/UNI-ATLAS Master Interrupt Status #5, is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 154 ...
Page 163
... Status register has been asserted. The I_UPCAI bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default REG6I X REG5I X REG4I X I_XCOSI X I_COSFULLI X I_PHYXPOLI X I_PHYPOLI X I_BCIFFULLI X I_SRCHERRI X I_PCELLI X I_RPRTYI X I_RSOCI X I_INSRDYI X I_UPCAI X I_UPFOVRI X I_FULLI X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 155 ...
Page 164
... When logic 1, the I_PHYPOLI bit indicates one or more cells have violated one or more of the 32 PHY policing instances. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 156 ...
Page 165
... Status #4 is currently asserted. REG6I: The REG6I bit indicates that at least one bit in Register 0x006, S/UNI-ATLAS Master Interrupt Status #5 is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 157 ...
Page 166
... All bits are cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default REG6I X REG5I X Unused X Unused X E_SPRTYI[3] X E_SPRTYI[2] X E_SPRTYI[1] X E_SPRTYI[0] X I_SPRTYI[7] X I_SPRTYI[6] X I_SPRTYI[5] X I_SPRTYI[4] X I_SPRTYI[3] X I_SPRTYI[2] X I_SPRTYI[1] X I_SPRTYI[0] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 158 ...
Page 167
... Status #4, is currently asserted. REG6I: The REG6I bit indicates that at least one bit in Register 0x006, S/UNI-ATLAS Master Interrupt Status #5, is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 159 ...
Page 168
... This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default REG6I X E_PCELLI X E_IOVRI X E_INSRDYI X E_UPCAI X E_UPFOVRI X E_FULLI X E_End_RDII X E_Seg_RDII X E_End_AISI X E_Seg_AISI X E_END_CCI X E_SEG_CCI X E_OAMERRI X E_PTIVCII X E_XFERI x PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 160 ...
Page 169
... When logic 1, the I_END_RDII bit indicates the End-to-End RDI Alarm bit in the Egress VC Table has changed state for one or more virtual connections. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 161 ...
Page 170
... This bit is cleared when this register is read. REG6I: The REG6I bit indicates that at least one bit in Register 0x006, S/UNI-ATLAS Master Interrupt Status #5, is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 162 ...
Page 171
... This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X E_SEARCHEI X E_XCOSI X E_COSFULLI X E_BCIFFULLI X E_IWRENBI X E_IPRTYI X E_ISOCI X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 163 ...
Page 172
... If the BADVCtoUP register bit is a logic 1, the cell associated with the failed search is routed to the Egress Microprocessor Cell Interface Extract FIFO. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 164 ...
Page 173
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X Unused X I_XFERE 0 I_XPOLE 0 I_POLE 0 I_END_RDIE 0 I_SEG_RDIE 0 I_END_AISE 0 I_SEG_AISE 0 I_END_CCE 0 I_SEG_CCE 0 I_OAMERRE 0 I_PTIVCIE 0 I_INVALE 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 165 ...
Page 174
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X I_XCOSE 0 I_COSFULLE 0 I_PHYXPOLE 0 I_PHYPOLE 0 I_BCIFFULLE 0 I_SRCHERRE 0 I_PCELLE 0 I_RPRTYE 0 I_RSOCE 0 I_INSRDYE 0 I_UPCAE 0 I_UPFOVRE 0 I_FULLE 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 166 ...
Page 175
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X Unused X E_SPRYTE[3] 0 E_SPRYTE[2] 0 E_SPRYTE[1] 0 E_SPRYTE[0] 0 I_SPRYTE[7] 0 I_SPRYTE[6] 0 I_SPRYTE[5] 0 I_SPRYTE[4] 0 I_SPRYTE[3] 0 I_SPRYTE[2] 0 I_SPRYTE[1] 0 I_SPRYTE[0] 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 167 ...
Page 176
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X E_PCELLE 0 E_IOVRE 0 E_INSRDYE 0 E_UPCAE 0 E_UPFOVRE 0 E_FULLE 0 E_END_RDIE 0 E_SEG_RDIE 0 E_END_AISE 0 E_SEG_AISE 0 E_END_CCE 0 E_SEG_CCE 0 E_OAMERRE 0 E_PTIVCIE 0 E_XFERE 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 168 ...
Page 177
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X E_SEARCHE 0 E_XCOSE 0 E_COSFULLE 0 E_BCIFFULLE 0 E_IWRENBE 0 E_IPRTYE 0 E_ISOCE 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 169 ...
Page 178
... RFCLKA is set high on a rising edge of RFCLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default DLLRUN X RSTDLL 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X TFCLKA X IFCLKA X ESYSCKLA X OFCLKA X RFCLKA X ISYSCLKA X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 170 ...
Page 179
... The Delay Locked Loop run register bit (DLLRUN). When logic 1, this bit indicates that all DLL components have locked to their input clocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 171 ...
Page 180
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default RHECUDF 1 RCAINV 0 RCELLPOST[3] 0 RCELLPOST[2] 0 RCELLPOST[1] 0 RCELLPOST[0] 0 RCELLLEN[3] 0 RCELLLEN[2] 0 RCELLLEN[1] 0 RCELLLEN[0] 0 Reserved 0 RPTYP 0 Reserved 0 Reserved 0 RCALEVEL0 1 RFIFORST 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 172 ...
Page 181
... RCA[4:1] signals become active low. If the state of the RCAINV bit has been changed, the Ingress Input Cell Interface must be reset via the FIFORST. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 173 ...
Page 182
... ATM cell is omitted and a 26-word cell (plus appended words) is transferred. If RBUS8 is logic 1, the fifth octet of the 53-octet ATM cell is omitted and a 52- octet cell (plus appended octets) is transferred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 174 ...
Page 183
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X RPICELL[7] X RPICELL[6] X RPICELL[5] X RPICELL[4] X RPICELL[3] X RPICELL[2] X RPICELL[1] X RPICELL[0] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 175 ...
Page 184
... Register 0x000. After a write to register 0x000, the Physical Layer Cell Counter register is loaded with the current count value and the counter is reset as described above. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 176 ...
Page 185
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default RCELL[15] X RCELL[14] X RCELL[13] X RCELL[12] X RCELL[11] X RCELL[10] X RCELL[9] X RCELL[8] X RCELL[7] X RCELL[6] X RCELL[5] X RCELL[4] X RCELL[3] X RCELL[2] X RCELL[1] X RCELL[0] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 177 ...
Page 186
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default RCELL[31] X RCELL[30] X RCELL[29] X RCELL[28] X RCELL[27] X RCELL[26] X RCELL[25] X RCELL[24] X RCELL[23] X RCELL[22] X RCELL[21] X RCELL[20] X RCELL[19] X RCELL[18] X RCELL[17] X RCELL[16] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 178 ...
Page 187
... S/UNI-ATLAS DATASHEET PMC-1971154 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 179 ...
Page 188
... Unused X Unused X Unused X Unused X RBUS8 0 Reserved 0 Unused X Reserved 0 RNNI 1 RPHYDEV[4] 0 RPHYDEV[3] 0 RPHYDEV[2] 0 RPHYDEV[1] 0 RPHYDEV[0] 0 Meaning Poll all 32 PHY devices Poll PHY#1 thru PHY#2 Poll PHY#1 thru PHY#3 Poll PHY#1 thru PHY#31 Poll all 32 PHY devices PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 180 ...
Page 189
... When RBUS8 is logic 0, an 18-bit interface consisting of a start of cell indication, 16-bit word bus and a parity bit is selected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 181 ...
Page 190
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default OHECUDF 1 OCAINV 0 OCELLPOST[3] 0 OCELLPOST[2] 0 OCELLPOST[1] 0 OCELLPOST[0] 0 OCELLLEN[3] 0 OCELLLEN[2] 0 OCELLLEN[1] 0 OCELLLEN[0] 0 Reserved 0 OPTYP 0 Reserved 0 Reserved 0 OCALEVEL0 1 OFIFORST 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 182 ...
Page 191
... ATM cell is omitted and a 26-word cell (plus appended words) is transferred. If OBUS8 is logic 1, the fifth octet of the 53-octet ATM cell is omitted and a 52- octet cell (plus appended octets) is transferred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 183 ...
Page 192
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default OCELL[15] X OCELL[14] X OCELL[13] X OCELL[12] X OCELL[11] X OCELL[10] X OCELL[9] X OCELL[8] X OCELL[7] X OCELL[6] X OCELL[5] X OCELL[4] X OCELL[3] X OCELL[2] X OCELL[1] X OCELL[0] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 184 ...
Page 193
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default OCELL[31] X OCELL[30] X OCELL[29] X OCELL[28] X OCELL[27] X OCELL[26] X OCELL[25] X OCELL[24] X OCELL[23] X OCELL[22] X OCELL[21] X OCELL[20] X OCELL[19] X OCELL[18] X OCELL[17] X OCELL[16] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 185 ...
Page 194
... S/UNI-ATLAS DATASHEET PMC-1971154 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 186 ...
Page 195
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OBUS8 0 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 187 ...
Page 196
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default IHECUDF 1 ICAINV 0 ICELLPOST[3] 0 ICELLPOST[2] 0 ICELLPOST[1] 0 ICELLPOST[0] 0 ICELLLEN[3] 0 ICELLLEN[2] 0 ICELLLEN[1] 0 ICELLLEN[0] 0 Reserved 0 IPTYP 0 IFIFODP[1] 0 IFIFODP[0] 0 Reserved 0 IFIFORST 0 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 188 ...
Page 197
... ICA[4:1] signals become active low. If the state of the ICAINV bit has been changed, the Egress Input Cell Interface must be reset via the IFIFORST. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 IFIFODP[1] IFIFODP[0] APPARENT DEPTH PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 4 cells 3 cells 2 cells 1 cell 189 ...
Page 198
... ATM cell is omitted and a 26-word cell (plus appended words) is transferred. If IBUS8 is logic 1, the fifth octet of the 53-octet ATM cell is omitted and a 52-octet cell (plus appended octets) is transferred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 190 ...
Page 199
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default ICELL[15] X ICELL[14] X ICELL[13] X ICELL[12] X ICELL[11] X ICELL[10] X ICELL[9] X ICELL[8] X ICELL[7] X ICELL[6] X ICELL[5] X ICELL[4] X ICELL[3] X ICELL[2] X ICELL[1] X ICELL[0] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION 191 ...
Page 200
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 7 Function Default ICELL[31] X ICELL[30] X ICELL[29] X ICELL[28] X ICELL[27] X ICELL[26] X ICELL[25] X ICELL[24] X ICELL[23] X ICELL[22] X ICELL[21] X ICELL[20] X ICELL[19] X ICELL[18] X ICELL[17] X ICELL[16] X PM7324 S/UNI-ATLAS S/UNI-ATM LAYER SOLUTION the 192 ...