M5M4V16G50DFP-10 MITSUBISHI, M5M4V16G50DFP-10 Datasheet
M5M4V16G50DFP-10
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M5M4V16G50DFP-10 Summary of contents
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... Some of contents are described for general products and are subject to change without notice. DESCRIPTION The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz. The BLOCK WRITE and WRITE-PER-BIT functions provide improved performance in graphic memory systems ...
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... DSF A0-10 A0-9 A0-7 A10 DQ0-31 DQM0-3 Vdd VddQ Vss VssQ M5M4V16G50DFP -8, -10, -12 100 Pin QFP 14.0 x 20.0 mm2 0.65 mm pitch : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Special Function Enable : Address Input : Row Address inputs : Column Address inputs ...
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... Synchronous Graphics RAM BLOCK DIAGRAM DQM0-3 Memory Array Bank #0 Mode Register Address Buffer A0-9 A10 Type Designation Code M5M4V16G50DFP -8, -10, -12 DQ0-31 I/O Buffer Memory Array Bank #1 Control Circuitry Control Signal Buffer Clock Buffer /CS /RAS /CAS CLK CKE This rule is applied only to Synchronous DRAM family ...
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... Power Supply VddQ, VssQ Power Supply M5M4V16G50DFP -8, -10, -12 Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is stopped. CKE is also used to select auto / self refresh ...
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... Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM BASIC FUNCTIONS The M5M4V16G50DFP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS, /WE, and DSF at CLK rising edge. In addition to 3 signals, /CS ,CKE and A9 are used as chip select, refresh option, and precharge option, respectively ...
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... BW command starts the 8 column Block Write function. Burst Length = 1 is assumed. Write data comes from the color register and column address mask data is applied on the DQs. When this command, the bank is deactivated after the burst write (auto-precharge, BWA). M5M4V16G50DFP -8, -10, -12 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... Self-Refresh Exit REFSX Burst Terminate TERM Mode Register Set MRS Special Register Set SRS H=High Level, L=Low Level, BA=Bank Address, Col.=Column Address (A0-A7) Row Add.=Row Address (A0-A9), X=Don't Care, n=CLK cycle number M5M4V16G50DFP -8, -10, -12 CKE CKE /CS /RAS /CAS /WE n ...
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... M5M4V16G50DFP -8, -10, -12 Address Command DSF X X DESEL NOP H X Undefined TERM Undefined H H BA, CA READ / READA BA, CA, A9 WRITE / WRITEA L L BA, CA, A9 ...
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... M5M4V16G50DFP -8, -10, -12 Address Command DSF X DESEL NOP TERM BA, CA, A9 READ / READA H WRITE / BA, CA WRITEA BA, CA BWA L BA, RA ACT L H BA, RA ...
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... PRECHARGE M5M4V16G50DFP -8, -10, -12 DSF Address Command DESEL NOP TERM L H BA, CA, A9 READ / READA ILLEGAL WRITE / L L BA, CA, A9 WRITEA BW / BWA L H BA, CA BA, RA ...
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... M5M4V16G50DFP -8, -10, -12 Address Command DSF DESEL NOP L BA TERM L H BA, CA, A9 READ / READA ILLEGAL BA, CA, A9 WRITE / WRITEA L L BA, CA BWA H H BA, RA ...
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... M5M4V16G50DFP -8, -10, -12 Address Command DSF X X DESEL NOP TERM H L BA, CA, A9 READ / READA ILLEGAL*2 L BA, CA WRITE / WRITEA L H BA, CA BWA H BA, RA ...
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... Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. M5M4V16G50DFP -8, -10, -12 DSF Address Command X ...
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... CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. M5M4V16G50DFP -8, -10, -12 DSF /CS /RAS /CAS /WE ...
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... Operating Mode A10 Normal Operation Burst Read and Single Write All Others are Reserved - - - - M5M4V16G50DFP -8, -10, - LTMODE BT BL LVTTL Reserved Reserved 2 3 Reserved Reserved Reserved Reserved BURST TYPE MITSUBISHI ELECTRIC MITSUBISHI LSIs CLK ...
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... The Mask Register and Color Register can be loaded by setting the special register (SRS and MR are both high, data in the Mask and Color Registers will be unknown.After tRSC from a SRS command, the SGRAM is ready for new command A10 M5M4V16G50DFP -8, -10, - Operation ...
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... NOTE: FULL PAGE BURST is an extension of the above tables of Sequential Addressing with the length being 256. M5M4V16G50DFP -8, -10, - Burst Length Burst Type Column Addressing Sequential ...
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... Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited until the internal precharge is complete. The internal precharge start timing depends on /CAS Latency. The next ACT command can be issued after tRP from the internal precharge timing. M5M4V16G50DFP -8, -10, -12 ACT READ ...
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... A9 Xa A10 0 DQ READ with Auto-Precharge (BL=4, CL=3) CLK Command ACT tRCD A0 A10 0 DQ READ Auto-Precharge Timing (BL=4) CLK Command ACT CL=3 DQ CL=2 DQ M5M4V16G50DFP -8, -10, -12 READ ACT READ PRE Qa0 Qa1 Qa2 /CAS latency Burst Length READ Qa0 ...
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... Dual Bank Interleaving WRITE (BL=4) CLK Command ACT A0 A10 0 DQ WRITE with Auto-Precharge (BL=4) CLK Command ACT A0 A10 0 DQ M5M4V16G50DFP -8, -10, -12 Write ACT tRCD tRCD Da0 Da1 Da2 Da3 Burst Length Write tRCD tWR Da0 ...
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... SGRAM (Rev. 0.0) Jan'97 Preliminary 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of the same or the other bank. M5M4V16G50DFP allows random column access. READ to READ interval is minimum 1 CLK. CLK Command READ ...
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... Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is mini- mum 1 CLK. A PRE command disables the data output depending on the /CAS Latency. The figure below shows examples of when the dataout is terminated. Command Command CL=3 Command Command Command CL=2 Command M5M4V16G50DFP -8, -10, -12 Read Interrupted by Precharge (BL=4) CLK READ DQ Q0 READ PRE DQ Q0 READ ...
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... READ to TERM interval is minimum 1 CLK. The figure below shows examples when the dataout is terminated. CLK Command DQ Command CL=3 DQ Command DQ Command DQ Command CL=2 DQ Command DQ M5M4V16G50DFP -8, -10, -12 Read Interrupted by Burst Terminate (BL=4) READ TERM Q0 Q1 READ TERM Q0 Q1 READ TERM Q0 READ TERM READ ...
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... WRITE to READ interval is minimum 1 CLK. The input data the interrupting READ cycle is “don’t care”. Write Interrupted by Read (BL=4, CL=3) CLK Command Write READ A0 A10 0 0 DQM0-3 DQ Dai0 M5M4V16G50DFP -8, -10, -12 Write Write Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Write Qaj0 Qaj1 ...
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... The figure below shows the case that 3 words of data are written. Random column access is allowed. WRITE to TERM interval is minimum 1 CLK. Write Interrupted by Burst Terminate (BL=4) CLK Command Write A0 A10 0 DQM0-3 DQ Dai0 Dai1 M5M4V16G50DFP -8, -10, -12 PRE ACT tRP tWR TERM Dai2 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... Additional commands must not be supplied to the device before tRC from the REFA command. Auto-Refresh CLK /CS /RAS /CAS /WE DSF CKE A0-9 A10 Auto Refresh on Bank 0 M5M4V16G50DFP -8, -10, -12 NOP or DESLECT minimum tRC MITSUBISHI ELECTRIC MITSUBISHI LSIs Auto Refresh on Bank 1 ...
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... CKE (REFSX). After tRC from REFSX both banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted until then. Self-Refresh CLK /CS /RAS /CAS /WE DSF CKE A0-9 A10 Self Refresh Entry M5M4V16G50DFP -8, -10, -12 Stable CLK Self Refresh Exit MITSUBISHI ELECTRIC MITSUBISHI LSIs NOP new command X 0 minimum tRC for recovery ...
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... CLK CKE Command PRE CKE Command ACT CLK CKE Command Write M5M4V16G50DFP -8, -10, -12 Power Down by CKE Standby Power Down NOP NOP NOP NOP NOP Active Power Down NOP NOP NOP NOP NOP DQ Suspend by CKE READ D2 D3 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... DQM0 masks DQ0-7, DQM1 masks DQ8-15, DQM2 masks DQ16-23, DQM3 masks DQ24-031. CLK Command Write DQM0 DQ(0-7) D0 masked by DQM0=High DQM1 DQ(8-15 masked by DQM1=High DQM2 DQ(16-23 masked by DQM2=High DQM3 D0 D1 DQ(24-31) M5M4V16G50DFP -8, -10, -12 DQM0 - 3 Function READ disabled by DQM1=High masked by DQM3=High disabled by DQM3=High MITSUBISHI ELECTRIC MITSUBISHI LSIs disabled by DQM0=High ...
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... Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Symbol CI(A) Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin M5M4V16G50DFP -8, -10, -12 Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ °C Parameter Min. 3 ...
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... Parameter VOH (DC) High-Level Output Voltage (DC) VOL (DC) Low-Level Output Voltage (DC) IOZ Off-state Output Current I Input Current I M5M4V16G50DFP -8, -10, -12 Test Conditions tRC=min, tCLK=min, BL=1, CL=3 both banks idle, tCLK=min, CKE=H both banks idle, tCLK=min, CKE=L both banks active, tCLK=min, CKE=H tCLK=min, BL=4, CL=3, 1 bank idle tRC=min, tCLK=min CKE < ...
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... Write Recovery time tRRD Act to Act Delay time Mode Register Set tRSC Cycle time tPDE Power Down Exit time tREF Refresh Interval time tBWC Block Write Cycle time tBPL Block Write to Precharge CLK Signal M5M4V16G50DFP -8, -10, -12 0.8V to 2.0V Limits -8 Min. Max. Min ...
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... Output Hold time from tOH CLK Delay time, output low tOLZ impedance from CLK Delay time, output high tOHZ impedance from CLK Output Load Condition V TT 50* V OUT 50pF CLK DQ M5M4V16G50DFP -8, -10, -12 -8 Min. Max. Min. CL =1.4V CLK V =1.4V REF ...