M2V56S20AKT-6 MITSUBISHI, M2V56S20AKT-6 Datasheet
M2V56S20AKT-6
Related parts for M2V56S20AKT-6
M2V56S20AKT-6 Summary of contents
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... Single Data Rate July '01 Some of contents are subject to change without notice. DESCRIPTION M2V56S20AKT is a 4-bank x 16777216-word x 4-bit, M2V56S30AKT is a 4-bank x 8388608-word x 8-bit, M2V56S40AKT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK ...
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... Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM VSS VSS VSS 64 DQ15 VSSQ VSSQ VSSQ 62 ...
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... Process Generation Function Reserved for Future Use Organization x4, 3: x8, 4: x16 SDRAM Data Rate Type S:Single Data Rate Density 56: 256M bits Interface V:LVTTL Memory Style (DRAM) Mitsubishi Main Designation MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Memory Array Bank #3 6: 133MHz@CL3, 100MHz@CL2 7: 100MHz@CL2 A:2nd ...
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... When DQMU/L is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only. MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM 4 ...
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... REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically. M2V56S20/ 30/ 40 AKT -5, -6, -7 Chip Select : L=select, H=deselect Command Command define basic commands Command Refresh Option @refresh command Precharge Option @precharge or read/write command MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM 5 ...
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... MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM A10 A0-9, /WE BA0,1 /AP 11- ...
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... BA, CA, A10 L L BA, CA, A10 BA, A10 Op-Code Mode-Add MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Command Action DESEL NOP NOP NOP TBST ILLEGAL*2 READ / WRITE ILLEGAL*2 ACT Bank Active, Latch RA PRE / PREA NOP*4 REFA Auto-Refresh*5 MRS ...
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... BA BA, A10 PRE / PREA Op-Code Mode-Add MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Command Action DESEL NOP (Continue Burst to END) NOP NOP (Continue Burst to END) TBST Terminate Burst Terminate Burst, Latch CA, Begin Read, Determine Auto- Precharge*3 Terminate Burst, Latch CA, ...
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... READ / WRITE ILLEGAL BA BA, A10 Op-Code Mode-Add MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Command Action DESEL NOP (Idle after tRP) NOP NOP (Idle after tRP) TBST ILLEGAL*2 ACT ILLEGAL*2 PRE / PREA NOP*4 (Idle after tRP) REFA ...
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... READ / WRITE ILLEGAL BA, A10 PRE / PREA Op-Code Mode-Add MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Command Action DESEL NOP (Idle after tRC) NOP NOP (Idle after tRC) TBST ILLEGAL ACT ILLEGAL ILLEGAL REFA ILLEGAL MRS ILLEGAL ...
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... MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Add Action X INVALID X Exit Self-Refresh (Idle after tRC) X Exit Self-Refresh (Idle after tRC) X ILLEGAL X ILLEGAL X ILLEGAL X NOP (Maintain Self-Refresh) X INVALID X Exit Power Down to Idle ...
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... TBST WRITE WRITEA READA READ WRITE WRITE WRITEA WRITEA READA PRE WRITEA PRE PRE PRE PRE CHARGE ON MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM SELF REFRESH REFSX REFA AUTO REFRESH CKEL POWER DOWN TBST READ CKEL READ READ SUSPEND CKEH READA ...
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... M2V56S20/ 30/ 40 AKT -5, - LTMODE 0 Burst Write 1 Single Write MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM CLK /CS /RAS /CAS /WE BA0,1 A12- BT BURST ...
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... MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Write Burst Length Burst Type Interleaved ...
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... BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met. M2V56S20/ 30/ 40 AKT -5, -6, -7 ACT READ tRCD Qb0 MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM PRE ACT tRP Qb1 Qb2 Qb3 Precharge All 15 ...
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... Qa0 Qa1 Qa2 Qa0 Qa1 Qa2 i nternal precharge starts BL Qa0 Qa1 Qa2 Qa0 Qa1 i nternal precharge starts MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM PRE ACT tRP Qa3 Qb0 Qb1 Qb2 ACT tRP Qa3 ...
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... M2V56S20/ 30/ 40 AKT -5, -6, -7 Write (BL=4) Write Da0 Da1 Da2 Da3 Write with Auto-Precharge (BL=4) Write Da0 Da1 Da2 Da3 internal precharge starts MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM PRE ACT tRP tWR ACT tRP tWR 17 ...
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... ACT A0-9,11-12 Xa A10 Xa BA0-1 00 DQM DQ M2V56S20/ 30/ 40 AKT -5, -6, -7 READ READ Qa0 Qa1 Qa2 READ Write Qa0 Output disable by DQM by WRITE MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Qb0 Qc0 Qc1 Qc2 Qc3 Da0 Da1 Da2 Da3 18 ...
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... A PRE command to output disable latency is equivalent to the /CAS Latency. CLK Command DQ Command CL=2 DQ Command DQ Command DQ Command CL=3 DQ Command DQ M2V56S20/ 30/ 40 AKT -5, -6, -7 Read interrupted by Precharge (BL=4) READ PRE Q0 Q1 READ PRE Q0 Q1 READ PRE Q0 READ PRE Q0 READ PRE Q0 READ PRE Q0 MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM ...
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... CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. CLK Command DQ Command CL=2 DQ Command DQ Command DQ Command CL=3 DQ Command DQ M2V56S20/ 30/ 40 AKT -5, -6, -7 Read interrupted by Terminate (BL=4) READ TBST Q0 Q1 READ TBST Q0 Q1 READ TBST Q0 READ TBST Q0 READ TBST Q0 READ TBST Q0 MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM ...
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... BA0 M2V56S20/ 30/ 40 AKT -5, -6, -7 Write Write Da1 Da2 Db0 Dc0 Write interrupted by Read (CL=2, BL=4) Write READ Da0 Da1 don't care MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Dc1 Dc2 Dc3 Qb0 Qb1 Qb2 Qb3 21 ...
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... Write interrupted by Terminate (BL=4) CLK Command ACT A0-9,11-12 Xa A10 0 BA0 M2V56S20/ 30/ 40 AKT -5, -6, -7 Write PRE tWR Da0 Da1 Write TBST Write Da0 Da1 MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM ACT tRP Db0 Db1 Db2 Db3 22 ...
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... Da0 auto-precharge M2V56S20/ 30/ 40 AKT -5, -6, -7 Write Da1 Db0 Db1 Db2 Db3 interrupted Read Da1 Qb0 Qb1 interrupted MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM ACT tRP activate ACT tRP Qb2 Qb3 activate 23 ...
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... Single Write When sigle write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0). M2V56S20/ 30/ 40 AKT -5, -6, -7 Read BL tRP Qa0 Qa1 Qb0 Qb1 interrupted MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM ACT Qb2 Qb3 activate 24 ...
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... Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command. CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 Auto Refresh on All Banks M2V56S20/ 30/ 40 AKT -5, -6, -7 Auto-Refresh NOP or DESELECT minimum tRFC Auto Refresh on All Banks MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM 25 ...
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... DESEL or NOP commands must be asserted till then. CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 Self Refresh Entry M2V56S20/ 30/ 40 AKT -5, -6, -7 Self-Refresh Stable CLK Self Refresh Exit MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM NOP new command X 00 minimum tRFC for recovery 26 ...
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... CLK CKE Command Write D0 DQ M2V56S20/ 30/ 40 AKT -5, -6, -7 tIH tIS tIH tIS Power Down by CKE NOP NOP NOP NOP NOP NOP DQ Suspend by CKE MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Standby Power Down Active Power Down Read ...
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... During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0. During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2. CLK Command Write DQMU masked by DQMU/L=H M2V56S20/ 30/ 40 AKT -5, -6, -7 DQM Function Read D2 D3 MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM disabled by DQMU/L=H 28 ...
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... VssQ Input Voltage with respect to Vss Output Voltage with respect to VssQ Output Current Power Dissipation Ta=25'C Parameter Supply Voltage Supply Voltage Parameter Test Condition VI=25mVrms MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ Vdd+0.5 -0.5 ~ VddQ+0.5 50 1000 0~ 70 -65 ~ 150 Limits Min. Typ. Max. ...
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... CKE>VIHmin, /CS> VIHmin tCLK=L, CKE>VIHmin tCLK=min, BL=4, gapless data tCLK=min, tRFC=min CKE<0.2v -5 /-6/-7 Test Conditions IOH=-2mA IOL= 2mA Q floating Vo=0 ~ VddQ VIH=0 ~ VddQ+0.3V, other input pins=0V MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Limits(max) Organi Unit zation - 110 ...
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... Average Refresh Interval CLK Signal M2V56S20/ 30/ 40 AKT -5, -6, -7 0.8V to 2.0V 1.4V -5 Min. Max. Min. CL=2 7.5 CL=3 6 2.5 2 1.5 0 120000 7.8 1.4V 1.4V MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Limits -6 -7 Max. Min. Max 7.5 10 2 1 120000 50 120000 20 ...
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... Note (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters. Output Load Condition Vout CLK DQ tOLZ tAC M2V56S20/ 30/ 40 AKT -5, - Min. CL=2 CL=3 CL CL=2 3 CL=3 3 50pF 1.4V 1.4V tOHZ tOH MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Limits -6 -7 Max Min. Max Min. Max 5.4 6 5 5.4 3 5.4 ...
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... DQ D0 ACT#0 WRITE#0 M2V56S20/ 30/ 40 AKT -5, - tRC tRP tRAS tWR PRE#0 ACT #0 WRITE#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tRCD tWR ...
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... PRE#0 ACT #0 WRITEA#1 (Auto-Precharge) Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tRCD tWR WRITE#0 ...
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... DQ ACT#0 READ#0 M2V56S20/ 30/ 40 AKT -5, - tRC tRP tRCD PRE#0 ACT #0 READ#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tRAS PRE#0 35 ...
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... ACT #0 READ#0 READA#1 Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tRAS PRE#0 ACT #1 36 ...
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... WRITE#0 WRITEA #1 interrupt interrupt same other bank bank Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tWR WRITE#0 PRE#0 interrupt other ...
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... READ#1 READA#1 interrupt interrupt interrupt other same bank other bank bank Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM READ#0 ACT # ...
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... ACT#0 WRITE#0 ACT#1 M2V56S20/ 30/ 40 AKT -5, - tRCD READ#1 Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tWR WRITE#1 PRE ...
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... WRITE#0 M2V56S20/ 30/ 40 AKT -5, - tRP tRCD tWR ACT#0 PRE#0 Terminate Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tRC tRAS tRP READ#0 PRE#0 ...
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... ACT#0 WRITE#0 M2V56S20/ 30/ 40 AKT -5, - READ#0 TBST TBST Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tWR WRITE#0 PRE ...
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... CKE DQM A0-9, A10 X A12 X BA0 ACT#0 WRITE#0 READ#0 M2V56S20/ 30/ 40 AKT -5, - Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM ...
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... CKE DQM A0-9,11 A10 A12 BA0,1 DQ NOP Power On PRE ALL M2V56S20/ 30/ 40 AKT -5, -6, -7 tRFC REFA REFA REFA Minimum 8 REFA cycles Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tRFC tRSC MRS ACT #0 43 ...
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... All banks must be idle before REFA is issued. M2V56S20/ 30/ 40 AKT -5, - tRFC tRCD ACT#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM WRITE#0 44 ...
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... PRE ALL Self Refresh Entry All banks must be idle before REFS is issued. M2V56S20/ 30/ 40 AKT -5, - Self Refresh Exit Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM tRFC ACT#0 ...
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... A12 X BA0 ACT#0 WRITE#0 M2V56S20/ 30/ 40 AKT -5, - internal READ#0 CLK suspended Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM internal CLK suspended 46 ...
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... CKE DQM A0-9,11 A10 A12 BA0,1 DQ PRE ALL M2V56S20/ 30/ 40 AKT -5, - Standby Power Down ACT #0 Italic paramater shows minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM Active Power Down 47 ...
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... Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customerÕs application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party ...
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... SDRAM (Rev.1.01) Single Data Rate July '01 Revison History Rev. Date Description 1.01 July / '01 1st edition M2V56S20/ 30/ 40 AKT -5, -6, -7 MITSUBISHI ELECTRIC MITSUBISHI LSIs 256M Synchronous DRAM 49 ...