M37640E8FP MITSUBISHI, M37640E8FP Datasheet

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... Power-saving modes ..... WIT (Idle), STP (Clocks halt) 1.3 APPLICATIONS Cameras, games, musical instruments, modems ) = 24 MHz in scanners, and PC peripherals MHz M37640E8FP M37640M8-XXXFP Package outline: 80P6N-A 7640 Group = 4.15~5.25V ...

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... Ver 1.4 1.4 FUNCTIONAL BLOCK DIAGRAM Fig. 1.2. Functional Block Diagram 2 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ...

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... CMOS I/O port or HOLD pin I/O CMOS I/O port MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION out pin. output to master CPU for data bus buffer 0. 0 output to master CPU for data bus buffer 0. 0 input from master CPU for data bus buffer 0. ...

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... Vss to ensure proper operation of the USB line driver. The voltage converter is enabled by setting bit 4 of the USB control register (0013 4 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION output to master CPU for data bus buffer 1, or HLDA pin. ...

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... M37640M8-XXXFP M 37640E8FP M37640E8FS MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Package Type: ROM Number ROM capacity: Memory type: 7640 Group 7600 Series M37640E8FP One-time PROM version ROM RAM Package capacity capacity type 32K bytes 1 K bytes 80P6N-A 32K bytes 1 K bytes 80P6N-A ...

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... Program Counter (PC Fig. 1.4. Register Structure 6 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1.9.1 Register Structure Five of the CPU registers are 8-bit registers. These are the Accumulator (A), Index register X (X), Index Regis- ter Y (Y), Stack pointer (S), and the Processor Status register (PS) as shown in Figure 1.4. ...

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... CPMA7 CPMA6 CPMA5 CPMA4 7 Fig. 1.5. CPU Mode Register A (CPMA) MSB ved CPMB5 CPMB4 7 Fig.1.6. CPU Mode Register B (CPMB) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0000 Access: R CPMA2 CPMA1 CPMA0 0 Reset: OC CPMA0,1 ...

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... MCU is in memory expansion or microprocessor mode. 0000 16 The area from 8000 006F 16 0070 FFFF are factory reserved areas. Mitsubishi uses for test and evaluation purposes. The user can not 00FF 16 use this area in single-chip or memory expansion 0100 16 modes. ...

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... FFFB FFFC Reserved Area FFFF Fig. 1.8. Operation Modes Memory Maps MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER set. After the reset sequence has completed, the mode can be changed with software by modifying the value of bits 0 and 1 of CPMA. However, while CNVss is high, bit 1 of CPMA is “1” and cannot be changed. ...

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... CPMB. The wait function is disabled for internal memory and is valid only for memory expansion and microprocessor modes. 10 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Software wait is used to extend the read/write cycle by one, two, or three cycles of F. The cycle number is determined by the value of bits 0 and 1 of CPMB ...

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out AD out DB in/out Out RDY No Wait One Time S/W Wait CPMB = 01 CPMB = out AD out DB In in/out RD WR ...

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out AD out DB in/out In Out RDY One Time Fixed Wait No Wait CPMB = 09 CPMB = out AD out ...

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out AD out DB in/out In In Out ///////// ///////// RDY One Time Extended RDY Wait No Wait CPMB = 0D CPMB = ...

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... HOLD HLDA Fig. 1.12. Hold Function Timing Diagram 14 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1.12.6 Expanded Data Memory Access The Expanded Data Memory Access (EDMA) mode feature allows the user to access a greater than 64 Kbyte data area for instructions LDA (IndY) with T=“0” ...

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... EDMA [LDA ($zz), “1”)] Instruction Sequence (EDMA) SYNC out Address Data B1 EDMA Fig. 1.14. Instruction sequences for LDA ($zz) IndY with EDMA Enable MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PC +1 BAL, 00 BAL+1, 00 ADL+Y,ADH BAL Invalid ADH ADL ADL+Y, BAL, 00 BAL+1, 00 ...

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... UART1 Transmit/Receiver Buffer 1 U1TRB1=XX 16 0035 UART1 Transmit/Receiver Buffer 2 U1TRB2=XX 16 0036 UART1 RTS Control Register U1RTSC=80 16 0037 Reserved 16 16 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Acronym and Addr Description 0038 UART2 Mode Register 16 0039 UART2 Baud Rate Generator 16 003A UART2 Status Register 16 003B ...

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... Input/output, Port 8 individual bits MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O Non-Port Related Format Function SFR’s CMOS I/O CPU Mode Register Address Bus port CMOS I/O Address Bus CPU Mode Register port CMOS I/O Data Bus CPU Mode Register ...

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... Direction Register D ata Bus Key-on Wake up Input Fig. 1.15. Ports P0, P1, P2, P3 Block Diagram 18 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Most of the I/O Ports are multiplexed with secondary functions. When a GPI/O is multiplexed with a sec- ond function, the control signal from the peripheral overrides the direction register. The multiplexing is briefly described below ...

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... EDMA Signal Port P4 and Direction Register Data Bus Port Latch Interrupt Input Fig. 1.16. Port P4 Block Diagram MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port These pins are multiplexed with Timer X and Y func- tions for P4 and P4 respectively. The timer ...

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... Data Bus Port Latch OBF 0 Fig. 1.17. Port P5 Block Diagram 20 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ing used as a system clock or XC abled, the pin can be configured as the Timer 1/2 pulse output pin. This feature is configured in the Timer123 mode register as described in section 1.17. Port P5 ...

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... Port P6 MBI Write MBI Read Direction Register Data Bus Fig. 1.18. Port P6 Block Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port Latch Output Buffer Status Register 0 Output Buffer Status Register 1 Input Buffer 0 ...

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... Data Bus Port Latch S 1 Fig. 1.19. Port P7 Block Diagram 22 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P7 3 This pin is multiplexed with the IBF signal for a Master CPU and the HLDA function. When DBBC11 and DBBC17 are “1”, the pin takes on ...

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... Block Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 2 of the SIO control register 1 (SIOCON1 “1”, the port acts as the SIO SCLK signal. In this mode a “1” in bit 6 of SIOCON1 configures the pin to output SCLK whereas a “0” configures the pin to input SCLK. ...

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... P8 and P8 Block Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P8 6 This pin is multiplexed with the UART1 CTS signal. When bit 5 of the UART1 control register (U1CON “1”, the port acts as the CTS input signal. Port P8 7 This pin is multiplexed with the UART1 RTS signal ...

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... Fig. 1.23. Pull-up Control Register (PUP2) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1.14.3 Port P2 Pull-up Control Register (PUP2) This device is equipped with internal pull ups on Port P2 that can be enabled by software. Each bit of the pull-up control register controls a corresponding pin of Port P2. The pull-up control register pulls up the port when the port is in input mode ...

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... SIO FFD3 24 IBF FFD1 25 OBE FFCF 26 KEY FFCD 27 BRK FFCB 26 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 1.6. Interrupt Registers Address 0002 Interrupt request register A 16 0003 Interrupt request register B 16 0004 Interrupt request register C 16 0005 Interrupt control register A 16 0006 ...

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... IRC5 IRC4 IRC3 Fig. 1.26. Interrupt Request Register C (IREQC) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER mines whether the interrupt request bit it is paired with is seen when the interrupts are polled. When the inter- rupt enable bit is a “0”, the interrupt request bit is not seen ...

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... Fig. 1.29. Interrupt Control Register C (ICONC) The interrupt polarity register allows the user to se- lect the edge that will trigger an external interrupt MSB Reserved Reserved Reserved Reserved Reserved 7 Fig. 1.30. Interrupt Polarity Register (IPOL) 28 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0005 LSB 16 ICA2 ICA1 ICA0 Access: R/W 0 ...

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... Off Chip On Chip Fig. 1.31. Port P2 with Key-on Wake up function MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER by applying low level to any pin of Port P2 key matrix is connected as shown in Figure 1.31, the mi- crocomputer can be returned to a normal state by pressing any one of the keys. Key-on wake up is en- abled in single-chip mode only ...

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... T123M6= 1 T123M5 1 Fig. 1.32. Block diagram of Timers and 3 30 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER an underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to that timer is set to a “ ...

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... Timer X Data Write Control Bit (TXM0) (bit 0) is “0”, the value in the Timer X reload latch is also loaded in Timer X. If TXM0 is “0”, the data in the Timer X reload latch is loaded in Timer X after Timer X underflows. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0027 ...

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... The edge used to clock Timer X is determined by the CNTR0 polarity select bit (bit 6). 32 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER • Pulse Width Measurement Mode ...

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... Timer Y Data Write Control Bit (TYM0) (bit 0) is low, the value in the Timer Y reload latch is also loaded in Timer Y. If TYM0 is “1”, the data in the Timer Y reload latch is loaded in Timer Y after Timer Y underflows. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0028 ...

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... MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER •Event Counter Mode Count Source: CNTR1 Timer countdown is triggered by input to the CNTR1 pin. Each time a timer underflows, the correspond- ing timer interrupt request bit is set to a “ ...

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... In Timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a “1”, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0029 ...

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... When this bit is “0”, the output starts from a high level. When this bit is “1”, the out- put starts from a low level. 36 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1.17.5 Timer 3 Timer 8-bit timer with an 8-bit reload latch (see Figure 1 ...

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... Slave Selected SPI Slave Fig. 1.36. Clock Synchronous SIO Block Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER • External Clock (When SIO synchronous clock select bit is “1”, an external clock input from the SCLK pin is selected). •An SPI compatible mode in which the TxD and RxD pins function as MOSI and MISO pins, respectively. • ...

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... CPha CPol 7 Fig. 1.38. SIO Control Register 2 (SIOCON2) 38 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SIO Control Register 2 determines the transfer clock phase and polarity, and also whether the SIO is to function in SPI compatible mode (see Figure 1.38). All of this register’s bits can be read from and written to by software ...

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... When the internal clock is selected, the TxD pin goes into high- impedance after the data is transferred. Fig. 1.39. Normal Mode SIO Function Timing (with LSB-First selected) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER lected, the STXD pin enters a high-impedance state after an 8-bit transfer is completed external ...

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... First bit TxD/RxD Fig. 1.40. SPI Compatible Transmission Formats 40 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1.18.3.1 SPI Slave Mode When configured as an SPI slave the SIO does not initiate any serial transfers. All transfers are initiated by an external SPI bus master. When the CPha (bit 4 in SIOCON2) is “ ...

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... SCSGCLK Clock Set Prescaler /1/8/32/256 Fig. 1.41. UART Block Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The following descriptions apply to both UARTs. The UART receives parallel data from the core or DMAC, converts it into serial data, and transmits the results to the send data output terminal UTXDx. The ...

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... CTS_SEL TIS RIN 7 Fig. 1.43. UART Control Register (U1CON, U2CON) 42 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1.19.2 UART Control Register (UxCON) The UxCON specifies the initialization and enabling of a transmit/receive process (see Figure 1.43). Data can be read from and written to the Control Register. Address: 0030 ...

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... RIN. If the re- ceive operation completes while the status register is being read, the status information is updated upon completion of the status register read. MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1.19.3.4 Receive Parity Error Flag The Receive Parity Error Flag (PER) is set when the parity of received data and the Parity Selection Bit (PMD, bit 4 of UxMOD) are different ...

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... TBE is cleared to “0”. If 9-bit character length has been selected, the high-order byte of the transmit buffer (UxTRB2) should be written before the low-order byte (UxTRB1). 44 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0032 ,003A LSB 16 ...

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... If two or more of the samples are not low, the start bit is invalidated and the UART again begins wait- ing for a falling edge on the URXDx pin. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D0 Stop bit Start bit • ...

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... RTS (output) In both examples, the Transmit and Receive have already been enabled Fig. 1.47. CTSx and RTSx Timing Examples MSB RTS3 RTS2 RTS1 RTS0 Reserved 7 Fig. 1.48. UxRTSC Register 46 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D0 Stop bit 2-of-3 2-of-3 Edg sampling sampling detection start DATA ...

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... UART does not stop sending until the transmission is completed, even if CTSx is deasserted (high input). If TEN is cleared to “0”, the UART will not stop transmitting and the port MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER pins will remain under the control of the UART until the end of the transmission. If CTS handshaking is disabled and TEN is a “ ...

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... Instead, either the framing error or par- ity error flag is set, the error sum flag is set, and the error sum interrupt is set. 48 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER While in UART address mode, the generation of over- run errors is disabled after the first byte of data is received ...

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... ved Fig. 1.51. Special Count Source Mode Register (SCSM) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A memory map and the initial values after reset of the timers and timer reload latches are detailed above. The divide ratio of each timer is given by 1/(n + 1), where n is the value written to the timer ...

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... FIFO and CSR regis- ter (see Figure 1.51). CPU Fig. 1.51. USB Function Control Unit Block Diagram 50 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The USB Function Control Unit is composed of five sections: •Serial Interface Engine (SIE) •Generic Function Interface (GFI) • ...

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... Interrupt Enable Register 2), but not one for the resume interrupt. The resume interrupt is always en- abled. MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The USB Reset Interrupt Status Flag is set if the USB FCU sees a SE0 present on D+/D- for at least 2 ...

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... DMAC, the USB FCU sets the IN_PKT_RDY bit to a “1” automatically. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready 52 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER to accept another data packet. (The FIFO can hold up to two data packets at the same time in this con- figuration for back-to-back transmission) ...

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... The CPU writes a “0” to the OUT_PKT_RDY bit after the packet of data has been unloaded from MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER the OUT FIFO by the CPU/DMAC. In this configura- tion, the FIFO can hold up to two data packets at the same time for back-to-back reception ...

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... FUNAD6 FUNAD5 7 Fig. 1.53. Function Address Register (USBA) 54 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ditionally, the bits may be configured to allow the user to write only a “0” “1” to individual bits. When ac- cessing these registers, writing a “0” register that can only be set to a “1” by the CPU will have no affect on that register bit ...

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... ved ved Fig. 1.54. USB Power Management Register (USBPM) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER • USB Resume Detection Flag (RESUME) When the USB FCU is in the suspend state and de- tects signaling on D+/D- (from the host), it sets the Resume Detection Flag (RESUME) and generates an interrupt. The CPU writes a “ ...

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... INTST12 ved 7 Fig. 1.56. USB Interrupt Status Register 2 (USBIS2) 56 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER writing back to the register the same value that was read. To ensure proper operation, the CPU should read both USB interrupt status registers, then write back the same values it read to these two registers for clearing the status bits ...

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... USB FCU) •IN0CSR4 (FORCE_STALL) bit is set (by the USB FCU) •IN0CSR5 (SETUP_END) bit is set (by the USB FCU) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0054 INTEN2 ved ...

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... IN CSR, OUT CSR, IN MAXP, OUT MAXP and OUT WRT CNT reg- isters. This register also contains two global bits, ISO_UPD and AUTO_FL, which affect isochronous data trans- fers for endpoints 1-4. 58 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0056 FN3 FN2 FN1 ...

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... OUT_PKT_RDY. The USB FCU returns a STALL hand- shake for all subsequent IN/OUT transactions (during control transfer data or status stages) while this bit is set. The CPU writes a “0” to this bit to clear it. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0059 ...

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... INXCSR5 INXCSR4 INXCSR3 7 Fig. 1.63. USB Endpoint x IN CSR (IN_CSR) 60 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER IN0CSR6 and IN0CSR7: These bits are used to clear IN0CSR0 and IN0CSR5 respectively. Writing a “1” to these bits will clear the corresponding register bit. The USB Endpoint x IN CSR, shown in Figure 1.63, contains control and status information of the respec- tive IN endpoint 1-4 ...

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... Fig. 1.64. USB Endpoint 0 OUT CSR (OUT_CSR) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INXCSR5 (TX_FIFO_NOT_EMPTY): The USB FCU sets this bit to a “1” when there is data in the IN FIFO. This bit in conjunction with IN_PKT_RDY bit will pro- vide the transmit FIFO status information (see section 1 ...

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... When the endpoint is required to initialize the data toggle sequence bit (reset to DATA0 for the next data packet), the CPU sets this bit to a “1” and then resets 62 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 005A OUTXCSR2 ...

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... ved 7 Fig. 1.69. USB Endpoint x OUT WRT CNT High Register (WRT_CNTH) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The CPU can change this value as negotiated with the host controller through the SET_DESCRIPTOR com- mand. The setting of this register also affects the configuration of single/dual packet operation. When MAXP > ...

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... DATA_5 DATA_4 DATA_3 7 Fig. 1.73. USB Endpoint 3 FIFO Register (USBFIFO3) MSB DATA_7 DATA_6 DATA_5 DATA_4 DATA_3 7 Fig. 1.74. USB Endpoint 4 FIFO Register (USBFIFO4) 64 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 0060 DATA_2 DATA_1 DATA_0 Access: R/W 0 Reset: N Endpoint 0 IN/OUT FIFO register ...

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... OBF1 (OBE1) OBE Fig. 1.76. Data Bus Buffer Interrupt Request Circuit MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER When the bus interface is operating, DQ come a 3-state data bus that sends and receives data, command, and status to and from the master CPU. At the same time host CPU control signal input pins ...

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... MSB DBBC07 DBBC06 ved DBBC04 DBBC03 7 Fig. 1.78. Data Bus Buffer Control Register 0 (DBBC0) 66 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A Flag ( The level of the A written from the host CPU to the input data bus buffer. 1.22.2 Input Data Bus Buffer Registers ...

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... DBBS14 7 Fig. 1.79. Data Bus Buffer Status Register 1 (DBBS1) MSB DBBC17 ved ved DBBC14 DBBC13 7 Fig. 1.80. Data Bus Buffer Control Register 1 (DBBC1) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 004D Access: R/W DBBS12 DBBS11 DBBS10 0 Reset ...

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... Index & Temp Reg Status Reg Data Bus Fig. 1.81. DMAC Block Diagram 68 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Each channel of the DMAC is made up of the following: • 16-bit source and destination registers • A 16-bit transfer count register • Two mode registers • ...

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... ved DRLDD DTSC DISFI 7 Fig. 1.82. DMAC Index and Status Mode Register (DMAIS) MSB DxTMS DxRLD DxDAUE DxDWC DxDRCE Fig. 1.83. DMAC Channel x Mode Register 1 (DMAxM1) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 003F DIUF DOSFI DOUF Access: R/W 0 Reset D0UF ...

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... Fig. 1.84. DMAC Channel 0 Mode Register 2 (DMA0M2) MSB D1CEN D1CRR D1UMIE D1SWT D1HRS3 7 Fig. 1.85. DMAC Channel 1 Mode Register 2 (DMA1M2) 70 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LSB Address: 0041 16 D0HRS2 D0HRS1 D0HRS0 Access: R/W D0HRS3,2,1,0 DMAC Channel 0 Hardware Transfer Request Source Bits (bits 3,2,1,0) 0000: Disable ...

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... Signal (Port3 ) 3 Transfer Request Source (active low) Transfe Request Source Sampling Transfer Request Source Sample Latch Reset Fig. 1.88. DMAC Transfer-Burst Transfer Initiated MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER STA $zz LDA$zz DMAC Transfer (first cycle) DMA Dest ADL1 DMA Source ...

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... Fig. 1.89. Clock Control Register (CCR) 72 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER f are phase-locked frequency multiples of the fre- SYN quency synthesizer input. The inputs to the frequency synthesizer can be either X The two-phase non-overlapping system clock (CPU and peripherals) is derived from the source to the clock circuit and is half the frequency of the source ...

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... The input clock for the frequency synthesizer must be set oscillation can be disabled. in Note: CPMA values shown assume single-chip mode with stack in one page. Fig. 1.90. Clock Flow Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CPMA6 FSC0 X in clock clock stopped ...

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... Setting FSM2 to 255 disables the prescaler and Prescaler IN FSM2 006E Fig. 1.91. Frequency Synthesizer Circuit 74 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The relationship between f as follows: • that VCO PIN SYN of the value loaded in FSM1. (See Figure 1.94). n must be chosen such that f • ...

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... out in Fig. 1.92. Clock Block Diagram MSB FIN ved 7 Fig. 1.93. Frequency Synthesizer Control Register (FSC) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN1 P2 P2+ T STP ...

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... MHz 128 48.00 MHz 255 (m+1)) SYN VCO Fig. 1.96. Frequency Synthesizer divided Ratio Register (FSD) 76 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address: 006D LSB Bit 2 Bit 1 Bit 0 Access: R/W 0 Reset: FF Bit 0-7 Frequency synthesizer multiply value, n, that is used to multiply the prescaler output frequency, f ...

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... Opcode Data ote: Return from a STP Instruction is caused by an interrupt, followed by the countdown and underflow of Time 2 Fig. 1.97. STP Cycle Timing Diagram (STP) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Oscillation is restarted when a reset or an external in- terrupt is received. The interrupt control bit of the interrupt used to release the stop mode must be set to a " ...

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... Data Opcode Note: Return from a WIT instruction is caused by a interrupt. Fig. 1.98. WIT Cycle Timing Diagram (WIT) 78 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Returning from wait mode is accomplished just when returning from stop mode, with the exception that you need not provide time for the oscillator to sta- bilize, because the oscillation never stopped ...

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... Reset SYNC out Address Data Timer countdown from 01FF Fig. 1.99. Internal Processing Sequence after RESET MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER bilize, a delay is generated by the countdown of Timer 1 and Timer 2 cascaded with FF and 01 loaded in Timer 2. After the reset sequence 16 completes, program execution begins at the address ...

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... Power dissipation (Note Operating temperature OPR T Storage temperature STG Note: Maximum power dissipation is based on heat dissipation characteristics not chip power consumption. 80 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Conditions Limits -0.3 to 6 Values are with respect to -0 Output transistors are SS -0 ...

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... The maximum oscillation frequency of 50 KHz is for a crystal oscillator connected between XCin and XCout. An external signal having a maximum frequency of 5 MHz can be input to XCin. Note 7. When using Frequency Synthesizer Circuit, minimum limit is 4 MHz. And when using USB, put internal clock f(.)to more than 6 MHz. MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Parameter RESET ...

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... USB operating with transceiver voltage converter enabled CPU and DMAC running Timers and SCSG running BothUARTs transmitting MBI and SIO disabled 82 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ° C unless otherwise noted) Test Conditions Ioh = -10mA USB D+, USB D- pins pull down to Vss by 15 ...

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... SIO internal clock output “Low” pulse width tsu(SRXD-SCLKI) SIO receive setup time (internal clock) th(SCLKI-SRXD) SIO receive hold time (internal clock) td(SCLKI-STXD) SIO transmit delay time (internal clock) MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Limits Min Typ. Max 2 41 ...

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... Data input hold time after write ta(E-D) Data output enable time after read tv(E-D) Data output disable time after read tv(E-OBF) OBF output transmission time after E inactive td(E-IBF) IBF output transmission time after E inactive 84 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Limits Min Typ ...

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... Ver 1.4 Inputs RESET Interrupts _____ _____ INT0, INT1 CNTR0, CNTR1 Timers TOUT CNTR0, CNTR1 CNTR0, CNTR1 Fig. 2.1. Reset, Clock, Interrupts and Timers Timing Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER _______ tw(RESET) 0.2Vcc tc twh(X ) twl(X in 0.8Vcc X in 0.2Vcc tc( twh( 0.8Vcc XC in ...

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... Note: TTL input levels in parenthesis (TTL levels selected when PTC7 = “1”) Fig. 2.2. MBI Timing Diagram (Separate R and W Type Mode R/W S0, S1 Read DQ - Write DQ - OBF, IBF Fig. 2.3. MBI Timing Diagram (R/W Type Mode) 86 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER __ t su(A-R) 0.8Vcc (2.0V) 0.2Vcc (0.8V) t su(S-R) 0.2Vcc (0.8V) t w(R) 0.8Vcc (2.0V) 0.2Vcc (0.8V) 0.8Vcc 0.2Vcc v(R-D) ...

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... Data bus hold time with respect to RD td(WR-DB) Data bus delay time with respect to WR tv(WR-DB) Data bus valid time with respect to WR tr(D+), tr(D-) USB output rise time, CL= (D+), tf(D-) USB output fall time, CL=50 pF Note : Measurement conditions: Iohl = MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Parameter Min. 83.33 0.5*tc( )-5 0.5*tc( )- ...

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... OUT RDY HOLD (Enter state) HLDA HOLD (Exit state) HLDA DB0-DB7 (CPU Read Phase) DB0-DB7 (CPU Write Phase) USB D+ USB D- Fig. 2.4. Microprocessor and Memory Expansion Mode Timing Diagram 1 88 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER twh( twl AH) 0.5Vcc - AL ) 0.5Vcc WR td( - ...

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... Read Phase) DB0-DB7 (CPU Write Phase) Fig. 2.5. Microprocessor and Memory Expansion Mode Timing Diagram 2 SIO Fig. 2.6. SIO Timing Diagram Measurement output pin Fig. 2.7. Output Switching Characteristics Measurements Circuits MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ___ ___ twl(RD), twl(WR) 0.5Vcc ___ td(AH - WR) ...

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... Mark Specification Form 3. Data to be written to ROM, in EPROM form three identical copies floppy disk form. 90 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ROM PROGRAMMING METHOD The built-in PROM of the blank One-time PROM ver- sion and built-in EPROM version can be read or programmed with a general-purpose PROM program- mer using a special programming adapter ...

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... How will you use the X Quartz crystal Other ( ) At what frequency? (2) Which function will you use the pins P5 Ports P5 and P5 function Comments MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI ELECTRIC 16 EPROM type 27512 *= $0000 .BYTE ‘M37640M8-’ -X oscillator? in out External clock input f(X ...

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... The ASCII codes and addresses are listed to the right in hexadecimal notation. 92 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TEL ( In the address space of the microcomputer, the internal ROM area is from ad- dress 8080 to FFFB . The reset vector is stored in addresses FFFA ...

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... Ver 1.4 80P6n (80-PIN QFP) MARK SPECIFICATION FORM Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). Notes A. Standard Mitsubishi Mark Mitsubishi product number (6-digit, or 7-digit Customer’s Parts Number + Mitsubishi IC Catalog Name ...

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... EIAJ Package Code JEDEC Code QFP80-P-1420-0.80 – MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Weight(g) Lead Material 1.58 Alloy Detail F 7640 Group Plastic 80pin 14 20mm body QFP Recommended Mount Pad ...

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... These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. ...

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REVISION HISTORY Rev. No. 1.4 First Edition 7640 GROUP DATA SHEET Revision Description (1/1) Rev. date 09/05/00 ...