UPD4564323G5-A10B-9JH NEC, UPD4564323G5-A10B-9JH Datasheet
UPD4564323G5-A10B-9JH
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UPD4564323G5-A10B-9JH Summary of contents
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... Burst termination by Burst stop command and Precharge command The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. ...
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Ordering Information Part number PD4564323G5-A60-9JH PD4564323G5-A70-9JH PD4564323G5-A80-9JH PD4564323G5-A10-9JH PD4564323G5-A10B-9JH 2 Organization Clock frequency (word bit bank) MHz (MAX.) 512K 32 4 166 143 125 100 100 Data Sheet M14376EJ2V0DS00 PD4564323 for Rev. E Package 86-pin Plastic TSOP (II) (10.16 mm ...
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... Part Number PD4564323G5 - A60 NEC Memory Synchronous DRAM Memory Density 64 : 64M bits Organization 32 : x32 Number of Banks & Interface 3 : 4Bank, LVTTL Data Sheet M14376EJ2V0DS00 PD4564323 for Rev. E Minimum Cycle Time (166MHz (143MHz (125MHz (100MHz) 10B : 10 ns (100MHz) Low Voltage ± ...
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... Row address strobe /CAS : Column address strobe /WE : Write enable DQM0 to DQM3 : DQ mask enable V : Supply voltage Ground Supply voltage for Ground for connection 4 [ PD4564323] 512K words 32 bits 4 banks ...
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Block Diagram CLK Clock Generator CKE Address Mode Register /CS /RAS /CAS /WE Bank D Bank C Bank B Row Address Buffer & Refresh Bank A Counter Sense Amplifier Column Decoder & Column Latch Circuit Address Buffer & Burst Data ...
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Input / Output Pin Function .............................................................................................................. 8 2. Commands ......................................................................................................................................... 9 3. Simplified State Diagram ................................................................................................................ 12 4. Truth Table ....................................................................................................................................... 13 4.1 Command Truth Table............................................................................................................................. 13 4.2 DQM Truth Table ...................................................................................................................................... 13 4.3 CKE Truth Table....................................................................................................................................... 13 4.4 ...
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Electrical Specifications ................................................................................................................. 32 13.1 AC Parameters for Read Timing ......................................................................................................... 37 13.2 AC Parameters for Write Timing ......................................................................................................... 39 13.3 Relationship between Frequency and Latency ................................................................................. 40 13.4 Mode Register Set ................................................................................................................................ 41 13.5 Power on Sequence and ...
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Input / Output Pin Function Pin name Input / Output CLK Input CKE Input /CS Input /RAS, /CAS, /WE Input A0 - A10 Input BA0, BA1 Input DQM0 - DQM3 Input DQ0 - DQ31 Input / Output V , ...
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Commands Mode register set command (/CS, /RAS, /CAS, /WE = Low) The PD4564323 has a mode register that defines how the device operates. In this command, A0 through A10, BA0 and BA1 are the data input pins. After power ...
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Write command (/CS, /CAS, /WE = Low, /RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first ...
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Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the PD4564323 exits the self refresh mode. During self refresh mode, ...
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Simplified State Diagram MRS Mode Register Set Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 12 Self Refresh REF IDLE Power CKE Active ROW Power ACTIVE CKE Read Read READ Write READA Precharge ...
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Truth Table 4.1 Command Truth Table Function Symbol Device deselect DESL No operation NOP Burst stop BST Read READ Read with auto precharge READA Write WRIT Write with auto precharge WRITA Bank activate ACT Precharge select bank PRE Precharge ...
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Note1 4.4 Operative Command Table Current state /CS /RAS /CAS /WE Idle ...
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Current state /CS /RAS /CAS /WE Read with auto H precharge Write with auto H precharge ...
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Current state /CS /RAS /CAS /WE Write recovering Write recovering H with auto precharge L ...
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Command Truth Table for CKE Current State CKE /CS /RAS /CAS /WE n – Self refresh Self refresh recovery ...
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Initialization The synchronous DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling. (2) After the pause, all ...
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Programming the Mode Register The mode register is programmed by the Mode register set command using address bits A10 through A0, BA0 and BA1 as data inputs. The register retains data until it is reprogrammed or the device loses ...
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Mode Register BA1 BA0 A10 BA1 BA0 A10 LTMODE BA1 BA0 A10 BA1 ...
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Burst Length and Sequence [Burst of Two] Starting address (column address A0, binary [Burst of Four] Starting address (column address A1 - A0, binary [Burst of Eight] Starting address (column address A2 - ...
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Address Bits of Bank-Select and Precharge Row (Activate command (Precharge command) Col (/CAS strobes A10 BA0 ...
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Precharge The precharge command can be issued anytime after t Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after t is satisfied. The parameter t RP The earliest timing ...
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Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected ...
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Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of the t data word input to the device CLK /CAS latency = 2 Command WRITA ...
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Read / Write Command Interval 11.1 Read to Read Command Interval During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will ...
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Write to Read Command Interval Write command and Read command interval is also 1 cycle. Only the write data before Read command will be written. The data bus must be Hi-Z at least one cycle prior to the first ...
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... Command Read DQM DQ /CAS latency = 3 Command Read DQM Write 1cycle Hi-Z is necessary Q1 Q2 Hi-Z is necessary Data Sheet M14376EJ2V0DS00 PD4564323 for Rev. E Burst length = Burst length = Write Write ...
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Burst Termination There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. 12.1 Burst Stop Command During a ...
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Precharge Termination 12.2.1 Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same ...
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Precharge Termination in WRITE Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be ...
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Electrical Specifications All voltages are referenced to V (GND). SS After power up, wait more than 100 s and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Voltage ...
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DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Operating current I Burst length = 1, CC1 t I One bank active Precharge standby current I P CKE CC2 in power down mode I PS CKE CC2 Precharge ...
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DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Input leakage current I 0 I(L) All other pins not under test = Output leakage current 0 O(L) V High level output voltage ...
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Synchronous Characteristics Parameter /CAS Symbol latency Clock cycle time CK3 CK2 Access time from CLK AC3 AC2 CLK high level width t CH CLK ...
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Asynchronous Characteristics Parameter /CAS Symbol latency REF to REF/ACT command t RC period (Operation) REF to REF/ACT command t RC1 period (Refresh) ACT to PRE command period t RAS PRE to ACT command period t RP Delay time ACT to ...
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CLK CKE CKS CMS CMH /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM L Hi RCD Activate Read Command Command ...
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CLK CKE CKS CMS CMH /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM L Hi RCD Activate Read with Command ...
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CLK CKE t CKS t t CMS CMH /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM Hi RCD t RRD Write with ...
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Relationship between Frequency and Latency Speed version Clock cycle time [ns] Frequency [MHz] /CAS latency [t ] RCD /RAS latency (/CAS latency + [t ]) RCD [ RC1 [t ] RAS [t ] RRD [t ...
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CLK CKE H t RSC 2 CLK (MIN.) /CS /RAS /CAS /WE BA0 BA1 A10 ADDRESS KEY ADD DQM Hi-Z DQ Precharge Mode Activate All Banks Register Set Command Command Command is valid t ...
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... BA0 BA1 A10 ADDRESS KEY ADD DQM High level is necessary Hi-Z DQ Precharge Mode CBR(Auto) All Banks Register Set Refresh Command Command Command is necessary is necessary is necessary refresh cycles are necessary CBR (Auto) refresh Command is necessary t t RC1 RC1 Activate Command ...
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CLK CKE H /CS /RAS /CAS /WE BA0 L BA1 L A10 RAa ADD RAa CAa DQM L Hi-Z DQ Activate Read Command Command for Bank A for Bank ...
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CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z QAa1 QAa2 DQ Activate Read Command Command for Bank A for Bank T10 ...
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CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ Activate Read Command Command for Bank A for Bank T10 T11 T12 ...
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CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ DAa1 DAa2 Activate Write 1-CLOCK Command Command SUSPENDED for Bank A for Bank ...
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CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ DAa1 DAa2 Activate Write 1-CLOCK Command Command SUSPENDED for Bank A for Bank ...
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CLK t CKSP CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ Activate Read Command Command for Bank A for Bank A Power Down Power Down Mode ...
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... CKE H /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM L Hi-Z DQ Precharge CBR (Auto) Command Refresh (if necessary CBR(Auto) Refresh t t RC1 RC1 Activate Read Command Command ...
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... T3 T4 CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM L Hi-Z DQ Precharge Self Refresh Command Entry (if necessary Self Refresh Self Refresh Self Refresh Entry Exit Exit (or Activate Command) Next Clock Enable t RC1 ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z QAa1 QAa2 DQ Activate Read Command Command for Bank A for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ Activate Read Command Command for Bank A for Bank T10 T11 ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RDa ADD RDa CDa DQM L Hi-Z DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DQ Activate Write Command Command for Bank D for Bank D ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RDa ADD RDa CDa DQM L Hi-Z DDa1 DDa2 DDa3 DDa4 DQ Activate Write Command Command for Bank D for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RDa ADD RDa CDa DQM L Hi-Z QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 DQ Activate Read Command ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RBa ADD RBa CBa DQM L Hi-Z DQ Activate Read Command Command for Bank B for Bank T10 T11 ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa L DQM Hi-Z DAa1 DAa2 DAa3 DAa4 DQ Activate Write Command Command for Bank A for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa L DQM Hi-Z DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DQ Activate Write Command Command for ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z QAa1 QAa2 DQ Activate Read Command Command for Bank A for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ Activate Read Command Command for Bank A for Bank T10 T11 ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z Aa1 Aa2 DQ Activate Read Command Command for Bank A for Bank A Activate Command ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z DQ Activate Read Command Command for Bank A for Bank A Activate Command for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RBa ADD RAa CAa RBa DQM L Hi-Z Aa1 Aa2 Aa3 Aa4 DQ Activate Write Command Command for Bank A for Bank A ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RBa ADD RAa CAa RBa DQM L Hi-Z Aa1 Aa2 Aa3 DQ Activate Write Command Command for Bank A for Bank A Activate ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z DQ Activate Activate Command Command Read for Bank A for Bank D Command Auto Precharge ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z DQ Activate Activate Command Command for Bank A for Bank D Read Command for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 RAa RDa A10 ADD RAa CAa RDa DQM L Hi-Z DQ Activate Activate Command Command for Bank A for Bank D Write Write with ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z DQ Activate Activate Command Command for Bank A for Bank D Write Command for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z Aa Aa+1 DQ Activate Read Activate Command Command Command for Bank A for Bank A ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa L DQM Hi-Z DQ Activate Read Activate Command Command Command for Bank A for Bank A for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z Aa Aa+1 Aa+2 Aa-2 Aa-1 DQ Activate Write Activate Command Command Command for Bank A ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa DQM L Hi-Z Aa Aa+1 Aa+2 DQ Activate Write Activate Command Command Command for Bank A for Bank ...
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CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM0 DQM1 DQ 0-7 DQ 8-15 Activate Read Byte 1 Command Command not Read for Bank D for Bank ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM Hi-Z DQ Qa1 Activate Read Command Command for Bank D for Bank T10 T11 T12 T13 Qa2 ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa RDa CAa CDa CAb t RCD t t RRD RCD DQM L Hi-Z DQ QAa1 QDa1 QAb1 QAb2 QDb1 QDb2 ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa RDa CAa CDa CAb t RCD t t RRD RCD DQM L Hi-Z DAa1 DDa1 DAb1 DQ Activate Activate Command ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RAa CAa ADD DQM L Hi-Z DAa1 DAa2 DAa3 DAa4 DQ Activate Write Command Command for Bank A for Bank A PRE Termination ...
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CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa L DQM Hi-Z DAa1 DAa2 DAa3 DQ Activate Write Command Command for Bank A for Bank A PRE Termination ...
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Package Drawing 86-PIN PLASTIC TSOP (II) (10.16 mm (400 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. Dimension "A" does ...
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Recommended Soldering Condition Please consult with our sales offices for soldering conditions of the PD4564323. Type of Surface Mount Device PD4564323G5: 86-pin Plastic TSOP (II) (10.16 mm (400)) 16. Revision History Edition / Page Date This Previous edition edition ...
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Data Sheet M14376EJ2V0DS00 PD4564323 for Rev ...
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Data Sheet M14376EJ2V0DS00 PD4564323 for Rev. E ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...