MC74AC74ML1 ON Semiconductor, MC74AC74ML1 Datasheet

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MC74AC74ML1

Manufacturer Part Number
MC74AC74ML1
Description
Dual D Type Positive Edge Triggered Flip Flop
Manufacturer
ON Semiconductor
Datasheet
1.MC74AC74ML1.pdf (6 pages)
Dual D Type Positive
Edge Triggered Flip Flop
and Set inputs and complementary (Q,Q) outputs. Information at the input is
transferred to the outputs on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
TRUTH TABLE (Each Half)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Q 0 (Q 0 ) = Previous Q(Q) before
Outputs Source/Sink 24 mA
C D1
S D
= LOW-to-HIGH Clock Transition
ACT74 Has TTL Compatible Inputs
The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear
LOW input to S D (Set) sets Q to HIGH level
LOW input to C D (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C D and S D makes both Q and Q HIGH
V CC
H
H
H
H
L
L
14
1
D 1
CP 1
C D2
D 1
C D
13
LOW-to-HIGH Transition of Clock
C D1
Inputs
S D1
2
H
H
H
H
L
L
Q 1
Q 1
CP 1
D 2
12
CP
3
X
X
X
L
CP 2
S D1
11
4
D
X
X
X
H
X
L
CP 2
D 2
S D2
Q 1
10
5
Q 0
Q
H
H
H
C D2
L
L
S D2
Outputs
Q 2
Q 2
Q 2
Q 1
9
6
Q 0
Q
H
H
H
L
L
GND
Q 2
8
7
PIN NAMES
D 1 , D 2
CP 1 , CP 2
C D1 , C D2
S D1 , S D2
Q 1 , Q 1 , Q 2 , Q 2
FACT DATA
5-1
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
MC74ACT74
MC74AC74
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED
LOGIC SYMBOL
S D1
S D2
CASE 751A-03
CASE 646-06
Q 1
D 1
D 2
FLIP-FLOP
Q 2
N SUFFIX
D SUFFIX
PLASTIC
PLASTIC
CP 1
CP 2
Q 1
Q 2
C D1
CD 2

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MC74AC74ML1 Summary of contents

Page 1

Dual D Type Positive Edge Triggered Flip Flop The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the ...

Page 2

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. MAXIMUM RATINGS* Symbol Supply Voltage (Referenced to GND) ...

Page 3

DC CHARACTERISTICS Symbol Symbol Parameter Parameter V IH Minimum High Level Input Voltage Input Voltage V IL Maximum Low Level Input Voltage Input Voltage V OH Minimum High Level Output Voltage Output Voltage V OL Maximum Low Level Output Voltage ...

Page 4

AC OPERATING REQUIREMENTS Symbol Symbol Parameter Parameter Set-up Time, HIGH or LOW Hold Time, HIGH or LOW ...

Page 5

AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Symbol Parameter Parameter Maximum Clock f max f max Frequency Frequency Propagation Delay t PLH t PLH ...

Page 6

SEATING PLANE –A– –B– –T– SEATING 14 PL PLANE 0.25 (0.010 Motorola reserves the right to make changes without ...

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