MPC859 Freescale Semiconductor, Inc, MPC859 Datasheet
MPC859
Available stocks
Related parts for MPC859
MPC859 Summary of contents
Page 1
... Freescale Semiconductor, Inc. Advance Information MPC866EC/D Rev. 1.4, 8/2003 MPC866/859 Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC866/859 family (refer to Table 1 for a list of devices). The MPC866P is the superset device of the MPC866/859 family. ...
Page 2
... Kbytes 3 MPC852T 4 KBytes 1 On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot Assigner (TSA the MPC859DSL, the SMC (SMC1) is for UART only. 3 For more details on the MPC852T, please refer to the MPC852T Hardware Specifications. ...
Page 3
... UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission time. (The earlier UTOPIA level 1 specification is also supported.) – Multi-PHY support on the MPC866, MPC859P, and MPC859T – Four PHY support on the MPC866/859 — Parameter RAM for both SPI and I — ...
Page 4
... Interrupts — Seven external interrupt request (IRQ) lines — Twelve port pins with interrupt capability — The MPC866P and MPC866T have 23 internal interrupt sources; the MPC859P, MPC859T, and MPC859DSL have 20 internal interrupt sources. — Programmable priority between SCCs (MPC866P and MPC866T) — ...
Page 5
... The MPC866/859 is comprised of three modules that each use a 32-bit internal bus: MPC8xx core, system integration unit (SIU), and communication processor module (CPM). The MPC866P block diagram is shown in Figure 1 on page 6. The MPC859P/859T/859DSL block diagram is shown in Figure 2 on page 7. MOTOROLA MPC866/859 Hardware Specifications ...
Page 6
... Freescale Semiconductor, Inc. Features Features Instruction Instruction Cache Bus Instruction MMU Embedded 32-Entry ITLB MPC8xx Processor Load/Store Core Data Cache Bus Data MMU 32-Entry DTLB Fast Ethernet Controller DMAs FIFOs Parallel I/O 10/100 4 Baud Rate Base-T Generators Media Access Control Parallel Interface Port ...
Page 7
... UTOPIA MII SCC1 † The MPC859P has a 16-Kbyte instruction cache and a 8-Kbyte data cache. * The MPC859DSL does not contain SMC2 nor the time slot assigner, and provides eight SDMA controllers. Figure 2. MPC859P/859T/MPC859DSL Block Diagram 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC866/859. Table 2 shows the maximum tolerated ratings, and Table 3 shows the operating temperatures ...
Page 8
... Freescale Semiconductor, Inc. Maximum Tolerated Ratings Maximum Tolerated Ratings Table 2. Maximum Tolerated Ratings (continued) Rating 2 Input voltage V in Storage temperature range T stg 1 The power supply of the device must start its ramp from 0 Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum ratings are stress ratings only ...
Page 9
... Freescale Semiconductor, Inc. 4 Thermal Characteristics Table 4 shows the thermal characteristics for the MPC866/859. Table 4. MPC866/859 Thermal Resistance Data Rating 1 Junction-to-ambient Natural Convection Airflow (200 ft/min) 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package top Natural Convection Airflow (200 ft/min) 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airfl ...
Page 10
... Freescale Semiconductor, Inc. Power Dissipation Power Dissipation 5 Power Dissipation Table 5 shows power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1 mode, where CPU frequency is twice the bus speed. Die Revision Bus Mode 0 1 Typical power dissipation at VDDL and VDDSYN is at 1.8 V. and VDDH is at 3.3 V. ...
Page 11
... Freescale Semiconductor, Inc. Table 6. DC Electrical Specifications (continued) Characteristic Input low voltage EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5V (except TMS, TRST, DSCK and DSDI pins) for 5 Volts Tolerant Pins Input leakage current, Vin = VDDH (except TMS, TRST, ...
Page 12
... Freescale Semiconductor, Inc. Thermal Calculation and Measurement Thermal Calculation and Measurement 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature +( θ where ambient temperature (º package junction-to-ambient thermal resistance (ºC/W) θ power dissipation in package ...
Page 13
... Freescale Semiconductor, Inc Board Temperture Rise Above Ambient Divided by Package Figure 3. Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: ...
Page 14
... Freescale Semiconductor, Inc. Power Supply and Power Sequencing Power Supply and Power Sequencing 7.5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (Ψ measurement of the temperature at the top center of the package case using the following equation: ...
Page 15
... Freescale Semiconductor, Inc. These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes are forward-biased and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 4 can be added to meet these requirements ...
Page 16
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Freq Min Core 40 Bus 40 Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) Part 50 MHz Freq Min Max Core 40 50 Bus 20 25 Table 9 shows the timings for the MPC866/859 at 33, 40, 50, and 66 MHz bus operation ...
Page 17
... Freescale Semiconductor, Inc. Table 9. Bus Operation Timings (continued) Num Characteristic B7a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR output hold (MIN = 0.25 x B1) B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2), IWP(0:2), LWP(0:1), STS output hold (MIN = 0.25 x B1) B8 CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31), DP(0:3), valid (MAX = 0. 6.3) B8a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR valid (MAX = 0 ...
Page 18
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 9. Bus Operation Timings (continued) Num Characteristic B16a TEA, KR, RETRY, CR valid to CLKOUT (setup time) (MIN = 0. 4.5) B16b BB, BG, BR, valid to CLKOUT (setup 2 time) (4 MIN = 0. 0.00 ) B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) (MIN = 0. ...
Page 19
... Freescale Semiconductor, Inc. Table 9. Bus Operation Timings (continued) Num Characteristic B24a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11, TRLX = 0 (MIN = 0. 2.00) B25 CLKOUT rising edge to OE, WE(0:3) asserted (MAX = 0. 9.00) B26 CLKOUT rising edge to OE negated (MAX = 0. 9.00) B27 A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 1 (MIN = 1 ...
Page 20
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 9. Bus Operation Timings (continued) Num Characteristic B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 (MIN = 0. – 2.00) B29d WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1. – ...
Page 21
... Freescale Semiconductor, Inc. Table 9. Bus Operation Timings (continued) Num Characteristic B30c WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375 x B1 – 3.00) B30d WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS ...
Page 22
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 9. Bus Operation Timings (continued) Num Characteristic B32c CLKOUT rising edge to BS valid, as requested by control bit BST3 in the corresponding word in the UPM (MAX = 0. 6.80) B32d CLKOUT falling edge to BS valid- as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0 ...
Page 23
... Freescale Semiconductor, Inc. Table 9. Bus Operation Timings (continued) Num Characteristic B37 UPWAIT valid to CLKOUT falling 8 edge (MIN = 0. 6.00) B38 CLKOUT falling edge to UPWAIT 8 valid (MIN = 0. 1.00) B39 AS valid to CLKOUT rising edge = 0. 7.00) B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge (MIN = 0. 7.00) B41 TS valid to CLKOUT rising edge (setup time) (MIN = 0 ...
Page 24
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 5 shows the control timing diagram. 2.0 V CLKOUT B 2.0 V Outputs 0.8 V Outputs Inputs Inputs A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure 6 shows the timing for the external clock. ...
Page 25
... Freescale Semiconductor, Inc. Figure 7 shows the timing for the synchronous output signals. CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 7. Synchronous Output Signals Timing Figure 8 shows the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB ...
Page 26
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 9 shows the timing for the synchronous input signals. CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure 9. Synchronous Input Signals Timing Figure 10 shows normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller ...
Page 27
... Freescale Semiconductor, Inc. Figure 11 shows the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 D[0:31], DP[0:3] Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 12 through Figure 15 show the timing for the external bus read controlled by various GPCM factors ...
Page 28
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing CLKOUT B11 TS B8 A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10) CLKOUT B11 TS B8 A[0:31] CSx OE D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 11) 28 MPC866/859 Hardware Specifications ...
Page 29
... Freescale Semiconductor, Inc. CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, B12 B8 B22a B27 B27a B22b B22c B18 Go to: www.freescale.com Bus Signal Timing B23 B26 ...
Page 30
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 16 through Figure 18 show the timing for the external bus write controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) 30 MPC866/859 Hardware Specifi ...
Page 31
... Freescale Semiconductor, Inc. CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, B12 B28b B28d B25 B28a B28c B8 Go to: www.freescale.com Bus Signal Timing B30a B30c ...
Page 32
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing CLKOUT B11 TS A[0:31] B22 CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) 32 MPC866/859 Hardware Specifications For More Information On This Product, B12 B8 B28b B28d B25 B29e B29i B29d B29h ...
Page 33
... Freescale Semiconductor, Inc. Figure 19 shows the timing for the external bus controlled by the UPM. CLKOUT B8 A[0:31] CSx B34 B34b BS_A[0:3], BS_B[0:3] B35 B36 B35b GPL_A[0:5], GPL_B[0:5] Figure 19. External Bus Timing (UPM Controlled Signals) MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, ...
Page 34
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 20 shows the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 21 shows the timing for the asynchronous negated UPWAIT signal controlled by the UPM. ...
Page 35
... Freescale Semiconductor, Inc. Figure 22 shows the timing for the synchronous external master access controlled by the GPCM. CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx Figure 22. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 23 shows the timing for the asynchronous external master memory access controlled by the GPCM. ...
Page 36
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 10 shows the interrupt timing for the MPC866/859. Num Characteristic I39 IRQx valid to CLKOUT rising edge (setup time) I40 IRQx hold time after CLKOUT I41 IRQx pulse width low I42 IRQx pulse width high ...
Page 37
... Freescale Semiconductor, Inc. Table 11 shows the PCMCIA timing for the MPC866/859. Num Characteristic A(0:31), REG valid to PCMCIA 1 P44 Strobe asserted (MIN = 0. – 2.00) A(0:31), REG valid to ALE P45 1 negation (MIN = 1. – 2.00) CLKOUT to REG valid (MAX = 0.25 P46 8.00) CLKOUT to REG invalid (MIN = P47 ...
Page 38
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Figure 27 shows the PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] P46 REG P48 CE1/CE2 PCOE, IORD P52 ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Read 38 MPC866/859 Hardware Specifications ...
Page 39
... Freescale Semiconductor, Inc. Figure 28 shows the PCMCIA access cycle timing for the external bus write. CLKOUT TS A[0:31] P46 REG P48 CE1/CE2 PCWE, IOWR P52 ALE D[0:31] Figure 28. PCMCIA Access Cycles Timing External Bus Write Figure 29 shows the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 29 ...
Page 40
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC866/859. Num Characteristic CLKOUT to OPx, valid (MAX = 0. P57 + 19.00) 1 HRESET negated to OPx drive P58 0. 3.00) IP_Xx valid to CLKOUT rising edge (MIN P59 = 0. 5.00) CLKOUT rising edge to IP_Xx invalid P60 (MIN = 0 ...
Page 41
... Freescale Semiconductor, Inc. Table 13 shows the debug port timing for the MPC866/859. Num Characteristic D61 DSCK cycle time D62 DSCK clock pulse width D63 DSCK rise and fall times D64 DSDI input data setup time D65 DSDI data hold time D66 ...
Page 42
... Freescale Semiconductor, Inc. Bus Signal Timing Bus Signal Timing Table 14 shows the reset timing for the MPC866/859. Num Characteristic CLKOUT to HRESET high impedance R69 (MAX = 0. 20.00) CLKOUT to SRESET high impedance R70 (MAX = 0. 20.00) RSTCONF pulse width (MIN = 17.00 x R71 B1) R72 — Configuration data to HRESET rising R73 edge setup time (MIN = 15 ...
Page 43
... Freescale Semiconductor, Inc. Figure 34 shows the reset timing for the data bus configuration. HRESET R71 RSTCONF R74 D[0:31] (IN) Figure 34. Reset Timing—Configuration from Data Bus Figure 35 shows the reset timing for the data bus weak drive during configuration. CLKOUT ...
Page 44
... Freescale Semiconductor, Inc. IEEE 1149.1 Electrical Specifications IEEE 1149.1 Electrical Specifications Figure 36 shows the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 36. Reset Timing—Debug Port Configuration 11 IEEE 1149.1 Electrical Specifications Table 15 shows the JTAG timings for the MPC866/859 shown in Figure 37 through Figure 40. ...
Page 45
... Freescale Semiconductor, Inc. TCK J82 J84 Figure 37. JTAG Test Clock Input Timing TCK TMS, TDI TDO Figure 38. JTAG Test Access Port Timing Diagram TCK TRST Figure 39. JTAG TRST Timing Diagram MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, IEEE 1149.1 Electrical Specifications ...
Page 46
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics TCK Output Signals Output Signals Output Signals Figure 40. Boundary Scan (JTAG) Timing Diagram 12 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC866/859. ...
Page 47
... Freescale Semiconductor, Inc. DATA-IN STBI STBO Figure 41. PIP Rx (Interlock Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 42. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 43. PIP Rx (Pulse Mode) Timing Diagram MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, ...
Page 48
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics DATA-OUT STBO (Output) STBI (Input) Figure 44. PIP TX (Pulse Mode) Timing Diagram CLKO DATA-IN DATA-OUT Figure 45. Parallel I/O Data-In/Data-Out Timing Diagram 12.2 Port C Interrupt AC Electrical Specifications Table 17 shows timings for port C interrupts. Num ...
Page 49
... Freescale Semiconductor, Inc. Figure 46 shows the port C interrupt detection timing. Port C (Input) Figure 46. Port C Interrupt Detection Timing 12.3 IDMA Controller AC Electrical Specifications Table 18 shows the IDMA controller timings as shown in Figure 47 through Figure 50. Num 40 DREQ setup time to clock high 41 DREQ hold time from clock high ...
Page 50
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 48. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 49. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA 50 MPC866/859 Hardware Specifications ...
Page 51
... Freescale Semiconductor, Inc. CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 50. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA 12.4 Baud Rate Generator AC Electrical Specifications Table 19 shows the baud rate generator timings as shown in Figure 51. Table 19. Baud Rate Generator Timing Num Characteristic 50 BRGO rise and fall time ...
Page 52
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 12.5 Timer AC Electrical Specifications Table 20 shows the general-purpose timer timings as shown in Figure 52. Num 61 TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low to TOUT valid CLKO ...
Page 53
... Freescale Semiconductor, Inc. Num Characteristic 75 L1RSYNC, L1TSYNC rise/fall time 76 L1RXD valid to L1CLK edge (L1RXD setup time) 77 L1CLK edge to L1RXD invalid (L1RXD hold time) 78 L1CLK edge to L1ST(1–4) valid 78A L1SYNC valid to L1ST(1–4) valid 79 L1CLK edge to L1ST(1–4) invalid 80 L1CLK edge to L1TXD valid ...
Page 54
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RXD (Input) 76 L1ST(4-1) (Output) Figure 53. SI Receive Timing Diagram with Normal Clocking (DSC = 0) 54 MPC866/859 Hardware Specifications For More Information On This Product, 70 71a 72 RFSD ...
Page 55
... Freescale Semiconductor, Inc. L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 54. SI Receive Timing with Double-Speed Clocking (DSC = 1) MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, 72 83a RFSD=1 77 BIT0 to: www.freescale.com CPM Electrical Characteristics ...
Page 56
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) 80a L1TXD BIT0 (Output) 80 L1ST(4-1) (Output) Figure 55. SI Transmit Timing Diagram (DSC = 0) 56 MPC866/859 Hardware Specifications For More Information On This Product TFSD to: www.freescale.com ...
Page 57
... Freescale Semiconductor, Inc. L1RCLK (FE=0, CE=0) (Input) 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 56. SI Transmit Timing with Double Speed Clocking (DSC = 1) MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, 72 83a 81 Go to: www.freescale.com ...
Page 58
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 58 MPC866/859 Hardware Specifications For More Information On This Product, Figure 57. IDL Timing Go to: www.freescale.com MOTOROLA ...
Page 59
... Freescale Semiconductor, Inc. 12.7 SCC in NMSI Mode Electrical Specifications Table 22 shows the NMSI external clock timings. Table 22. NMSI External Clock Timings Num Characteristic 100 RCLK1 and TCLK1 width high 101 RCLK1 and TCLK1 width low 102 RCLK1 and TCLK1 rise/fall time ...
Page 60
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics Figure 58 through Figure 60 show the NMSI timings. RCLK1 102 106 RxD1 (Input) CD1 (Input) CD1 (SYNC Input) Figure 58. SCC NMSI Receive Timing Diagram TCLK1 102 102 TxD1 (Output) 103 RTS1 (Output) 104 ...
Page 61
... Freescale Semiconductor, Inc. TCLK1 102 102 TxD1 (Output) 103 RTS1 (Output) 104 CTS1 (Echo Input) Figure 60. HDLC Bus Timing Diagram 12.8 Ethernet Electrical Specifications Table 24 shows the Ethernet timings as shown in Figure 61 through Figure 65. Num 120 CLSN width high 121 RCLK1 rise/fall time ...
Page 62
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics Table 24. Ethernet Timing (continued) Num 135 RSTRT active delay (from TCLK1 falling edge) 136 RSTRT inactive delay (from TCLK1 falling edge) 137 REJECT width low 138 CLKO1 low to SDACK asserted 139 CLKO1 low to SDACK negated 1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1 ...
Page 63
... Freescale Semiconductor, Inc. TCLK1 128 131 TxD1 (Output) 133 TENA(RTS1) (Input) RENA(CD1) (Input) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. ...
Page 64
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 12.9 SMC Transparent AC Electrical Specifications Table 25 shows the SMC transparent timings as shown in Figure 66. Table 25. SMC Transparent Timing Num Characteristic 1 150 SMCLK clock period 151 SMCLK width low 151A SMCLK width high 152 ...
Page 65
... Freescale Semiconductor, Inc. 12.10 SPI Master AC Electrical Specifications Table 26 shows the SPI master timings as shown in Figure 67 and Figure 68. Num Characteristic 160 MASTER cycle time 161 MASTER clock (SCK) high or low time 162 MASTER data setup time (inputs) 163 Master data hold time (inputs) ...
Page 66
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 68. SPI Master ( Timing Diagram 12.11 SPI Slave AC Electrical Specifications Table 27 shows the SPI slave timings as shown in Figure 69 and Figure 70. ...
Page 67
... Freescale Semiconductor, Inc. SPISEL (Input) SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 69. SPI Slave ( Timing Diagram SPISEL (Input) 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 SPIMISO msb Undef (Output) ...
Page 68
... Freescale Semiconductor, Inc. CPM Electrical Characteristics CPM Electrical Characteristics 12. Electrical Specifications 2 Table 28 shows the I C (SCL < 100 kHz) timings. Table 28. I Num Characteristic 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 Bus free time between transmissions ...
Page 69
... Freescale Semiconductor, Inc. 2 Table 29 shows the I C (SCL > 100 kHz) timings. Table 29. I Num Characteristic 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 Bus free time between transmissions 203 Low period of SCL 204 High period of SCL 205 Start condition setup time ...
Page 70
... Freescale Semiconductor, Inc. UTOPIA AC Electrical Specifications UTOPIA AC Electrical Specifications 13 UTOPIA AC Electrical Specifications Table 30 through Table 32 show the AC electrical specifications for the UTOPIA interface. Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications Num Signal Characteristic U1 UtpClk rise/fall time (Internal clock option) ...
Page 71
... Freescale Semiconductor, Inc. Figure 72 shows signal timings during UTOPIA receive operations. UtpClk U2 PHREQn RxClav HighZ at MPHY RxEnb UTPB SOC Figure 72. UTOPIA Receive Timing Figure 73 shows signal timings during UTOPIA transmit operations. UtpClk U2 5 PHSELn TxClav HighZ at MPHY TxEnb UTPB SOC Figure 73. UTOPIA Transmit Timing MOTOROLA MPC866/859 Hardware Specifi ...
Page 72
... Freescale Semiconductor, Inc. FEC Electrical Characteristics FEC Electrical Characteristics 14 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation) ...
Page 73
... Freescale Semiconductor, Inc. Table 34 shows information on the MII transmit signal timing. Table 34. MII Transmit Signal Timing Num Characteristic M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low Figure 75 shows the MII transmit signal timing diagram. ...
Page 74
... Freescale Semiconductor, Inc. FEC Electrical Characteristics FEC Electrical Characteristics 14.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 36 shows the timing for the MII serial management channel signal. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. ...
Page 75
... Temperature (Tj) Frequency (MHz) 0° to 95° 100 133 1 –40° to 100°C TBD Go to: www.freescale.com Cache Size Instruction Data 4 Kbyte 4 Kbytes 16 Kbyte 8 Kbytes 4 Kbyte 4 Kbytes 4 Kbyte 4 Kbytes Order Number MPC859DSLZP50 MPC859DSLZP66 MPC866PZP100 MPC866TZP100 MPC859PZP100 MPC859TZP100 MPC866PZP133 MPC866TZP133 MPC859PZP133 MPC859TZP133 TBD 75 ...
Page 76
... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information 15.1 Pin Assignments Figure 78 shows the top view pinout of the PBGA package. For additional information, see the MPC866 PowerQUICC Family User’s Manual. NOTE: This is the top view of the device. ...
Page 77
... Freescale Semiconductor, Inc. Table 39 contains a list of the MPC866 input and output signals and shows multiplexing and pin assignments. Name A[0:31] B19, B18, A18, C16, B17, A17, B16, A16, D15, C15, B15, A15, C14, B14, A14, D12, C13, B13, D9, D11, C12, B12, B10, B11, C11, ...
Page 78
... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name FRZ G3 IRQ6 IRQ0 V14 IRQ1 U14 M_TX_CLK W15 IRQ7 CS[0:5] C3, A2, D4, E4, A4, B4 CS6 D5 CE1_B CS7 C4 CE2_B WE0 C7 BS_B0 IORD WE1 A6 BS_B1 ...
Page 79
... Freescale Semiconductor, Inc. Table 39. Pin Assignments (continued) Name RSTCONF P3 HRESET N4 SRESET P2 XTAL P1 EXTAL N1 CLKOUT W3 EXTCLK N2 TEXP N3 ALE_A K2 MII-TXD1 CE1_A B3 MII-TXD2 CE2_A A3 MII-TXD3 WAIT_A R3 2 SOC_Split WAIT_B R4 IP_A0 T5 2 UTPB_Split0 MII-RXD3 IP_A1 T4 2 UTPB_Split1 MII-RXD2 IP_A2 U3 IOIS16_A 2 UTPB_Split2 MII-RXD1 IP_A3 W2 2 UTPB_Split3 ...
Page 80
... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name ALE_B J1 DSCK/AT1 IP_B[0:1] H2, J3 IWP[0:1] VFLS[0:1] IP_B2 J2 IOIS16_B AT2 IP_B3 G1 IWP2 VF2 IP_B4 G2 LWP0 VF0 IP_B5 J4 LWP1 VF1 IP_B6 K3 DSDI AT0 IP_B7 H1 PTR ...
Page 81
... Freescale Semiconductor, Inc. Table 39. Pin Assignments (continued) Name PA13 E17 RXD2 PA12 F17 TXD2 PA11 G16 L1TXDB RXD3 PA10 J17 L1RXDB TXD3 PA9 K18 L1TXDA RXD4 PA8 L17 L1RXDA TXD4 PA7 M19 CLK1 L1RCLKA BRGO1 TIN1 PA6 M17 CLK2 TOUT1 PA5 ...
Page 82
... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PA0 U19 CLK8 TOUT4 L1TCLKB PB31 C17 SPISEL REJECT1 PB30 C19 SPICLK RSTRT2 PB29 E16 SPIMOSI PB28 D19 SPIMISO BRGO4 PB27 E19 I2CSDA ...
Page 83
... Freescale Semiconductor, Inc. Table 39. Pin Assignments (continued) Name PB19 N19 RTS1 L1ST1 PB18 N17 2 RXADDR4 RTS2 L1ST2 PB17 P18 L1RQb L1ST3 RTS3 1 PHREQ1 2 RXADDR1 PB16 N16 L1RQa L1ST4 RTS4 1 PHREQ0 2 RXADDR0 PB15 R17 BRGO3 TxClav RxClav PB14 U18 2 RXADDR2 RSTRT1 PC15 ...
Page 84
... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PC10 K19 CD1 TGATE1 PC9 L18 CTS2 PC8 M18 CD2 TGATE2 PC7 M16 CTS3 L1TSYNCB SDACK2 PC6 R19 CD3 L1RSYNCB PC5 T18 CTS4 ...
Page 85
... Freescale Semiconductor, Inc. Table 39. Pin Assignments (continued) Name PD9 V17 RXD4 MII-TXD0 UTPCLK PD8 W17 TXD4 MII-MDC MII-RXCLK PD7 T15 RTS3 MII-RXERR UTPB4 PD6 V16 RTS4 MII-RXDV UTPB5 PD5 U15 REJECT2 MII-TXD3 UTPB6 PD4 U16 REJECT3 MII-TXD2 UTPB7 PD3 W16 REJECT4 ...
Page 86
... Freescale Semiconductor, Inc. Mechanical Data and Ordering Information Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name VDDSYN T1 GND F6, F7, F8, F9, F10, F11, F12, F13, F14, G6, G7, G8, G9, G10, G11, G12, G13, G14, H6, H7, H8, H9, H10, H11, H12, H13, H14, ...
Page 87
... Freescale Semiconductor, Inc. Note: Solder sphere composition for MPC866XZP, MPC859PZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb 2%Ag Figure 79. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, Mechanical Data and Ordering Information Go to: www.freescale.com 87 ...
Page 88
... Initial revision 1 11/2002 Added the 5-V tolerant pins, new package dimensions, and other changes. 1.1 4/2003 Added the Spec. B1d and changed spec. B1a. Added the Note Solder sphere composition for MPC866XZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb 2%Ag to Figure 15-79. 1.2 4/2003 Added the MPC859P. 1.3 5/2003 Changed the SPI Master Timing Specs. 162 and 164. ...
Page 89
... Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, Go to: www.freescale.com Document Revision History 89 ...
Page 90
... Freescale Semiconductor, Inc. Document Revision History Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK 90 MPC866/859 Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
Page 91
... Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA MPC866/859 Hardware Specifications For More Information On This Product, Go to: www.freescale.com Document Revision History 91 ...
Page 92
... HOME PAGE: www.motorola.com/semiconductors Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...