PTM1300AEBEA Philips Semiconductors, PTM1300AEBEA Datasheet

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TM-1300 Media Processor Product Specification Supersedes data of 1999 October 21 File under INTEGRATED CIRCUITS, TR1 INTEGRATED CIRCUITS 2000 May 30 ...

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... Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation products for use in such applications their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from improper use or sale. ...

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Foreword The TriMedia TM-1300 is a higher speed, functionally enhanced version of the TM-1000 media processor. TM-1300 contains an ultra-high performance Very Long Instruction Word processor, as well as a complete intelli- gent video and audio input/output subsystem. The pro- ...

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... TM1300 Data Book ii PRODUCT SPECIFICATION Philips Semiconductors ...

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Table of Contents Foreword 1 Pin List 1.1 TM1300 versus TM1100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.11 Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1 Guarding (Conditional Execution 3-5 3.2.2 Load and Store Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.3 Compute Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.4 Special-Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.5 Control-Flow Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3 TM1300 Instruction Issue Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Memory and MMIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 The Memory Hole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3 MMIO Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5 Special Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 iv PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors 3.5.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.2 EXC (Exceptions 3-9 3.5.3 INT and NMI (Maskable and Non-Maskable Interrupts 3-9 3.5.3.1 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3 ...

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... Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6.1 Example 1: Data-Cache/Input-Unit Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6.2 Example 2: Data-Cache/Output-Unit Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6.3 Example 3: Instruction-Cache/Data-Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6.4 Example 4: Instruction-Cache/Input-Unit Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6.5 Four-Way Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.6.6 LRU Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.6.7 LRU Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.6.8 LRU for the Dual-Ported Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.7 Performance Evaluation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.8 MMIO Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 6 Video In 6.1 video in overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.2 Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 vi PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors 6.1.3 Power Down and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.4 Hardware and Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6 ...

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... Clock System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.5 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.6 Memory Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.7 Audio In Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.8 Power Down and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.9 Highway Latency and HBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.10 Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.11 Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 9 Audio Out 9.1 Audio Out Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 New and Changed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.4 Summary of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 viii PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors 9.5 Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.5.1 TM1300 Standard Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.5.2 TM1000 Clock Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.6 Clock System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9 ...

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... Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.6.16 Max_Lat, Min_Gnt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7 Registers in MMIO Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.1 DRAM_BASE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.2 MMIO_BASE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.3 MMIO/DRAM_BASE updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.4 BIU_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.5 BIU_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.7.6 PCI_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.7.7 PCI_DATA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.7.8 CONFIG_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.7.9 CONFIG_DATA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.7.10 CONFIG_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.7.11 IO_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.7.12 IO_DATA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.7.13 IO_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.7.14 SRC_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.7.15 DEST_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 x PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors 11.7.16 DMA_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.7.17 INT_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.8 PCI Bus Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.8.1 Single-Data-Phase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.8.2 Multi-Data-Phase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.9 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11 ...

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... Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5.2 Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5.3 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5.4 YUV to RGB Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.5.5 Overlay and Alpha Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.5.6 Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.5.7 Implementation Overview: Horizontal Scaling and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 14.5.7.1 Loading the extra pixels in the filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.5.7.2 Mirroring pixels at the ends of a line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.5.7.3 Horizontal filter SDRAM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 xii PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors 14.5.8 Implementation Overview: Vertical Scaling and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.5.8.1 Mirroring lines at the ends of an image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 14.5.8.2 Vertical filter SDRAM block timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 14.5.9 Horizontal Scaling and Filtering for RGB Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 14 ...

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... I2C Software Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.6 I2C Hardware Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.6.1 Slave NAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.7 I2C Clock Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 17 Synchronous Serial Interface 17.1 Synchronous Serial Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.3.1 General Purpose I 17-2 17.3.2 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.3.3 SSI Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.3.4 SSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.4 SSI Transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.4.1 Setup SSI_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.4.2 Operation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 xiv PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors 17.4.3 Interrupt and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.5 SSI Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.5.1 Setup SSI_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.5.2 Operation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.5.3 Interrupt and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17 ...

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... Bus I/O device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.4.1.4 Multiple Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.5 XIO_CTL MMIO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.5.1 PCI_CLK Bus Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.5.2 Wait State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.6 PCI-XIO Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.7 PCI-XIO Bus Controller Operation and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 A DSPCPU Operations for TM1300 A.1 Alphabetic Operation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2 Operation List By Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 alloc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 allocd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 xvi PRODUCT SPECIFICATION Philips Semiconductors ...

Page 19

... Philips Semiconductors allocr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 allocx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 asl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 asli ...

Page 20

... A-49 fleqflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-50 fles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-51 flesflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-52 fmul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-53 fmulflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-54 fneq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-55 fneqflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-56 fsign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-57 fsignflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-58 fsqrt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-59 fsqrtflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-60 fsub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-61 fsubflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-62 funshift1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-63 funshift2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-64 funshift3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-65 h_dspiabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-66 h_dspidualabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-67 h_iabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-68 h_st16d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-69 h_st32d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-70 h_st8d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-71 hicycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-72 iabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-73 iadd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-74 iaddi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-75 iavgonep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-76 ibytesel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-77 iclipi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-78 iclr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-79 ident . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-80 ieql . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-81 ieqli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-82 ifir16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-83 ifir8ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-84 xviii PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors ifir8ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-85 ifixieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-86 ifixieeeflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-87 ifixrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-88 ifixrzflags ...

Page 22

... A-146 prefr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-147 quadavg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-148 quadumax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-149 quadumin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-150 quadumulmsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-151 rdstatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-152 rdtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-153 readdpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-154 readpcsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-155 readspc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-156 rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-157 roli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-158 sex16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-159 sex8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-160 st16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-161 st16d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-162 st32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-163 st32d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-164 xx PRODUCT SPECIFICATION Philips Semiconductors ...

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... Philips Semiconductors st8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-165 st8d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-166 ubytesel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-167 uclipi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-168 uclipu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-169 ueql . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-170 ueqli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-171 ufir16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-172 ufir8uu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-173 ufixieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-174 ufixieeeflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-175 ufixrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-176 ufixrzflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-177 ufloat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-178 ufloatflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-179 ufloatrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-180 ufloatrzflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-181 ugeq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-182 ugeqi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-183 ugtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-184 ugtri ...

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... C.4.2 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 C.4.3 TM1300 PCI Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 C.4.4 Image Coprocessor (ICP C-3 C.4.5 Video In (VI) and Video Out (VO) Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 C.4.6 Audio In (AI), Audio-Out (AO), and SPDIF Out (SDO) Units . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 C.4.7 Variable Length Encoder (VLD) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 C.4.8 Synchronous Serial Interface (SSI C-8 C.4.9 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9 C.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9 C.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9 Index xxii PRODUCT SPECIFICATION Philips Semiconductors ...

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Pin List by Muhammad Hafeez, Naeem Maan, Thorwald Rabeler, Luis Lucas, Gert Slavenburg 1.1 TM1300 VERSUS TM1100 The following summarizes pinout differences between TM1100 and TM1300: • TM1300 uses a BGA 27x27 package and is hence not physically pin compatible ...

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... For driving a 50-ohm trace, a resistor ohm is recommended. We recom- mend against using higher impedance traces in the SDRAM signals. Main memory address bus; used for row and column addresses (was ‘RESERVED2’ in TM1000 - also sometimes name MM_BA1) (new in TM1300 - also named MM_64M_11 in some documents) Philips Semiconductors Description Section Section 1.6. ...

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... Philips Semiconductors BGA Pad Pin Name Mode Ball Type MM_DQ00 Y20 NORM3 I/O MM_DQ01 V18 MM_DQ02 W19 MM_DQ03 W20 MM_DQ04 U18 MM_DQ05 V19 MM_DQ06 V20 MM_DQ07 T18 MM_DQ08 W18 MM_DQ09 V17 MM_DQ10 Y18 MM_DQ11 W17 MM_DQ12 Y17 MM_DQ13 W16 MM_DQ14 Y16 MM_DQ15 ...

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... Driven by TM1300 as PCI bus master to request use of the PCI bus. IN Indicates to TM1300 that access to the bus has been granted. Sustained tri-state. Parity error generated/received by TM1300. System error. This signal is asserted when operating as target and detecting an address parity error. Philips Semiconductors Description ...

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... Philips Semiconductors BGA Pad Pin Name Mode Ball Type PCI_INTA# C9 PCIOD I/OD PCI_INTB# A8 PCI I/O/OD PCI_INTC# B8 PCIOD I/OD PCI_INTD# A7 PCIOD I/OD JTAG Interface (debug access port and 1149.1 boundary scan port) JTAG_TDI F20 WEAK5 JTAG_TDO F18 WEAK5 I/O JTAG_TCK F19 WEAK5 JTAG_TMS E20 WEAK5 VI_CLK C20 ...

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... AI_WS acts as an input. AI_WS is sampled on the same edge as selected for AI_SD. • When Audio In is programmed as the serial-interface timing master, AI_WS acts as an output asserted on the opposite edge of the AI_SD sampling edge. AI_WS is the word-select or frame-synchronization signal from/to the external A/D subsystem. Philips Semiconductors Description or 384f over sam ...

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... Philips Semiconductors BGA Pad Pin Name Mode Ball Type Audio Out (always acts as sender, but can be master or slave for D/A timing) AO_OSCLK B14 STRG3 OUT AO_SCK A14 STRG5 I/O AO_SD1 B13 WEAK5 OUT AO_SD2 A13 WEAK5 OUT AO_SD3 C12 WEAK5 OUT AO_SD4 B12 ...

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... U7 D6 K17 U10 D7 K18 U11 D10 L3 U14 D11 L4 U15 D14 L17 V7 D15 L18 V10 F4 P3 V11 F17 P4 V14 G3 P17 G4 P18 Philips Semiconductors VDD (2.5V core supply) C8 H17 N17 C13 H18 N18 J17 U9 D12 M4 U12 D13 M17 U13 V13 ...

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... Philips Semiconductors 1.6 PIN REFERENCE VOLTAGE With the exception of Open Drain mode outputs, outputs always drive to a level determined by the 3.3-V I/O voltage. VREF_PERIPH and VREF_PCI purely determine input voltage clamping, not input signal thresholds or output levels. VREF_PCI determined mode PCI_AD00 PCI_AD27 PCI_AD01 PCI_AD28 ...

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... ORDERING INFORMATION To order 143-MHz v1.2 TM-1300 parts, refer to part number ‘PTM1300AEBEA’ product code 9352 6691 7557. To order 166-MHz v1.2 TM-1300 parts, refer to part number ‘PTM1300FBEA’ product code 9352 6687 1557. SOT number is 553AA1. 1-10 PRODUCT SPECIFICATION ø2.0 0.10 R 0.625X3 ø17mm (Heat Slug) 0 ...

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... Philips Semiconductors 1.9 PARAMETRIC CHARACTERISTICS 1.9.1 Operating Range and Thermal Characteristics Functional operation, long-term reliability and AC/DC characteristics are guaranteed for the operating conditions below. Symbol V Core supply voltage DD V I/O supply voltage CC T Operating case temperature range case junction to case thermal resistance jt junction to ambient thermal resistance (natural convection ...

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... Philips Semiconductors TM1300-166:133 TM1300-180:144 Pwd Typ Max Pwd Typ Max 250 1200 1350 280 1300 1450 45 165 185 50 170 190 0.7 3.5 3.8 0.8 3.8 4.1 - 900 1050 - 1000 1150 - 2.4 2.7 - 2.7 3.0 - 630 - - 690 - - 1 ...

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... Philips Semiconductors 1.9.4.2 TM-1300 Peripheral Current Consumption Details TM1300-100:100 Symbol Current/Notes Pwd running raw mode MHz I , running raw mode running raw mode DD 81 MHz I , running raw mode running raw mode MHz I , running raw mode stereo 16-bit ...

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... Figure 1-1. Figure 1-1. TM1300-143 Condition/Notes Min. Nominal 0. Figure 1-2. Figure 1-2. TM1300-143 Condition/Notes Min. Nominal 0. Figure 1-3. Figure 1-3. Condition/Notes I = -6.0 mA OUT 10 - 400 pF load Philips Semiconductors TM1300-166/180 Max Min. Nominal Max. 0.9V CC 0.1V 0. 8.5 8.5 2.0 1.6 2.0 1.6 TM1300-166/180 Max. Min. Nominal Max. 0.9V CC 0.1V 0. 4.0 3.0 4.0 3.0 TM1300-166/180 Max. Min. ...

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... Philips Semiconductors 1.9.4.7 SDRAM interface timing Symbol f MM_CLK frequency SDRAM T Skew between MM_CLK0, CLK1 CS T Propagation delay of data, address, control PD T Output hold time of data, address and control OH T Input data setup time SU T Input data hold time IH Notes: 1. For best high speed SDRAM operation, 50-ohm matched PCB traces are recommended for all MM_xxx signals. ...

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... Figure 1-9. Parameter IH-IIC IL-IIC Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Parameter Min Figure 1-16. Parameter Min Figure 1-17. Figure 1-18. Philips Semiconductors Max Units Notes 20 MHz Min. Max Units Notes 400 kHz ...

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... Philips Semiconductors 1.9.4.13 AudioIn I/O timing Symbol f Audio In AI_SCK clock frequency AI-SCK T Input setup time to AI_SCK su-SCK T Input hold time from AI_SCK h-SCK T AI_SCK to AI_WS SCK-WS Notes: 1. See the timing measurement conditions in 2. The timing measurements are done with respect to the clock edge according to CLOCK_EDGE 3 ...

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... Figure 1-7. PCI T V_th V_tl V_tfall Figure 1-8. PCI T V_trise TCK TDI, TMS Figure 1-9. JTAG Input Timing V_th TCK V_tl V_test V_max TDO Figure 1-10. JTAG Output Timing Philips Semiconductors pin 1/2 in. max Output Buffer (max) Rising Edge val pin 1/2 in. max Output Buffer Vcc ...

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... Philips Semiconductors T T HIGH LOW SCL Figure 1-11 I/O Timing SCL T TBUF SDA 2 Figure 1-12 I/O Timing SCL T su_STA SDA 2 Figure 1-13 I/O Timing SCL T su_SDA valid SDA 2 Figure 1-14 I/O Timing SCL T dv_SDA valid SDA 2 Figure 1-15 I/O Timing VI_CLK T r VI_DATA, VI_IO Figure 1-16. VideoI n I/O Timing ...

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... Figure 1-21. Audio Out I/O Timing AO_SCK AO_WS Figure 1-22. Audio Out I/O Timing AO_SCK T su_SCK valid AO_WS Figure 1-23. Audio Out I/O Timing 1-20 PRODUCT SPECIFICATION SSI_CLK T SCK_DV valid SSI I/O Figure 1-24. SSI I/O Timing SSI_CLK T SCK_WS valid SSI_IO Figure 1-25. SSI I/O Timing T h_SCK Philips Semiconductors T CLK_DV valid T T su_CLK h_CLK valid ...

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Overview 2.1 INTRODUCTION TM1300 is a successor to the TM1100 and TM1000 me- dia processors. For those familiar with the TM1100, the new features specific to the TM1300 are summarized in Section 2.6. For those familiar with the TM1000, new ...

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... DMA-driven multimedia coprocessors that operate independently and in parallel with the DSPCPU to perform operations specific to important multimedia algorithms. 2-2 PRODUCT SPECIFICATION Philips Semiconductors 2Mx32 SDRAM CCIR656 digital video stereo ADC audio in ...

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... Philips Semiconductors 2.4 BRIEF EXAMPLES OF OPERATION The key to understanding TM1300 operation is observ- ing that the DSPCPU and peripherals are time-shared and that communication between units is through SDRAM memory. The DSPCPU switches from one task to the next; first it decompresses a video frame, then it decompresses a slice of the audio stream, then back to video, etc ...

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... CCIR656 digital video data stream that contains a composited video and graphics overlay image. The vid- 2-4 PRODUCT SPECIFICATION Philips Semiconductors eo image is taken from separate Y, U, and V planar data structures in SDRAM. The graphics overlay is taken from a pixel-packed YUV data structure in SDRAM. Compos- iting allows both alpha-blending and chroma keying ...

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... Philips Semiconductors PC Screen FrameMaker 5 File Edit Format View IMAGE 1 Calendar File Edit Image 2 Image 1 Figure 2-3. ICP - Windows on the PC screen and data structures in SDRAM for two live video windows. Figure 2-3 illustrates a possible display situation and the data structures in SDRAM that support ICP operation. ...

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... I C peripheral devices, such as video decoders, video encoders and some camera types. 2-6 PRODUCT SPECIFICATION Philips Semiconductors 2.6 NEW IN TM1300 (VERSUS TM1100) TM1300 offers significant improvements over the TM1100: • DSPCPU and coprocessor speed 166 MHz • Support for 64-Mbit organized in x8 (limited to 32 MBytes), x16, x32 and 128 Mbit organized in x16 (limited to 32 MB) ...

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DSPCPU Architecture 3.1 BASIC ARCHITECTURE CONCEPTS This section documents the system programmer or ‘bare-machine’ view of the TM1300 CPU (or DSPCPU). 3.1.1 New in TM1300 Default reset value of PCSW register is 0x800. This new reset value allows Audio Out ...

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... Byte sex (1 little endian) Yes) allow interrupts TFE Trap on first exit Philips Semiconductors shows the PCSW register. The TM1300 value dspiadd ifloatrz in Appendix A, “DSPCPU Op- Section 3.5, Section 3.5. IFZ ...

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... Philips Semiconductors Table 3-2. PCSW FP exception flag definitions Flag Function INV Standard IEEE invalid flag OVF Standard IEEE overflow flag UNF Standard IEEE underflow flag INX Standard IEEE inexact flag DBZ Standard IEEE divide-by-zero flag OFZ ‘Output flushed to zero’ set if an operation caused a ...

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... Software Compatibility are support- The DSPCPU architecture expressly does not support binary compatibility between family members. The ANSI C compiler ensures that all family members are compat- ible at the source-code level. Philips Semiconductors Representation 0x7f800000 0xff800000 argument | 0x00400000 (forcing the NaN to be quiet) ...

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... Philips Semiconductors 3.2 INSTRUCTION SET OVERVIEW 3.2.1 Guarding (Conditional Execution) In the TM1300 architecture, all operations can be option- ally 'guarded'. A guarded operation executes conditional- ly, depending on the value in the ‘guard' register. For ex- ample, a guarded add is written as: IF R23 iadd R14 R10 R13 This should be taken to mean if R23 then R13 R14 + R10 ...

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... CONST ALU ALU FCOMP DSPMUL BRANCH IFMUL DSPALU Philips Semiconductors Section 3.5, “Special Event Handling”). Appendix A, “DSPCPU Opera- TM1300.”) issue slot 4 issue slot 5 CONST CONST ALU ALU DMEM ...

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... Philips Semiconductors • functional units should be ‘recovered’ from any prior operation issues Writeback constraint: • No more than 5 results should be simultaneously written to the register file at any point in time (write- back occurs ‘latency’ cycles after issue) Figure 3-3 shows all functional units of TM1300, includ- ing the relation to issue slots, and each functional unit’ ...

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... Philips Semiconductors The instruction and Section 3.9, “Debug 3-9, ordered by priority. Vector data breakpoints systimer timer3 timer2 timer1 intvec31 intvec30 ...

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... Philips Semiconductors The instruction scheduler uses interruptible jumps exclu- sively for inter-decision tree jumps. Hence, within a deci- sion tree, no special-event processing can be initiated tree-to-tree jump is taken, special-event processing is allowed. Since the only registers live at this point (i.e., that contain useful data) are the global registers allocat the ANSI C compiler, only a subset of the registers needs to be preserved by the event handlers ...

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... MP30 MP29 MP28 MP23 MP22 MP21 MP20 MP15 MP14 MP13 MP12 MP7 MP6 MP5 MP4 source operates in edge-triggered mode source operates in level-sensitive mode Philips Semiconductors Interrupt priorities Interrupt masking Figure 3-8) allows MP27 MP26 MP25 MP24 MP19 MP18 MP17 MP16 ...

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... Philips Semiconductors device events lead to the request of an interrupt. In addi- tion, the PCSW.IEN flag determines whether the DSPCPU is willing to handle regular interrupts. Non maskable interrupts ignore the state of this flag. All three mechanisms are necessary: the PCSW.IEN flag is used to implement critical sections of code during which the RTOS (real-time operating system) is unable to handle regular interrupts ...

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... Loading a new modulus does not affect the contents of the value register store operation to either the mod- ulus or value register results in value and modulus being the same, no interrupt will be generated. If the run bit is set, the next value will be modulus+1 or modulus+2, and Philips Semiconductors ...

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... Philips Semiconductors Timer base offset: 0 TMODULUS (r/w) 4 TVALUE (r/w) 8 TCTL (r/w) Figure 3-10. Timer register definitions. Table 3-11. Timer base MMIO address TIMER1 MMIO_BASE+0x10,0C00 TIMER2 MMIO_BASE+0x10,0C20 TIMER3 MMIO_BASE+0x10,0C40 SYSTIMER MMIO_BASE+0x10,0C60 Table 3-12. Timer source selections Source Source Name Bits Source Description Value CLOCK 0 CPU clock PRESCALE 1 prescaled CPU clock ...

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... DVC = ‘1’ and (data & BDATAMASK) != (BDATAVAL & BDATAMASK ‘DAC’ Data Address Control: 0 Breakpoint if address inside range 1 Breakpoint if address outside range ‘BL’ Break on Load: 0 Don’t check data loads 1 Do check data loads Philips Semiconductors daddr high ...

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... Philips Semiconductors Note: use a nonzero datamask or the result is undefined. When a successful comparison has taken place, a data breakpoint event is generated, which can be used as a clock input to a timer. After counting the set number of data breakpoint events, the timer will generate an inter- rupt request. ...

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... TM1300 Data Book 3-16 PRODUCT SPECIFICATION Philips Semiconductors ...

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Custom Operations for Multimedia 4.1 CUSTOM OPERATIONS OVERVIEW Custom operations in the TM1300 DSPCPU architecture are specialized, high-function operations designed to dramatically improve performance in important multime- dia applications. When properly incorporated into appli- cation source code, custom operations enable ...

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... Description (0..255). Table 4-2. Key Multimedia Custom Operations Listed by Operand Size Op. Size 32-bit 16-bit Philips Semiconductors Custom Op Description dspiabs Clipped signed 32-bit abs value dspiadd Clipped signed 32-bit add dspuadd Clipped unsigned 32-bit add ...

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... Philips Semiconductors Table 4-2. Key Multimedia Custom Operations Listed by Operand Size Op. Size Custom Op 8-bit quadumax Unsigned bytewise quad max quadumin Unsigned bytewise quad min dspuquadaddui Quad clipped add of unsigned/ signed bytes ifir8ii Signed sum of products of signed bytes ifir8iu Signed sum of products of signed/unsigned bytes ufi ...

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... IDCT results are assumed to have been computed into idct[]. mergemsb pack16msb mergemsb pack16lsb mergelsb pack16msb mergelsb pack16lsb Philips Semiconductors . . . = PACK16MSB(temp0, temp1); = PACK16LSB(temp0, temp1); = PACK16MSB(temp2, temp3); = PACK16LSB(temp2, temp3 Figure 4-1 Column Major a ...

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... Philips Semiconductors void reconstruct (unsigned char *back, { int i, temp; for ( < 64 temp = ((back[i] + forward[ >> idct[i]; if (temp > 255) else if (temp < 0) destination[i] = temp Figure 4-4. Straightforward code for MPEG frame reconstruction. A straightforward coding of the reconstruction algorithm might look as shown in Figure 4-4 ...

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... Figure 4-8 C-language notation. The compiler and scheduler take care of the rest. Philips Semiconductors Figure 4-4. illustrates several aspects of us- ...

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... Philips Semiconductors void reconstruct (unsigned char *back, { int i, temp0, temp1, temp2, temp3; for ( < 64 temp0 = ((back[i+0] + forward[i+ >> 1); temp1 = ((back[i+1] + forward[i+ >> 1); temp2 = ((back[i+2] + forward[i+ >> 1); temp3 = ((back[i+3] + forward[i+ >> 1); temp0 += idct[i+0]; if (temp0 > 255) temp0 = 255; else if (temp0 < 0) temp0 = 0; ...

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... Philips Semiconductors 4-9. shows the loop of Figure 4-9 Figure 4-11 shows a more parallel Figure 4-10. By simply giving ...

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... Philips Semiconductors unsigned char A[16][16]; unsigned char B[16][16 for (row = 0; row < 16; row += 1) { for (col = 0; col < 16; col += 4) { cost0 = abs(A[row][col+0] – B[row][col+0]); cost1 = abs(A[row][col+1] – B[row][col+1]); cost2 = abs(A[row][col+2] – B[row][col+2]); cost3 = abs(A[row][col+3] – B[row][col+3]); ...

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... UME8UU(IA[2], IB[2]); cost3 = UME8UU(IA[3], IB[3]); cost4 = UME8UU(IA[4], IB[4]); cost5 = UME8UU(IA[5], IB[5]); cost6 = UME8UU(IA[6], IB[6]); cost7 = UME8UU(IA[7], IB[7]); cost += cost0 + cost1 + cost2 + } Figure 4-16. Code from array index calculations. Philips Semiconductors shows one way to modify the code for sim- cost3 + cost4 + cost5 + cost6 + cost7; Figure 4-12. This . . . cost3 + cost4 + cost5 + cost6 + cost7 ...

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Cache Architecture 5.1 MEMORY SYSTEM OVERVIEW The high-performance video and audio throughput of TM1300 is implemented by its DSPCPU and autono- mous I/O and co-processing units, but the foundation of this processing is the TM1300 memory hierarchy. To get the ...

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... DRAM aperture starting at address 0x0). The boot pro- cess described in these initial settings DRAM_BASE_FIELD DRAM_LIMIT_FIELD Philips Semiconductors Figure Chapter 11, “PCI Interface.” In normal oper- and Chapter 13, for a description of this process. address < [DRAM_LIMIT] Chapter 13, “System Boot,” overrides 15 11 ...

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... Philips Semiconductors 5.3 DATA CACHE The data cache serves only the DSPCPU and is con- trolled by two memory units that execute the load and store operations issued by the DSPCPU. The following sections describe the data cache and its operation; Table 5-3 summarizes the important characteristics for easy reference ...

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... The LRU status of any set that contains locked blocks is set to the initialization value. 4. Cache locking is activated so that the locked blocks cannot be victims of the replacement algorithm. This sequence of events is triggered by writing ‘1’ to DC_LOCK_ENABLE even if the enable is already set to Philips Semiconductors Cache Locking by the MMIO Figure 5-5 ...

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... Philips Semiconductors MMIO_BASE offset: 0x10 0010 DC_LOCK_CTL (r/w) 0x10 0014 DC_LOCK_ADDR (r/w) 0x10 0018 DC_LOCK_SIZE (r/w) Figure 5-5. Formats of the registers in charge of data-cache locking. ‘1’. Setting DC_LOCK_ENABLE to ‘0’ causes no action except to allow the previously locked blocks to be re- placement victims. To program a new lock range, the following sequence of operations is used: 1. Disable cache locking by writing ‘ ...

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... Bit Definitions,” VALID DIRTY Philips Semiconductors Table 5-8. Description Read data-cache tag. The target address selects a data-cache block directly; the operation returns a 32-bit result containing the 21-bit cache tag and the valid bit. ...

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... Philips Semiconductors 5.3.10.3 Data cache allocation operation The data cache controller recognizes allocation opera- tions as shown in Table 5-9. The allocation operations al- locate a block and set the status of this block to valid. No data is fetched from main memory. The allocated block is undefined after this operation. The programmer has to fill it with valid data by store operations ...

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... Table 5-13 Table 5- BLOCKSIZE Philips Semiconductors TM1300 Implementation 32 KB 8-way set-associative 64 bytes One valid bit per 64-byte block among the eight blocks in a set Branch delay is three cycles Software uses a special operation to ...

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... Philips Semiconductors Table 5-13. Instruction Address Field Partitioning Address Field Purpose Bits Offset 5..0 Byte offset into a set Set 11..6 Selects one of the sets in the cache (one the case of TM1300) Tag 31..12 Compared against address tags of set members 5.4.3 Miss Processing Order When a miss occurs, the instruction cache starts filling the requested block from the beginning of the block ...

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... IC_LOCK_ADDRESS Philips Semiconductors Instruction Cache Initialization and Boot Sequence TAG_I_MUX SET 0 0 SET ...

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... Philips Semiconductors 1. The stall signal is asserted to prevent activity in the DSPCPU and data cache. 2. The valid bits for all blocks in the instruction cache are reset the completion of the block invalidation scan, the stall signal to the DSPCPU and data cache are deas- serted ...

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... CACHE1 and/or CACHE2, as described in Section 3.8, “Timers.” tracked simultaneously by using 2 timers. The MMIO register MEM_EVENTS determines which events are counted. See MEM_EVENTS. tracked and MEM_EVENTS fields. Event1 selects the actual source 2_way[0] 0 Philips Semiconductors LRU bit 2 LRU bit 1 LRU bit 0 R[3,2] R[3,1] R[3, ...

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... Philips Semiconductors for the TIMER CACHE1 source. Event2 selects the source for TIMER CACHE2. Table 5-14. Trackable cache-performance events Encoding Event 0 No event counted 1 Instruction-cache misses 2 Instruction-cache stall cycles (including data- cache stall cycles if both instruction-cache and data-cache are stalled simultaneously) 3 Data-cache bank conflicts ...

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... TM1300 Data Book 5-14 PRODUCT SPECIFICATION Philips Semiconductors ...

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Video In 6.1 VIDEO IN OVERVIEW The Video In (VI) unit provides the following functions: • Digital video input from a digital camera or analog camera (using a video decoder). • High-bandwidth (81 MB/sec) raw input data channel. • Direct ...

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... VI_STATUS, and VI_CLOCK registers are set to all ’0’s. The state of the other registers after RESET is unde- fined. Note that the VI clock has to be present while ap- plying the software reset. Termination & Receivers Cable Connector Philips Semiconductors TM1300 VI_DATA[9:8] GND VI_DATA[7:0] logic ‘1’ VI_DVALID VI_CLK ...

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... Philips Semiconductors TM1300 1 VO_DATA[7:0] (STMSG) VO_IO1 (ENDMSG) VO_IO2 VO_CLK Figure 6-2. VI unit connected to an EVO unit of another TM1300. Analog video 1–2 S-VHS Y/C 1–4 CVBS Figure 6-3. VI unit connected to a video decoder. Analog video Figure 6-4. VI connected to a 10-bit video A/D converter. 6.2 CLOCK GENERATOR The VI block can operate in two distinct clocking modes, ...

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... • • • Active area Philips Semiconductors – – – ...

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... Philips Semiconductors Figure 6-8. Format of CCIR656 SAV and EAV timing reference codes. Figure 6-9. VI capture parameters. VI_CTL.SC=1: ‘Interspersed sampling’ serves to gen- erate a sampling structure in memory where chromi- nance samples are spatially midway between luminance samples, as shown in Figure 6-6. This ‘interspersed’ for- mat is suitable for use in MPEG-1 encoding. The VI hardware applies a (– ...

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... Modifications to Y_DELTA, 1. Four clocks for each C luminance pixels 2. Note that consecutive pixel components of each line are stored in consecutive memory addresses but con- secutive lines need not be in consecutive memory ad- dresses Philips Semiconductors U_DELTA, V_BASE_ADR See Figure 6-10. ,Y,C ,Y group representing two ...

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... Philips Semiconductors Y_BASE_ADR Y_DELTA U_BASE_ADR U_DELTA Figure 6-10. VI YUV 4:2:2 planar memory format. U_DELTA and V_DELTA do affect the next horizontal re- trace. Hence, under normal circumstances, the DELTA variables should not be changed during capture. When capture is complete, i.e. any internal VI buffers have been flushed and the entire captured image is in lo- cal SDRAM, VI raises the STATUS register flag CAP- TURE COMPLETE ...

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... W/2–1 WIDTH/4 pixels pix0 pix2 • • • (Repeated for V_BASE_ADDR, V_DELTA) Philips Semiconductors CUR_X(12) FIELD2 Capture complete MODE Threshold reached INT enable Capture complete INT enable Threshold reached ACK (write ‘1’ to ACK) ...

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... Philips Semiconductors YUV 4:2:2 CCIR656 input samples Halfres capture sample results Figure 6-13. Halfres co-sited sample capture. YUV 4:2:2 CCIR656 input samples Halfres capture sample results Figure 6-14. Halfres interspersed sample capture. 6.4 HALFRES CAPTURE MODE Halfres capture mode is identical in operation to fullres capture mode except that horizontal resolution is re- duced by a factor of two on both luminance and chromi- nance data ...

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... SIZE registers once capture has started. Modifications of BASE or SIZE, therefore, have no effect until the start of the next use of the corresponding buffer. Note also that the VI_BASE1 and VI_BASE2 addresses must be 64-byte aligned (the six LSBs are always ‘0’). Philips Semiconductors ...

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... Philips Semiconductors RESET ACK2 Figure 6-16. VI raw mode major states. VI_DATA[7:0] XX VI_DATA[8] Start of message VI_DATA[9] VI_CLK Figure 6-17. VI message passing signal example. 6.6 MESSAGE-PASSING MODE In this mode, VI receives 8-bit message data over the VI_DATA[7:0] pins. The message data is written in packed form (four 8-bit message bytes per 32-bit word) to SDRAM ...

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... VI clock frequency (in MHz). Table 6-4. VI highway latency requirements (27-MHz data rate, 100-MHz TM1300 highway clock) Mode fullres capture halfres capture raw8 raw10s raw10u message passing Philips Semiconductors BUF1FULL BUF2FULL raise OVERRUN* Section 6.6) Max latency setting Formula (27 MHz, 100 MHz) 237 ...

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... Philips Semiconductors In fullres mode, bandwidth requirements (in bytes) per video line with active image for VI is: • ceil(WIDTH*2/256 fullr ceil(X) function is the least integral value greater than or equal halfres mode, the bandwidth is: • ceil(WIDTH*2/512 halfr Raw8 mode and message passing mode bandwidth de- pends only on VI clock speed ...

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... TM1300 Data Book 6-14 PRODUCT SPECIFICATION Philips Semiconductors ...

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Enhanced Video Out 7.1 ENHANCED VIDEO OUT SUMMARY The TM1300 Enhanced Video Out (EVO) improves on the design of the TM1000 Video Out (VO) unit while maintaining binary-compatibility. TM1300 EVO is fully backward compatible with TM1100, and has been ex- ...

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... GS9022 Digital Video Serializer or similar part (not shown). TM1300 VO_DATA[7:0] VO_CLK Figure 7-2. EVO connected to a CCIR 656 video- output connector. Figure 7-3 shows the EVO unit of one TM1300 connect the VI unit of a second TM1300. Philips Semiconductors 7-1, and Figure 7-2 illustrate typical MP[7:0] RCV1 RCV2 SAA7125 LLC CCIR 656 Subminiature “ ...

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... Philips Semiconductors TM1300 A VO_DATA[7:0] (STMSG) VO_IO1 (ENDMSG) VO_IO2 VO_CLK logic ‘1’ Figure 7-3. EVO unit connected to the VI unit of a second TM1300. Table 7-1. EVO unit interface pins Signal Name Type Description VO_DATA[7:0] OUT CCIR 656-style YUV 4:2:2 digital out- put data, or general-purpose high speed data output channel ...

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... SAV code indicates start of active video for the current line. Displayed Image Scan Direction Philips Semiconductors shows a timing diagram of NTSC-compatible CCIR 656 Pixel Timing 7-10. Pixels are generated in groups of CCIR 656 Line Timing Figure 7-11 ...

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... Philips Semiconductors Field Video Lines Vertical Blanking Sync 1/2 Line Interlace Offset Figure 7-9. Interlaced timing—NTSC analog sync. signals. Byte 0 VO_DATA[0: VO_CLK Figure 7-10. CCIR 656 pixel timing. SAV, EAV Codes E S Blanking Active Video Line i Figure 7-11. CCIR 656 line timing. ...

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... CCIR 656 line numbering. The Image Line Comments Figure 7-13. Active Video Area and Image Area in re- lation to vertical and horizontal blanking intervals. Philips Semiconductors Figure 7-13. The frame includes 7-13, the active video area begins after Frame ...

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... Philips Semiconductors Counter and Image Pixel Counter define the visible im- age within the field. The geometry of the active video area is defined by the contents of several MMIO registers Figure 7-29. The VO_FRAME.FIELD_2_START field defines the start line of Field 2. Field 2 is active when the Field Line Counter contents equal or exceed this value. ...

Page 112

... VO_IO2 timing, the EVO will appear to start the first byte of the first line just after the VO_IO2 active signal. Figure 7-16. 7.11 DATA TRANSFER TIMING In data-streaming and message-passing modes, the EVO supplies a stream of 8-bit data. No data selection or Philips Semiconductors Field 282 283 525 1 623 624 625 1 ...

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... Philips Semiconductors Image Data Line 525/625 EAV VO_IO2 Delay SLAVE_DLY in VO_CLK cycles Figure 7-16. Genlock mode. VO_DATA[7:0] XX VO_IO2 VO_IO1 VO_CLK Figure 7-17. Data-streaming valid data signals. VO_DATA[7: VO_IO1 Start of message VO_IO2 VO_CLK Figure 7-18. Message-passing START and END signals. data interpretation is done, and data is transferred at the rate of one byte per VO_CLK ...

Page 114

... PRODUCT SPECIFICATION Chrominance (U,V) Luminance samples samples Chrominance (U,V) Luminance samples samples Chrominance (U,V) Luminance samples samples Y0 OL_BASE_ADR OL_OFFSET Figure 7-23. YUV 4:2:2+alpha overlay format. Appendix C, “En- Philips Semiconductors YUV 4:2: OVERLAY_WIDTH pixels pix pix0 pix1 pix2 • • • W–1 ...

Page 115

... Philips Semiconductors Input Pixels: YUV Output Pixels: YU’V’ Figure 7-24. YUV interspersed to co-sited conversion. U0,0; V0,0 Y0,0 Input Pixels: YUV 4:2:0 Y0,0; U0,0; V0,0 Output Pixels: YU’V’ 4:2:2 Figure 7-25. YUV 4:2:0 to YUV 4:2:2 co-sited conversion. 7.13 VIDEO IMAGE CONVERSION ALGORITHMS The memory video image data formats are converted to the output YUV 4:2:2 co-sited format and optionally up- scaled 2 horizontally ...

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... As Input Pixel: Y’U’V’ = YUV Input Pixels: Y’ = (-3,19,19,-3)/32 Y Chrominance (U,V) Luminance samples samples Y Co-sited Chrominance Output U’,V’ = (–1,13,5,–1)/16 U,V Philips Semiconductors Figure shows an example of six pixels upscaled to Upscaled Chrominance Output Between Input Pixels: U’,V’ = (-3,19,19,-3)/32 Upscaled Luminance Output Same As Input Pixel: Y’ 7-26. U,V ...

Page 117

... Philips Semiconductors 1 Input Pixels Output Pixels: Y’ Y’=Y1 Y’=F(Y1,Y1,Y2,Y3) Figure 7-28. Mirroring pixels in 2x upscaling. 7.14 EVO OPERATING MODES EVO operating modes belong to two groups as follows: • Video-refresh modes • Data-transfer modes Data-transfer modes are further broken down into data- streaming mode and message-passing mode. ...

Page 118

... In the TM1000, this bit is a copy of the HBE flag (VO_STATUS[5]). In the EVO unit hard-wired to ‘1’. Software can use this bit to determine the type of (E)VO bit then reading VO_STATUS[4]. If the bit remains ‘1’, the unit is an EVO. Philips Semiconductors in the LOWER_CLIPUV Figure 7-29. VO MMIO Section 7 ...

Page 119

... Philips Semiconductors MMIO_BASE offset: 0x10 1800 VO_STATUS (r) 0x10 1804 VO_CTL (r/w) RESET SLEEPLESS CLOCK_SELECT PLL_S 0x10 1808 VO_CLOCK (r/w) 0x10 180C VO_FRAME (r/w) 0x10 1810 VO_FIELD (r/w) 0x10 1814 VO_LINE (r/w) 0x10 1818 VO_IMAGE (r/w) 0x10 181C VO_YTHR (r/w) 0x10 1820 VO_OLSTART (r/w) 0x10 1824 VO_OLHW (r/w) 0x10 1828 VO_YADD (r/w) ...

Page 120

... CCIR 656 line defini- tions are used. 7.16.4 EVO Control Register (EVO_CTL) New TM1300 EVO features are enabled by setting the 7-16 PRODUCT SPECIFICATION Philips Semiconductors Description 7.16.3.2 Recommended values for timing registers The recommended values for the various fields of the timing registers are shown in Table 7-10 625/50 timing cases ...

Page 121

... Philips Semiconductors 525 Line / Blanking: Field 2 Overlap 4 Blanking: Field 1 20 Video Image: Field 1 264 Blanking: Field 1 Overlap 266 Blanking: Field 2 283 Video Image: Field 2 525 Figure 7-30. EVO frame timing. Table 7-6. VO_CTL register fields Field RESET Software reset of the EVO. The recommended software reset procedure is as follows. ...

Page 122

... Note: De-asserting VO_ENABLE in video-refresh modes causes SDRAM reads to stop, but sync framing and BFR1_EMPTY generation and interrupts remain fully operational. The transmitted active image data is undefined in this case. To fully halt video output, a software reset is required. 7-18 PRODUCT SPECIFICATION Philips Semiconductors Description Table 7-4 on page 7-13. Appendix C, “Endian-ness,” ...

Page 123

... Philips Semiconductors Table 7-7. VO register fIelds Register Field VO_CLOCK FREQUENCY VO_FRAME FRAME_LENGTH FIELD_2_START FRAME_PRESET VO_FIELD F1_VIDEO_LINE F2_VIDEO_LINE F1_OLAP F2_OLAP VO_LINE FRAME_WIDTH VIDEO PIXEL START Pixel number in Frame Pixel Counter of starting pixel of active video area within the line VO_IMAGE IMAGE_HEIGHT IMAGE_WIDTH VO_YTHR ...

Page 124

... Lastly, software sets RESERVED MASK_Y MASK_UV HIGHER_CLIPUV LOWER_CLIPUV RESERVED KEY_V RESERVED Philips Semiconductors 7.15.2). Figure 7-31, and their reg- Table 7- GENLOCK FULL_BLENDING CLIPPING_ENABLE SYNC_STREAMING FIELD_SYNC KEY_ENABLE EVO_ENABLE RESERVED ...

Page 125

... Philips Semiconductors Table 7-8. EVO_CTL Register Fields Register Field EVO_CTL EVO_ENABLE When set to 1, new EVO features are enabled. When set to 0 (the hardware reset value), the EVO behaves exactly like a TM1000 VO unit. Default: 0. FULL_BLENDING Activates full 8-bit alpha blending when set to 1. When set to 0, only the original five TM1000 blending levels are implemented (0%, 25%, 50%, 75%, 100%) ...

Page 126

... DSPCPU updates the pointer to the next buffer before the EVO starts transferring data from the next table. 1. Note that consecutive pixel components of each line are stored in consecutive memory addresses but con- secutive lines need not be in consecutive memory ad- dresses Philips Semiconductors also supported by setting Figure 7-22. ...

Page 127

... Philips Semiconductors Note: In this mode, SYNC_MASTER must be set to en- sure correct operation of VO_IO1 and VO_IO2 as out- puts. When each buffer has been transferred, the correspond- ing buffer-empty bit is set in the status register, and the DSPCPU is interrupted if the buffer-empty interrupt is en- abled. To maintain continuous transfer of data, the DSPCPU supplies new pointers for the next data buffer following each buffer-empty interrupt ...

Page 128

... The PLL filter block is shown in Phase Loop Detect Filter div T+1 PLL_T 1. Assign a DDS frequency. This starts the DDS. Allow for at least 31 DSPCPU cycles for the DDS frequency setting to take effect. Philips Semiconductors W W ceil ( -------- - ) + ceil ( -------- - ...

Page 129

... Philips Semiconductors 2. Choose a value for PLL_S and PLL_T. For 8-40 MHz operation, a value of 1 (which selects division recommended. 3. Choose a value for CLOCK_SELECT. For 8-81 MHz operation, CLOCK_SELECT = 00 is recommended. 4. Assign values to the VO_CTL register containing the above choices. The first assignment with CLOCK_SELECT not equal to 0x3 enables the PLL system ...

Page 130

... TM1300 Data Book 7-26 PRODUCT SPECIFICATION Philips Semiconductors ...

Page 131

Audio In 8.1 AUDIO IN OVERVIEW The TM1300 Audio In (AI) unit connects to an off-chip stereo A/D converter subsystem through a flexible bit-se- rial connection. The AI unit provides all signals needed to interface to high quality, low cost ...

Page 132

... Audio Out (AO) unit clock system DDS is used to provide a single master A/ D and D/A clock. The AO unit, or the D/A converter, can be used as serial interface timing master, and the AI unit is set to be slave to the serial frame determined by AO Philips Semiconductors Square Wave DDS 31 FREQUENCY 32 ...

Page 133

... Philips Semiconductors (AI SER_MASTER=0, AI_SCK and AI_WS externally wired to the corresponding AO pins). In such systems, in- dependent software control over A/D and D/A sampling rate is not possible, but component count is minimized. Table 8-3.AI MMIO clock & interface control bits Field Name Description SER_MASTER 0 (RESET default), the A/D converter is the timing master over the serial inter- face ...

Page 134

... Philips Semiconductors left (18) n+1 Figure 8-3, use the settings of with SSPOS set to ‘4’. This results in Figure 8-4. Successive samples are always Appendix C, “Endian-ness,” Section 8.7 for details on hardware/ ...

Page 135

... Philips Semiconductors MMIO_base offset: 0x10 1C00 AI_STATUS (r/w) 0x10 1C04 AI_CTL (r/w) RESET CAP_ENABLE CAP_MODE SIGN_CONVERT LITTLE_ENDIAN 0x10 1C08 AI_SERIAL (r/w) SER_MASTER DATAMODE FRAMEMODE CLOCK_EDGE 0x10 1C0C AI_FRAMING (r/w) POLARITY 0x10 1C10 AI_FREQ (r/w) 0x10 1C14 AI_BASE1 (r/w) 0x10 1C18 AI_BASE2 (r/w) 0x10 1C1C AI_SIZE (r/w) Figure 8-5. AI status/control field MMIO layout. ...

Page 136

... If ‘1’, buffer 1 is full. If BUF1_INTEN is also ‘1’, an interrupt request (source 11) is pending. BUF1_FULL is cleared by writing a ‘1’ to ACK1, at which point the AI hard- ware will assume that BASE1 and SIZE describe a new empty buffer. • 0 after RESET. Philips Semiconductors , and an associated sam- s Chapter 20, “Ar- max T arbiter ...

Page 137

... Philips Semiconductors Table 8-8. AI MMIO status fields (read only) Field Name Description BUF2_FULL • If ‘1’, buffer 2 is full. If BUF2_INTEN is also ‘1’, an interrupt request (source 11) is pending. BUF2_FULL is cleared by writing a ‘1’ to ACK2, at which point the AI hard- ware will assume that BASE2 and SIZE describe a new empty buffer. • ...

Page 138

... TM1300 Data Book 8-8 PRODUCT SPECIFICATION Philips Semiconductors ...

Page 139

Audio Out 9.1 AUDIO OUT OVERVIEW The TM1300 Audio Out (AO) unit is new and contains many features not available in the TM1100. It has channels, and drives external stereo D/A con- verters through ...

Page 140

... Table 9-2. Clock system setting ( 44.1 kHz 48.0 kHz 44.1 kHz 48.0 kHz 7 0 div N+1 SCKDIV 9 DSPCPUCLK 8 0 div N+1 WSDIV SER_MASTER 16 LEFT[15:0] 16 RIGHT[15:0] 32 AO_CC[31:0] Philips Semiconductors system clock source for oversampling D OSCLK = 2 + ------------------------------- - 9 f DSPCPU =133 MHz) DSPCPU OSCLK SCK FREQUENCY SCKDIV 256fs 64fs 2187991971 ...

Page 141

... Philips Semiconductors AO_SCK AO_WS AO_SDx frame n-1 Figure 9-2. Definition of serial frame bit positions (POLARITY = 1, CLOCKEDGE = 0) 9.5.2 TM1000 Clock Compatibility Mode TM1000 clock compatibility mode is provided so that TM1000 audio software runs without changes. It should NOT be used for new software development, due higher jitter ...

Page 142

... Due to the implementation, there is a minimum serial frame length required that is operating mode dependent. This is shown in Table 9-6. Minimum serial frame length in bits operating mode 16 bits/sample, mono 32 bits/sample, mono 16 bits/sample, stereo Table 9-9. 32 bits/sample, stereo Philips Semiconductors Table 9-5. shows valid first last SSPOS bit bit values S[15] S[SSPOS] 0 ...

Page 143

... Philips Semiconductors AO_SCK AO_WS AO_SDx left channel data (18) n Figure 9-3. Serial frame (64 bits 18-bit precision I 2 9.7 Serial Framing Example Refer to Figure 9-3 and Table 9-7 to see how the AO unit MMIO registers should be set to transmit bits of 2 stereo data via serial standard to an 18-bit D/A converter with a 64-bit serial frame ...

Page 144

... SD1.left SD1.right SD1.left n n+1 n+1 adr+4 adr+6 adr+8 SD2.left SD2.right SD3.left adr+4 SD1.right n Philips Semiconductors CC2(16) (16) lsb lsb left data n locations. The setting for details on byte ordering con- Figure 9-6. Refer to for details on hard- adr+10 adr+12 adr+14 SD1 ...

Page 145

... Philips Semiconductors MMIO_base offset: 0x10 2000 AO_STATUS (r/w) 0x10 2004 AO_CTL (r/w) RESET TRANS_ENABLE TRANS_MODE SIGN_CONVERT LITTLE_ENDIAN 0x10 2008 AO_SERIAL (r/w) SER_MASTER DATAMODE CLOCK_EDGE 0x10 200C AO_FRAMING (r/w) POLARITY 0x10 2010 AO_FREQ (r/w) 0x10 2014 AO_BASE1 (r/w) 0x10 2018 AO_BASE2 (r/w) 0x10 201C AO_SIZE (r/w) 0x10 2020 AO_CC (r/w) 0x10 2024 ...

Page 146

... INTEN bit are as- serted. Interrupts are sticky, i.e. an interrupt remains as- serted until the software explicitly clears the condition flag by an ACK_x action. Philips Semiconductors Description ple to be transmitted. • buffer 2 will contain the next sample (1 after RESET). ...

Page 147

... Philips Semiconductors Table 9-12. AO MMIO Control Fields Field Name Description RESET Resets the audio-out logic. See 9.10, “Audio Out Operation” tion of the recommended procedure. TRANS_ENABLE Transmission Enable flag. 0 (RESET default) AO inactive transmits samples and acts as DMA master to read samples from local SDRAM. ...

Page 148

... If an HBE error occurs, the last valid sample or sample pair is repeated until the AO hardware retrieves a new 1 request every sample buffer across the highway. 166,667 ns 1 request every 111,111 ns 1 request every 166,667 ns 1 request every 55,556 ns Philips Semiconductors ...

Page 149

SPDIF Out 10.1 SPDIF OUT OVERVIEW The TM1300 SPDIF Output unit (SPDO) allows genera- tion of a 1-bit high-speed serial data stream. The primary application is to make SPDIF (Sony/Philips Digital Inter- face) data available for use by external audio ...

Page 150

... SPDO clock cycle as determined by the settings of the DDS (see Programming”). Figure 10-3 illustrates the transmission format of 8-bit data value “10011000”, as well as the transmission for- mat of the 3 pre-ambles. Note that each pre-amble al- Philips Semiconductors sub-frame 1 W sub-frame 2 M sub-fram frame 1 ...

Page 151

... Philips Semiconductors “1” “0” “0” “1” “1” UI cell B bi-phase mark violation M bi-phase mark violation W bi-phase mark violation Figure 10-3. Bi-phase mark data transmission ways starts with a rising edge. This is made possible thanks to the presence of the parity bit, which always guarantees an even number of ‘ ...

Page 152

... The timestamp can be read in the DMA interrupt handler as MMIO register SPDO_TSTAMP. Its contents corre- sponds to the (synchronized) clock edge at which the last bit in the DMA buffer was sent across the output signal pin. Philips Semiconductors Section for a description of ...

Page 153

... Philips Semiconductors MMIO_base offset: 0x10 4C00 SPDO_STATUS (r/ 0x10 4C04 SPDO_CTL (r/w) RESET TRANS_ENABLE TRANS_MODE LITTLE_ENDIAN 0x10 4C08 SPDO_FREQ (r/w) 0x10 4C0C SPDO_BASE1 (r/w) 0x10 4C10 SPDO_BASE2 (r/w) 0x10 4C14 SPDO_SIZE (r/w) 0x10 4C18 SPDO_TSTAMP (r/o) Figure 10-4. SPDO unit status/control field MMIO layout. 10.14 MMIO REGISTER DESCRIPTION Table 10-4. SPDO_STATUS MMIO register fi ...

Page 154

... Refer to Section 10.13, “Timestamps.” 10-6 PRODUCT SPECIFICATION Philips Semiconductors 10.15 RESET The SPDO block is reset by global TM1300 reset pin TRI_RESET writing a ‘1’ to the RESET bit in SPDO_CTL. The SPDO block is not affected by DSPCPU reset initiated though the PCI block BIU_CTL register ...

Page 155

... Philips Semiconductors Table 10-6. SPDO block highway latency requirements f Max. latency s (nSec) (kHz) 32.000 31250 44.100 22675 48.000 20833 10.18 LITERATURE REFERENCES [1] IEC-958 Digital Audio Interface, Part 1: General; Part 2: Professional applications; Part 3: Consumer applica- tions. [2] ‘Interface for non-PCM encoded Audio bitstreams ap- plying IEC958’, Philips Consumer Electronics, June 6 1997 ...

Page 156

... TM1300 Data Book 10-8 PRODUCT SPECIFICATION Philips Semiconductors ...

Page 157

PCI Interface 11.1 NEW IN TM1300 TM1300 DMA read transactions use the more efficient ‘memory read multiple’ PCI transactions, unless explicit- ly disabled. Section 11.7.5. TM1300 contains an on-board PCI_CLK generator for low-cost configurations. It can be enabled/disabled at boot ...

Page 158

... Explicit writes are not al- lowed and may cause undetermined results and/or data corruption. 11-2 PRODUCT SPECIFICATION Philips Semiconductors 11.3.2 I/O Operations Explicit programming by DSPCPU software is the only way to perform transactions to PCI I/O space. DSPCPU software writes three MMIO registers in the following se- quence: 1 ...

Page 159

... Philips Semiconductors The PCI interface begins the PCI-bus transactions when software writes to DMA_CTL. As with the I/O and config- uration operations, the BIU_STATUS and BIU_CTL reg- isters monitor the status of the operation and control in- terrupt signaling. The fully detailed description of the steps needed to start a DMA transaction can be found in “ ...

Page 160

... Interrupt Pin (0x01) Key sp Set by software if aperture size allows s Set by hardware from boot EEPROM Wait PAR SERR# Philips Semiconductors ...

Page 161

... Philips Semiconductors Table 11-2. Field values for Command Register Field Value Explanation I/O Hardwired to 0 (ignore I/O space accesses recognition of memory-space accesses 1 recognizes memory-space accesses EM 0 cannot act as PCI initiator 1 can act as PCI initiator SC Hardwired to 0 (ignore special cycle accesses) MWI 0 cannot generate memory write and invalidate ...

Page 162

... This field only matters when the MWI bit in configuration space is set. The value of the Cache Line Size register specifies the host system cache line size in units of 32- 15 Subclass Code Philips Semiconductors Revision ID Register Product description TM1300 original mask - tm1f 1.0 TM1300 1st metal revision - tm1f 1.1 TM1300 2nd metal revision - tm1f 1 ...

Page 163

... Philips Semiconductors Table 11-6. Base Class Encodings Base Class Meaning (in hex) 00 Device was built before class code definitions were finalized 01 Mass-storage controller 02 Network controller 03 Display controller 04 Multimedia device 05 Memory controller 06 Bridge device 07 Simple communications controller 08 Base system peripheral 0A Docking station 0B Processor 0C Serial bus controller 0D– ...

Page 164

... DRAM Base Address MMIO Base Address Philips Semiconductors 21 bytes). The host BIOS The PCI are writable and which are set to ‘0’ ...

Page 165

... Philips Semiconductors location of these bits is described in tailed EEPROM Contents.” A legal Vendor ID must be obtained from the PCI SIG. The vendor is free to assign subsystem ID’s. 11.6.13 Expansion ROM Base Address Register The Expansion ROM Base Address register is similar in purpose to the SDRAM and MMIO Base Address regis- ters ...

Page 166

... CR (PCI Clear Reset PCI Address PCI Data DN Configuration Data I/O Address I/O Data Source Address Destination Address T D Philips Semiconductors Done PCI-to-SDRAM Busy Done dma_cycle Busy Done io_cycle Busy Done config_cycle Busy ...

Page 167

... Philips Semiconductors while a request of similar type is in progress, the PCI in- terface ignores the second command and sets the ap- propriate error bit in the status register. When the DSPCPU issues either an io_cycle or config_cycle request while a previous request of either type is already in progress, the PCI interface sets bit 8 in BIU_STATUS ...

Page 168

... DN bit—can be asserted during a given configuration cycle. 11.7.9 CONFIG_DATA Register The 32-bit CONFIG_DATA register is used by the DSPCPU to buffer data for a configuration cycle. When TM1300 is acting as the host CPU, it must configure the Philips Semiconductors with the signal Sec- for more infor- ...

Page 169

... Philips Semiconductors PCI bus and devices. The DSPCPU writes or reads CONFIG_DATA depending on whether it is performing a write or read to a PCI device’s configuration space. See Section 11.7.10, “CONFIG_CTL Register,” formation on initiating configuration cycles. 11.7.10 CONFIG_CTL Register The DSPCPU writes to CONFIG_CTL to trigger a config- uration read or write cycle on the PCI bus. A PCI config- uration read or write should not be performed during an ongoing PCI I/O read or write ...

Page 170

... The PCI interface then drives the address from DEST_ADR and the data from r_buffer to the SDRAM controller. SRC_ADR and DEST_ADR are incremented, the TL field in DMA_CTL Philips Semiconductors (shows the interpretation of the D Data Movement Direction PCI memory space (DMA write) ...

Page 171

... Philips Semiconductors is decremented, and this sequence repeats until TL reaches ‘0’. At the end of the PCI SDRAM block transfer, the PCI interface will generate a DSPCPU interrupt if the appro- priate IntE bit is set in BIU_CTL. Alternatively, DSPCPU software can poll the appropriate ‘done’ status bit in BIU_STATUS ...

Page 172

... Finally, the target acknowledges the last data phase by deasserting trdy# and devsel Data 1 Data 2 Data 3 Data 4 Byte Enables Philips Semiconductors Address Data Byte Enables Command Figure 11-12. The Figure 11-12, a fast device is re- when it deasserts frame# in clock 17. The ...

Page 173

... Philips Semiconductors 1 2 pci_clk frame# ad Address c/be# Command irdy# trdy# devsel# Figure 11-13. Back-to-back PCI burst write operations with 16 data phases which might be generated by the ICP when writing image data to a PCI-resident video frame buffer. Figure 11-13 illustrates back-to-back DMA burst data transfers ...

Page 174

... TM1300 Data Book 11-18 PRODUCT SPECIFICATION Philips Semiconductors ...

Page 175

SDRAM Memory System 12.1 NEW IN TM1300 • Support of 64-Mbit SDRAMs organized in x16 and 128-Mbit organized in x32. • Partial support of 64-Mbit SDRAMs organized in x8 and 128-Mbit SDRAMs organized in x16. • External MM_MATCHOUT to MM_MATCHIN ...

Page 176

... Refer to the TM1100 Databook for smaller memory con- figurations. Note: • Some of these configurations may not be economi- cally attractive due to the price premium. • ‘Max. MHz’ refers to the memory interface/SDRAM speed, not the TM1300 core operating frequency. Philips Semiconductors CS# SDRAM Memory Address, Control Array ...

Page 177

... Philips Semiconductors MMIO_base offset: 0x10 0100 MM_CONFIG (r/o) 0x10 0300 PLL_RATIOS (r/o) Figure 12-2. Memory interface configuration registers. External Clock Input TRI_CLKIN Memory System Clocks MM_CLK1 MM_CLK0 Figure 12-3. TM1300 memory and core PLL connections. 12.6 MEMORY SYSTEM PROGRAMMING Memory system parameters are determined by the con- tents of two configuration registers, MM_CONFIG and PLL_RATIOS ...

Page 178

... SDRAM PLL (TM1300’s 7 Reserved external input clock). A value of ’0’ causes normal oper- ation, and the memory system is clocked by the output of the SDRAM PLL. Philips Semiconductors Function 0 1:1 1 2:1 2 3:2 3 ...

Page 179

... Philips Semiconductors 12.7 MEMORY INTERFACE PIN LIST The memory interface consists of 61 signal pins includ- ing clocks (but excluding power and ground pins). Table 12-7 lists the interface signal pins. Table 12-7. Memory Interface Signal Pins Name Function MM_CLK[1:0] Memory bus clock MM_CS#[3..0] Chip selects for the four ...

Page 180

... General Guidelines • In general, TM1300 and its memory chips should be as close together as possible to minimize parasitic Philips Semiconductors Table 12-7), can lists the clock frequency as a function of the shows a conceptual circuit board layout. ...

Page 181

... Philips Semiconductors TM1300 TM1300 Memory Interface DSPCPU Data Highway On-Chip Peripherals Figure 12-4. Conceptual board layout. Table 12-11. Glueless interface limits for address/ clocks Memory Chips Maximum Clock Frequency 4 143 MHz 6 133 MHz 8 133 MHz capacitance. Close proximity is especially important for a 143-MHz memory system. ...

Page 182

... RP a 16-, 32-, 48- or 64-MB memory systems. TM1300 2 512K 16 SDRAM MM_DQ[31:16] CLK DQ[15:0] Address UDQM Control LDQM CS# 2 512K 16 SDRAM MM_DQ[15:0] CLK DQ[15:0] Address UDQM Control LDQM CS# Philips Semiconductors Description Symbol Clocks t RRD t RCD t WR shows a 4-MB memory system. Figure 12-6 MM_DQM[3] MM_DQM[2] MM_DQM[1] MM_DQM[ ...

Page 183

... Philips Semiconductors MM_CLK[1] MM_CS#[1] MM_CLK[1] MM_CS#[1] MM_CLK[0] MM_CS#[0] MM_CLK[0] MM_CS#[0] Figure 12-6. Schematic of a 32-MB memory system consisting of four SDRAM chips (two ranks) details a 32-MB memory system. Removing the device controlled by MM_CS#[1] makes a 16-MB system. 64- TM1300 BA[1:0] SDRAM MM_DQ[31:16] CLK DQ[15:0] Address[11:0] MM_DQM[3:2] Control DQM[1:0] ...

Page 184

... SDRAMs organized in x16 and x32 could be mixed in or- der to create, for example ( memory sys- tem. 12-10 PRODUCT SPECIFICATION TM1300 4 512K 32 SDRAM BA[1:0] CLK DQ[31:0] Address[10:0] DQM[3:0] Control CS# Finally x8 devices could be used to build a 32-MB mem- ory system as illustrated in Philips Semiconductors Figure 12-9. Note that due to ...

Page 185

... Philips Semiconductors MM_CLK[1] MM_CS#[0] MM_CLK[0] MM_CS#[1] Figure 12-8. Schematic of a 16-MB memory system consisting of two ranks of 4 512K 32 SDRAM chips. TM1300 4 512K 32 BA[1:0] SDRAM MM_DQ[31:0] CLK DQ[31:0] Address[10:0] MM_DQM[3:0] Control DQM[3:0] CS# 4 512K 32 BA[1:0] SDRAM MM_DQ[31:0] CLK DQ[31:0] Address[10:0] MM_DQM[3:0] Control DQM[3:0] CS# PRODUCT SPECIFICATION SDRAM Memory System ...

Page 186

... Control DQM] CS# GND BA[1:0] SDRAM CLK DQ[7:0] Address[11:0] Control DQM] CS# GND BA[1:0] SDRAM CLK DQ[7:0] Address[11:0] Control DQM] CS# GND abling a 32-MB memory system to be built (cannot be ex- tended using the other MM_CS# pins). Refer to Philips Semiconductors MM_DQ[31:24] MM_DQM[3] MM_DQ[23:16] MM_DQM[2] MM_DQ[15:8] MM_DQM[1] MM_DQ[7:0] MM_DQM[0] ...

Page 187

... Philips Semiconductors Figure 12-10 for a more detailed connection scheme. MM_CONFIG.SIZE must be set to 6 (i. rank MM_CLK[0] MM_CLK[1] Figure 12-10. Schematic of a 32-MB memory system consisting of two SDRAM chips (one rank) scribed for the 128-Mbit SDRAMs organized in x16 can also be used to connect 64-Mbit SDRAM devices orga- ...

Page 188

... TM1300 Data Book MM_CLK[1] MM_CS#[0] MM_CLK[0] MM_CS#[1] Figure 12-11. Schematic of a 32-MB memory system consisting of two ranks SDRAM chips. 12-14 PRODUCT SPECIFICATION TM1300 BA[1:0] SDRAM MM_DQ[31:0] CLK DQ[31:0] Address[11:0] MM_DQM[3:0] Control DQM[3:0] CS BA[1:0] SDRAM MM_DQ[31:0] CLK DQ[31:0] Address[11:0] MM_DQM[3:0] Control DQM[3:0] CS# Philips Semiconductors ...

Page 189

System Boot 13.1 NEW IN TM1300 A new bit in the boot EEPROM allows an internal PCI_CLK clock source for low-cost standalone systems 13.2 TM1300 BOOT SEQUENCE OVERVIEW Before a TM1300 system can begin operating, the main- memory interface (MMI) ...

Page 190

... PCI configuration space register at offset 0x2C to pro- vide the 16-bit Subsystem ID and Subsystem Vendor ID values. These values are used by driver software to dis- tinguish the board vendor and product revision informa- tion for multiple board products based on the TM1300 chip. Refer to Philips Semiconductors Size Interpretation 1 bit 0 128 lines ...

Page 191

... Philips Semiconductors system Vendor ID Register,” for more information on the choice of values. 2 Table 13-3I C speed as a function of EEPROM byte 0 BOOT_CLK EEPROM divider bits speed bit value 00 (100 MHz) 0 (100 KHz) 1008 00 1 (400 KHz) 256 01 (75 MHz) 0 (100 KHz) 752 01 1 (400 KHz) ...

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... Boot System boot halts (Host driver will complete the boot procedure) Figure 13-2. Flow chart of system boot procedure for both host-assisted and autonomous configurations. 13-4 PRODUCT SPECIFICATION Philips Semiconductors 8-bit serial read Save 11-bit byte count 64-bit serial read Write to MMIO space: MMIO_BASE ...

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... Philips Semiconductors 13.3.2 Initial DSPCPU Program Load for Autonomous Bootstrap In a system where TM1300 serves as the host CPU, the system boot block performs an autonomous boot proce- dure. For an autonomous boot, the system boot block reads all the information described in “Boot Procedure Common to Both Autonomous and Host-Assisted Bootstrap,” ...

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... DSPCPU from its re- set state by a write to the BIU_CTL register with the CR bit set. See DSPCPU and host both running, the TM1300 bootstrap process is complete. Philips Semiconductors of MMIO_BASE and Section 11.6.11, for a more complete discus- n -byte-aligned boundary. ...

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... Philips Semiconductors 13.5 DETAILED EEPROM CONTENTS Table 13-5 shows the serial EEPROM contents needed for an autonomous boot procedure. For the host-assisted Table 13-5. Serial boot EEPROM contents Line bit 7 bit 6 SDRAM size[2:0] #lines 0: 128 lines 0 1: 256 or more lines — — ...

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... DSPCPU bootstrap program (bits [7:0] of last 32-bit word, stored at DRAM_BASE + n – 4) +47 13-8 PRODUCT SPECIFICATION Data Byte bit 5 bit 4 bit 3 DRAM_CACHEABLE_LIMIT value [31:24] DRAM_CACHEABLE_LIMIT value [23:16] DRAM_CACHEABLE_LIMIT value [15:8] DRAM_CACHEABLE_LIMIT value [7:0] repeat of DRAM_BASE value [31:24] repeat of DRAM_BASE value [23:16] repeat of DRAM_BASE value [15:8] repeat of DRAM_BASE value [7: Philips Semiconductors bit 2 bit 1 bit 0 ...

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... Philips Semiconductors 13.6 EEPROM ACCESS PROTOCOLS Figure 13-3 shows the SDA (serial data) line protocols for three types of read accesses supported by I EEPROMs. A read from the address currently latched in- side the EEPROM can be for either a single byte or for an arbitrary series of sequential bytes. The master makes the choice by setting the ACK bit after a byte has been transferred ...

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... TM1300 Data Book 13-10 PRODUCT SPECIFICATION Philips Semiconductors ...

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Image Coprocessor 14.1 IMAGE COPROCESSOR OVERVIEW The Image Coprocessor (ICP) connects to the TM1300 on-chip data highway to perform SDRAM block read and write actions. It also connects to the PCI interface to al- low block write transactions across PCI. ...

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... Microprogram Control Unit Figure 14-2. Image coprocessor block diagram 14-2 PRODUCT SPECIFICATION SDRAM Memory Controller SDRAM Highway I$ D$ PCI Master/Slave Interface PCI Local Bus 5-tap Filter Overlay Bit Mask To SDRAM Image Coprocessor Philips Semiconductors TM1300 VLD Coprocessor Video Out Interface SSI Image coprocessor ...